Ge Outdiffusion Research Articles

On the dc and noise properties of the gate current in epitaxial Ge p-channel metal oxide semiconductor field effect transistors with TiN∕TaN∕HfO2∕SiO2 gate stack

In this paper, we report the dc and noise properties of the gate current in epitaxial Ge p-channel metal oxide field effect transistors (pMOSFETs) with a Si passivated surface. The gate stack consists of HfO2∕SiO2 dielectric with TiN∕TaN metal gate. The observed temperature dependence of the gate current indicates that the dominant charge transport mechanism through the gate dielectric consists of Poole–Frenkel conduction. Gate current 1∕f noise is more than two orders higher in the case of Ge pMOSFETs when compared to reference Si pMOSFETs. Ge outdiffusion into the gate oxide is the suspected cause for the enhanced Poole–Frenkel conduction and the high gate current 1∕f noise in Ge pMOSFETs.

Investigation of Impact Ionization in Strained-Si n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

In this study, we have systematically re-investigated impact ionization (II) characteristics in strained-Si n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) with different strained-Si cap layers at two Ge contents. The strained-Si nMOSFETs can supply further II experimental conditions with band-gap energy narrowing, higher electron mobility, and greater scattering caused by the Ge out-diffusion effect. Despite such II conditions, no marked difference in the II multiplication coefficient as a function of drain voltage, M-1(VD), between unstrained- and strained-Si nMOSFETs is found for widely accepted strain-enhanced II efficiency, implying that II efficiency depends on the maximum channel electric field Em in the pinch-off region. Through the translation of M-1(VD) into M-1(Em), it is found that strain-enhanced II efficiency is attributed to the narrowing of band-gap energy, taking into account the difference in source/drain junction depth between unstrained- and strained-Si nMOSFETs.

Investigation of Effect of Germanium on the Crystallization Process of Hafnium Aluminum Oxide Matrix

Germanium (Ge) nanocrystals have been successfully synthesized in the hafnium aluminum oxide (HfAlO) matrix via co-sputtering and furnace annealing. The crystallization process of the HfAlO film has been studied using a combination of Raman spectroscopy, transmission electron microscopy, secondary ions mass spectrometry and X-Ray diffraction techniques. It was found that 800{degree sign}C is the ideal annealing temperature for synthesis of Ge nanocrystals in HfAlO matrix. A higher the annealing temperature will result in significant Ge outdiffusion and thus no formation of the nanocrystals. In addition, for the sample with relatively high Ge content (~23.3%) in the HfAlO matrix, a noteworthy Ge outdiffusion and the crystallization of the film were observed even upon the annealing at 800{degree sign}C. The crystallographic phase of the film was found to favor the orthorhombic phase.

Synthesis of germanium nanocrystals in hafnium aluminum oxide matrix

An examination on the effect of annealing temperature and duration, and the germanium (Ge) concentration on the growth of Ge nanocrystals in hafnium aluminum oxide (HfAlO) matrix, was carried out using a combination of Raman spectroscopy, transmission electron microscopy, and secondary ions mass spectrometry techniques. We found Ge nanocrystals in the HfAlO matrix with a Ge content of 10.5 at. % when annealed at 800 °C. At a relatively higher content of Ge at 23.3 at. % in HfAlO film, a significant outdiffusion of Ge at the film surface or diffusion into the Si substrate occurred, and this imposes a narrow annealing condition for the formation of nanocrystals. We attribute the different nanocrystal formation characteristics in the HfAlO and silicon oxide matrices to the difference crystallization temperatures of HfAlO and silicon oxide films.

Study of Thermal Stability of HfOxNy ∕ Ge Capacitors Using Postdeposition Annealing and NH3 Plasma Pretreatment

We studied the thermal stability of the as-deposited thin films on the Ge substrate by employing rapid thermal annealing. After undergoing high-temperature processing, we observed several interesting physical and electrical features presented in the system, including a large Ge out-diffusion ( atom %) into high- films, positive shift of the flatband voltage, severe charge trapping, and increased leakage current. These phenomena are closely related to the existence of defective layer and the degree of resultant GeO volatilization. We abated these undesirable effects, especially for reducing the amount of Ge incorporation ( atom %) and the substoichiometric oxide at dielectric-substrate interface, through performing plasma pretreatment on the Ge surface. These improvements can be interpreted in terms of a surface nitridation process that enhanced the thermal stability of the high- interface. In addition, we measured that the conductance loss in inversion was still high and it revealed independence with respect to gate bias, reflecting the fact that the minority carriers in Ge can rapidly respond either through a diffusion mechanism or through midgap trap states residing in Ge bulk substrates.

Improved Current Drivability and Gate Stack Integrity using Buried SiC Layer for Strained Si/SiGe Channel Devices

We report a novel Si/Si1-xGex channel with improved current drivability and reliability using a buried Si0.99C0.01. It is also found that the Si/Si1-xGex/Si0.99C0.01 structure is effective in reducing Ge out-diffusion which helps to improve gate dielectric interface quality.

Ge out-diffusion effect on low-voltage tunnelling current in strained-Si nMOSFETs

Ge out-diffusion effect on low-voltage tunnelling current is investigated using strained-Si nMOSFETs with different strained-Si layers. In a low gate voltage region (−1 V<VG<0 V), excess tunnelling current increases with reduced strained-Si layer thickness. In addition, change of the reciprocal effective electron mobility is found to be proportional to the increase in the low-voltage tunnelling current, which is attributed to the increase in strained-Si/SiO2 interface states caused by the presence of Ge out-diffusion and pileup at strained-Si/SiO2.

Ultrathin Si capping layer suppresses charge trapping in HfOxNy∕Ge metal-insulator-semiconductor capacitors

In this study the authors investigated the Ge outdiffusion characteristics of HfOxNy∕Ge metal-insulator-semiconductor capacitors to determine their charge trapping behavior. Capping the Ge substrate with an ultrathin Si layer inhibits the incorporation of Ge into the high-k bulk dielectric in the form of GeOx, thereby diminishing the resultant oxide charge trapping. The thermal stability of the entire capacitor structure was also improved after performing an additional Si passivation process.

Low-Frequency Noise Characteristics in Strained-Si nMOSFETs

The low-frequency (LF) (1/f) noise mechanism of strained-Si nMOSFETs grown on relaxed Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> virtual substrates (VSs) has been investigated. It is found that the Si-cap thickness plays an important role in characterizing the 1/f noise mechanism. Ge out-diffusion effect and slight strain relaxation in Si-cap layer are responsible for the degradation of 1/f noise in strained-Si device with 10- and 20-nm-thick Si-cap, respectively. In addition, by choosing proper Si-cap thickness, experimental result shows that as Si-cap undergoes stronger tensile strain for higher Ge concentration VS, the correlated mobility fluctuation term in the modified carrier-number fluctuation model is more dominated for the 1/f noise

Germanium MOS technology for infra-red detectors

Fabrication of an electrically stable dielectric is a key enabling technology in the production of a Ge detector with enhanced response in the near infra-red spectrum. This work investigates the physical and electrical properties of silicon dioxide (SiO 2) dielectrics deposited on Ge substrates. The deposited SiO 2 (silox) layers have been densified at 600 and 800 °C. Significant Ge outdiffusion from the substrate into the densifying silox layer has been observed for the 800 °C process, and the diffusivity has been estimated as 1.5×10 −4 μm 2/min. The C– V characteristics of Ge MOS capacitors incorporating this silox dielectric display the onset of ‘low frequency’ operation at a relatively high frequency of 100 kHz, and the capacitor C– t response suggests that Ge carrier lifetime is much shorter than that measured for Si MOS capacitors. These phenomena are shown to result from the narrow band gap of Ge, and this work therefore emphasises that increased cooling will be required to exploit the infra-red detector properties of a practical Ge device.

Impact of strained-Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs

Surface channel strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrates (VSs) have been established as an attractive avenue for extending Si CMOS performance as dictated by Moore's law. The performance of a surface channel Si n-MOSFET is significantly influenced by strained Si/SiO/sub 2/ interface quality. The effects of Ge content (20, 25, and 30%) in the VS and strained-Si thickness (6, 5.5, 4.7, and 3.7 nm) on the strained Si/SiO/sub 2/ interface have been investigated. The interface trap density was found to be proportional to the Ge content in the VS. Fixed oxide charge density reduces to a lower limit at higher strained-Si thickness for any Ge content in the VS, and the value increases as the strained-Si thickness is reduced. There is a high concentration of interface trap charge and fixed oxide charge present for devices with a strained-Si channel thickness below 4.7 nm. To investigate the effect of strained Si/SiO/sub 2/ interface quality on MOSFET devices fabricated using a high-temperature CMOS process, the performance of surface channel n-MOSFETs has been correlated with channel thickness. It is noted that the drain-current rapidly decreases at low gate voltages for channel thicknesses less than 4.7 nm. The performance of both MOS capacitors and MOSFETs degraded below a strained-Si thickness of 4.7 nm irrespective of the Ge content in the VS even up to 30%. TCAD simulations have been carried out to analyze the effect of strained Si/SiO/sub 2/ interface on electrical characteristics. Performance degradation in thin strained-Si channels is primarily attributed to gate oxide quality. The out-diffused Ge accumulates at the strained Si/SiO/sub 2/ interface, introducing a significant amount of interface traps and fixed oxide charges during thermal oxidation. Interface trap density and fixed oxide charge density significantly increased when the Ge concentration at the surface becomes more than 6%. This paper suggests that a minimum strained-Si layer thickness of /spl sim/ 5.0 nm is required to achieve a good strained Si/SiO/sub 2/ interface quality for surface channel strained-Si n-MOSFETs, fabricated using a high thermal budget CMOS process.

Ge out-diffusion and its Effect on Electrical Properties in s-Si/SiGe Devices

AbstractIn this paper we report on the quantification of Ge diffusion in strained Si/SiGe (s-Si/SiGe) structures for different Ge content in the SiGe virtual substrate. Using TCAD tools, the diffusivity has been calculated by varying pre-exponential factor and activation energy for Ge diffusion in s-Si and SiGe layers separately and obtaining a fit to the SIMS profiles. We observe an exponential and a linear dependence of pre-factor and activation energy for Ge diffusion in s-Si and SiGe, respectively, which is in agreement with literature. As a result of diffusion, the carrier confinement in thin strained layer reduces and the mobility is affected. Using C-V measurements on MOS capacitors fabricated along with devices, a shift in the flat band voltage has been observed and is attributed to a change in the interface trapped and fixed oxide charge. We observe a stronger effect of the variation of strained layer thickness than Ge content on the change in the flatband voltage. This observation is consistent with an exponential increase in Ge arriving at the interface with decrease in strained layer thickness.

Thermal Stability of Thin Virtual Substrates for High Performance Devices

AbstractDetailed investigations of strain generation and relaxation in Si films grown on thin Si0.78Ge0.22 virtual substrates using Raman spectroscopy are presented. Good virtual substrate relaxation (&gt;90%) is achieved by incorporating C during the initial growth stage. The robustness of the strained layers to relaxation is studied following high temperature rapid thermal annealing typical of CMOS processing (800-1050 °C). The impact of strained layer thickness on thermal stability is also investigated. Strain in layers below the critical thickness did not relax following any thermal treatments. However for layers above the critical thickness the annealing temperature at which the onset of strain relaxation occurred appeared to decrease with increasing layer thickness. Strain in Si layers grown on thin and thick virtual substrates having identical Ge composition and epilayer thickness has been compared. Relaxation through the introduction of defects has been assessed through preferential defect etching in order to verify the trends observed. Raman signals have been analysed by calibrated deconvolution and curve-fitting of the spectra peaks. Raman spectroscopy has also been used to study epitaxial layer thickness and the impact of Ge out-diffusion during processing. Improved device performance and reduced self-heating effects are demonstrated in thin virtual substrate devices when fabricated using strained layers below the critical thickness. The results suggest that thin virtual substrates offer great promise for enhancing the performance of a wide range of strained Si devices.

Nickel Germanosilicide Contacts Formed on Heavily Boron Doped&amp;lt;tex&amp;gt;$rm Si_1-xrm Ge_x$&amp;lt;/tex&amp;gt;Source/Drain Junctions for Nanoscale CMOS

Formation of source/drain junctions with a small parasitic series resistance is one of the key challenges for CMOS technology nodes beyond 100 nm. A new source/drain technology based on selective deposition of heavily in situ doped Si/sub 1-x/Ge/sub x/ layers was recently developed in this laboratory. This paper presents formation and structural characterization of self-aligned nickel germanosilicide contacts formed on heavily boron doped Si/sub 1-x/Ge/sub x/ alloys. The results show that thin NiSi/sub 1-x/Ge/sub x/ contacts with a resistivity of /spl sim/25 /spl mu//spl Omega/-cm can be formed on Si/sub 1-x/Ge/sub x/ alloys at temperatures as low as 350/spl deg/C. However, the low resistivity and the structural integrity of the NiSi/sub 1-x/Ge/sub x/ films can be maintained up to a maximum temperature of 450/spl deg/C. At higher temperatures, Ge out-diffusion from NiSi/sub 1-x/Ge/sub x/ grains results in interface roughening and NiSi spikes. If the maximum processing temperature is kept within 400/spl deg/C, p/sup +/-n junctions with excellent leakage behavior can be formed. A minimum contact resistivity of 2/spl times/10/sup -8/ /spl Omega/-cm/sup 2/ is demonstrated for Ge concentrations above /spl sim/40%, which can be linked to the smaller semiconductor bandgap and high boron activation under the metal contact. The results suggest that NiSi/sub 1-x/Ge/sub x/ contacts formed on Si/sub 1-x/Ge/sub x/ junctions have the potential to satisfy the contact resistivity requirements of future CMOS technology nodes.

Formation of Nickel Silicide Layer on Strained-Si0.83Ge0.17/Si(001) using a Sacrificial Si Layer and its Morphological Instability

Nickel silicide was formed on strained-Si0.83Ge0.17/Si(001) using a sacrificial Si capping (cap-Si) layer and its morphological characteristics were investigated. Nickel silicide layers were grown by rapid thermal annealing of the samples with the structure of Ni (\\cong14 nm)/cap-Si (\\cong26 nm)/Si0.83Ge0.17/Si(001) at the annealing temperature (TA) range of 400–800°C. The phase formation, surface and interfacial morphologies, and electrical properties of the resulting samples were characterized by various measurement techniques, including X-ray diffraction, atomic force microscopy, scanning electron microscopy, Auger electron spectroscopy, cross-sectional transmission electron microscopy, and the four-point probe method. The results showed the formation of a uniform layer nickel monosilicide (NiSi) with a thickness of \\cong30 nm at 400–550°C and sheet resistance values of 6.5–7.9 Ω/□. The sheet resistance values of the samples annealed at TA≥600°C were found to be increased, however, and this is attributed to the agglomeration of nickel monosilicide leading to discrete large-size NiSi grains. Microstructural and chemical analyses of the samples annealed at elevated temperature, TA≥750°C, indicated the formation of large agglomerated NiSi grains penetrating into the Si0.83Ge0.17/Si(001) structure and the conversion of the cap-Si layer situated in between the nickel silicide grains into an Sil-uGeu layer (u \\cong0.01–0.03), due to the out-diffusion of Ge from the SiGe layer during agglomeration. However, no NiSi2 phase was observed at these elevated annealing temperatures.

Relaxed silicon–germanium-on-insulator fabricated by oxygen implantation and oxidation-enhanced annealing

The application of separation-by-implantation-of-oxygen (SIMOX) for silicon–germanium-on-insulator (SGOI) fabrication is always limited by the Ge loss caused by the high temperature annealing. A unique SIMOX method was introduced to fabricate SGOI and resolve the problem of Ge loss. During the process, a SiO2 layer was formed pre-annealing to block the Ge out-diffusion. As the x-ray rocking curve and Raman spectra studies show, the Ge fraction of the SGOI was improved to 17 at.%. The final sample exhibits a planar and continuous buried oxide layer, sharp interfaces and a defect free top SiGe layer as the cross-sectional transmission-electron- microscopy (XTEM) and secondary-ion-mass-spectrometry studies show. The Rutherford backscattering spectroscopy demonstrated that the superficial SiGe layer was superior in quality (derived channelling yield of 10%). The results indicate that the additional step of thermal oxidation pre-annealing is vital to resolve the problem of Ge loss and the modified SIMOX process is applicable for SGOI fabrication.

Improved hole mobilities and thermal stability in a strained-Si∕strained-Si1−yGey∕strained-Si heterostructure grown on a relaxed Si1−xGex buffer

A dual channel heterostructure consisting of strained-Si∕strained-Si1−yGey on a relaxed Si1−xGex buffer (y&amp;gt;x), provides a platform for fabricating metal–oxide–semiconductor field-effect transistors with high hole mobilities. Ge outdiffusion during high temperature processing steps from the strained-Si1−yGey layer into the relaxed Si1−xGex buffer reduces the hole mobilities in these heterostructures. We present a strained-Si∕strained-Si1−yGey∕strained-Si heterostructure on relaxed Si1−xGex, in which the strained-Si layer between the strained-Si1−yGey and relaxed Si1−xGex reduces Ge outdiffusion. Improved hole mobilities in this heterostructure are also observed over similar dual channel heterostructures which could be a result of better hole confinement in the strained-Si1−yGey layer of the proposed heterostructure.

Alternative surface passivation on germanium for metal-oxide-semiconductor applications with high-k gate dielectric

An alternative surface passivation process for high-k Ge metal-oxide-semiconductor (MOS) device has been studied. The surface SiH4 annealing was implemented prior to HfO2 deposition. X-ray photoelectron spectroscopy analysis results show that the SiH4 surface passivation can greatly prevent the formation of unstable germanium oxide at the surface and suppress the Ge out-diffusion after the HfO2 deposition. The electrical measurement shows that an equivalent oxide thickness of 13.5Å and a leakage current of 1.16×10−5A∕cm2 at 1V gate bias was achieved for TaN∕HfO2∕Ge MOS capacitors with the SiH4 surface treatment.

Ge Outdiffusion Effect on Flicker Noise in Strained-Si nMOSFETs

The flicker noise characteristics of strained-Si nMOSFETs are significantly dependent on the gate oxide formation. At high temperature (900/spl deg/C) thermal oxidation, the Si interstitials at the Si/oxide interface were injected into the underneath Si-SiGe heterojunction, and enhanced the Ge outdiffusion into the Si/oxide interface. The Ge atoms at Si/oxide interface act as trap centers, and the strained-Si nMOSFET with thermal gate oxide yields a much larger flicker noise than the control Si device. The Ge outdiffusion is suppressed for the device with the low temperature (700/spl deg/C) tetraethylorthosilicate gate oxide. The capacitance-voltage measurements of the strained-Si devices with thermal oxide also show that the Si/oxide interface trap density increases and the Si-SiGe heterojunction is smeared out due to the Ge outdiffusion.

Effect of thermal processing on mobility in strained Si/strained Si1−yGey on relaxed Si1−xGex (x&amp;lt;y) virtual substrates

Annealing effects on hole and electron mobility in dual-channel structures consisting of strained Si and Si1−yGey on relaxed Si1−xGex layers (x=0.3/y=0.6, and x=0.5/y=0.8) were studied. Hole mobility decreases sharply, but electron mobility is quite immune to annealing conditions of 800 °C, 30 min or 900 °C, 15 s. The hole mobility decrease is more severe in dual-channel structures with higher Ge contents. Hole mobility degradation is a direct result of Ge outdiffusion from the Si1−yGey layer, and the resulting decreased Ge content. Ge diffusion preferentially towards the Si1−xGex buffer layer, rather than the Si cap layer, is a reason that electron mobility is highly immune to such annealing.