Abstract
Ge out-diffusion effect on low-voltage tunnelling current is investigated using strained-Si nMOSFETs with different strained-Si layers. In a low gate voltage region (−1 V<VG<0 V), excess tunnelling current increases with reduced strained-Si layer thickness. In addition, change of the reciprocal effective electron mobility is found to be proportional to the increase in the low-voltage tunnelling current, which is attributed to the increase in strained-Si/SiO2 interface states caused by the presence of Ge out-diffusion and pileup at strained-Si/SiO2.
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