Ge-on-insulator Research Articles

Strained single-crystal GOI (Ge on Insulator) arrays by rapid-melting growth from Si (1 1 1) micro-seeds

Liquid-phase epitaxial growth of Ge islands on insulator (GOI) using Ni-imprint-induced Si (1 1 1) micro-crystal seeds (∼1 μm ϕ) is proposed. As a result, single-crystalline GOI (1 1 1) structures with large area (∼10 μm ϕ) are realized. The transmission electron microscopy observations reveal no dislocation or stacking fault in the laterally grown regions. Moreover, the Raman measurements show that the tensile strain (∼0.2%) which enhances the carrier mobility is induced in the growth regions. This new method can be employed to realize the multi-functional SiGe large scale integrated circuits.

Growth-direction-dependent characteristics of Ge-on-insulator by Si–Ge mixing triggered melting growth

The lateral liquid-phase epitaxy of Ge-on-insulator (GOI) using Si seeds has been investigated as a function of the Si-seed orientation and the growth direction. Giant single-crystalline GOI structures with ∼200 μm length are obtained using Si(1 0 0), (1 1 0), and (1 1 1) seeds. The very long growth is explained on the basis of the solidification temperature gradient due to Si–Ge mixing around the seeding area and the thermal gradient due to the latent heat around the solid/liquid interface at the growth front. In addition, growth with rotating crystal orientations is observed for samples with several growth directions. The rotating growth is explained on the basis of the bonding strength between lattice planes at the growth front. This rotating growth does not occur in any direction for (1 0 0) orientated seeds. Based on this finding the mesh-patterned GOI growth with a large area (250 μm × 500 μm) is demonstrated.

Channel direction, effective field, and temperature dependencies of hole mobility in (110)-oriented Ge-on-insulator p-channel metal-oxide-semiconductor field-effect transistors fabricated by Ge condensation technique

This paper experimentally reports the channel direction (θ), effective field (Eeff), and temperature (T) dependencies of hole mobility in (110)-oriented 12-nm-thick accumulation mode Ge-on-insulator (GOI) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) fabricated by the Ge condensation technique. It is found that, the hole mobility on (110)-oriented GOI surfaces increases with the channel direction tilted from ⟨100⟩ to ⟨110⟩ direction, in contrast to (100)-oriented conventional GOI surfaces. By low temperature measurements, the extracted phonon-limited mobilities (μph) of (110)-oriented GOI surfaces along ⟨110⟩ direction occupy 2.1 and 7.1 of enhancement against (100)-oriented GOI and Si surfaces, respectively, at any T. Through physical insights into the present analyses, μph dependence on T−1.8 suggests the suppression of intervalley phonon scattering at low T as in Si. Also, μph is found to increase with Eeff, which can be regarded as an inherent property of hole mobility on (110)-oriented Ge. By further analyses base on the definition of mobility, the effective mass can be a dominant factor for the mobility anisotropy on (110)-oriented GOI pMOSFETs.

Formation and properties of GeOI prepared by cyclic thermal oxidation and annealing processes

Si0.82Ge0.18/SOI prepared by epitaxial growth of SiGe layer on SOI wafer in the ultra-high vacuum chemical vapor deposition is used to fabricate the SiGe on insulator (SGOI) substrate (0.24≤xGe≤1) by the cyclic oxidation and annealing processes. The structure and the optical properties of the SGOI with various Ge content are studied by employing HRTEM, Raman spectroscopy, and photoluminescence (PL) spectroscopy. The variations of Ge component and strain in the oxidation process are analyzed. High crystal quality Ge on insulator (GeOI), with a thickness of 11 nm, is obtained with a flat Ge/SiO2 interface. The direct band transition photoluminescence of the GeOI is observed at room temperature. The photoluminescence peak from GeOI is located at 1540 nm, and the PL intensity increases linearly with exciting power increasing. It is indicated that the formed GOI material has a high crystallization quality and is suitable for the applications in Ge optoelectronic and microelectronic devices.

Characterization of SiGe Layer during Ge Condensation Process by X-ray Diffraction Methods

We fabricated a Ge-on-insulator (GOI) structure by the Ge condensation method and characterized the SiGe layer during the condensation process by X-ray reciprocal space mapping and synchrotron microbeam X-ray diffraction. The crystalline quality of the SiGe layer degraded during the initial 1 h of oxidation at 1050 °C and it also rapidly degraded during 1 h of oxidation at 900 °C immediately before the formation of GOI structures. The slight degradation was caused by annealing in Ar, indicating that the degradation during the initial 1-h condensation is accelerated by Ge atoms being ejected from the oxidized interface.

Defect-free Ge-on-insulator with (100), (110), and (111) orientations by growth-direction-selected rapid-melting growth

Defect-free Ge-on-insulator (GOI) with various crystal orientations is essential to realize high-speed and multifunctional devices. Seeded rapid-melting growth of GOI is investigated as a function of seed-orientations and growth-directions. From (100)-oriented Si seeds, Ge growth with a (100) orientation propagates for all growth-directions, however, rotational-growth is observed for some directions when Si seeds with (110) and (111) orientations are used. Such rotational-growth can be completely suppressed by selecting the growth-directions deviating from ⟨111⟩ by more than 35°. Transmission-electron-microscopy observation shows no-stacking fault and no-dislocations. Consequently, defect-free GOI with (100), (110), and (111) orientation is achieved, which demonstrates high-hole mobility (∼1100 cm2/V s).

(Invited) High-Mobility Ge on Insulator (GOI) by SiGe Mixing-Triggered Rapid-Melting-Growth

High-quality orientation-controlled Ge on insulator (GOI) structures are essential to realize high-performance thin-film transistors (TFTs) and epitaxial templates for multifunctional 3-dimensional large-scale integrated circuits (3D-LSIs). We have investigated the Si-seeding rapid-melting process and demonstrated formation of giant Ge stripes with (100), (110), and (111) orientations on Si (100), (110), and (111) substrates, respectively, covered with SiO2 films. We revealed that crystallization is triggered by Si-Ge mixing in the seeding regions in this process. Based on this mechanism, we have proposed a novel technique to realize orientation-controlled Ge layers on transparent insulating substrates by using Si artificial micro-seeds with (100) and (111)-orientations. This achieved epitaxial growth of single crystalline (100) and (111)-oriented Ge stripes on quartz substrates. The transmission electron microscopy observations revealed no-defects in the laterally grown Ge regions. The Ge layers showed a high hole mobility exceeding 1100 cm2/Vs owing to the high crystallinity. This novel SiGe mixing-triggered growth technique opens up the possibility of the next-generation TFTs and multifunctional 3D-LSIs.

(Invited) Ge/III-V Heterostructures and Their Applications in Fabricating Engineered Substrates

Chip level integration of III-V devices with Si-CMOS platform requires the use of engineered substrates. Fabrication of engineered substrates utilizes technologies such as epitaxy, wafer bonding and layer transfer. We report on two aspects of III-V/IV materials integration developments that are on the path to enabling Ge-on-insulator (GeOI) and GaAs-on-insulator (GaAsOI) on Si substrates without the use of SmartcutTM technology. We report on the establishment of Ge/AlAs/GaAs and GaAs/Ge/GaAs epitaxial structures/sequences with low defect density and surface properties suitable for wafer bonding. The epitaxial structures have embedded layers that offer highly selective etch properties that facilitate lift-off onto Si substrates. We demonstrate the use of these novel Ge/III-V heterostructures to liftoff layers of Ge through an aqueous hydrogen fluoride (HF) based epitaxial lift-off (ELO) process, or layers of GaAs through a gas phased ELO process enabled by xenon difluoride (XeF2) selective etching of Ge.

High-Mobility Ge on Insulator (GOI) by SiGe Mixing-Triggered Rapid-Melting-Growth

not Available.

Giant growth of single crystalline Ge on insulator by seeding lateral liquid-phase epitaxy

Giant growth (~ 400 μm length) of single crystalline Ge on insulator (GOI) with (100), (110), and (111) orientations is demonstrated by lateral liquid-phase epitaxy (L-LPE) using Si(100), (110), and (111) substrates, respectively, as the seeds. The micro-probe Raman measurements and transmission electron microscopy observations showed that the growth regions were of very high crystal quality and were defect free. In addition, lateral diffusion of Si atoms was observed only in the regions near the seeding edges (~ 100 μm). Based on these findings, the trigger for the giant growth of the high-quality GOI was discussed considering the solidification temperature gradient due to Si–Ge mixing and the thermal gradient due to the latent heat at the growth front.

Optical and Electrical Characterizations of Defects in SiGe-on-insulator

In this work, we characterized defects in SiGe-On-Insulator (SGOI) and Ge-On-Insulator (GOI) by optical and electrical methods. All the SGOI and GOI substrates in this work were fabricated using Ge condensation by dry oxidation method. Defect generation and transformation during the temperature ramp-up process of Ge condensation were clarified by photoluminescence. The location of main defect levels were determined to be above mid-gap by back-gate metal-oxide-semiconductor field-effect-transistor (MOSFET) current deep-level-transient-spectroscopy and dual-metal-oxide-semiconductor thermally stimulated capacitance. The defects in fabricated SGOI and GOI were directly observed by transmission-electron-microscopy. These defects unintentionally induced high hole concentration in SGOI and GOI. The dependence of energy level position on Ge fraction was investigated in detail for the defect-related acceptor levels by Hall effect and back-gate MOSFET drain current vs. gate bias voltage. The suppressions of defects by post-Al-deposition-annealing and forming gas annealing were also discussed.

Defect delineation and characterization in SiGe, Ge and other semiconductor-on-insulator structures

The first part of this paper deals with the standard etching techniques (Secco, Schimmel, Wright etch…) used for defects delineation in Si, SiGe, Ge and in new engineered substrates made from these starting materials, such as Silicon-on-Insulator (SOI), strained and extra-strained Silicon-on-Insulator (sSOI and XsSOI) and Ge-on-Insulator (GeOI). We focus in the second part on the new, chromium-free etching techniques which have recently been developed: chemical solutions containing other oxidizing agents (such as organic peracids, additional compounds such as bromine, iodine etc.) and gaseous HCl etching. We compare the performances of standard etching solutions with those of chromium-free etching techniques and list the specificities of the different techniques. Finally, we attempt to link defect etching results with those coming from physical characterization techniques (such as Raman spectroscopy, X-ray diffraction and Pseudo-MOSFET mobility measurements). A few similar studies can be found in the literature. Extensive work is however still necessary to establish a proper correlation between selective etching and those techniques. Up to now, defect selective etching techniques are the most sensitive ones for an accurate evaluation of crystalline quality.

Evaluation of Electron and Hole Mobility at Identical Metal–Oxide–Semiconductor Interfaces by using Metal Source/Drain Ge-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors

In contrast to high hole mobility of p-channel Ge metal–oxide–semiconductor field-effect transistors (MOSFETs), low electron mobility and poor current drive of n-channel Ge MOSFETs are one of critical issues for realizing Ge complementary metal–oxide–semiconductor (CMOS) technologies. In order to adequately understand the physical origins of the difference in the Ge MOS mobility behaviors between electrons and holes, an appropriate mobility analysis is strongly needed. In this paper, we propose a novel method to extract both electron and hole mobility in an identical device by using metal source/drain (S/D) Ge-on-insulator (GOI) MOSFETs. The influence of the parasitic resistance associated with metal S/D junctions is eliminated by using MOSFETs with four-terminal Kelvin patterns. It is demonstrated that the electron and hole mobility at the same Ge MOS interfaces are accurately determined. It is found, as a result, that the present Ge n-channel MOSFET has the electron mobility close to the Si universal electron mobility. On the other hand, the hole mobility at the same MOS interface is lower than the Si universal hole mobility, which is attributable to low crystal quality of the channel and/or the poor MOS interface properties. These facts strongly suggest the low electron mobility in Ge MOSFETs, reported so far, is not necessarily limited by any essential problems, but much higher electron mobility is expected by further improvement of the material and interface qualities.

Engineered Si wafers: On the role of oxide heterostructures as buffers for the integration of alternative semiconductors

AbstractEngineered Si wafer systems present an important materials science approach to further improve the performance of Si‐based micro‐ and nanoelectronics. This is due to the potential to integrate alternative semiconductor layers on the mature Si wafer technology platform which are otherwise too expensive or even impossible to grow in bulk form in the required quality and quantity. Ge is attracting increasing research interest because it is for example a promising material for high mobility channel CMOS technologies as well as a mediator material to achieve the manufacturing of III‐V/Si hybrid devices. The integration of Ge on Si wafers is today either achieved by a combination of layer transfer and wafer bonding techniques or by a sequence of subsequent, epitaxial thin film deposition growth steps. In the latter case, the traditional approach to integrate Ge layers of low defect densities is given by the use of compositionally graded SiGe heterostructures. As this approach suffers however from required SiGe buffer thicknesses on the micrometer scale, making integrated circuit processing difficult, research on the development of innovative buffer heteroepitaxy approaches is intensively pursued. A new interesting class of buffer materials with a high degree of flexibility is given by oxide heterostructures. Using the integration of single crystalline Si and Ge on the Si(111) material platform via oxide heterostructures as an example, the flexibility of engineered oxide heterostructures to control important epitaxy parameters is demonstrated. In this study, epitaxial Si(111) and Ge(111) layers were grown on cubic Y2O3(111)/cubic Pr2O3(111)/Si(111) and Pr2O3(111)/Si(111) support systems, respectively. The structural properties of the Si‐on‐Insulator (SOI) and Ge‐on‐Insulator (GOI) heterostructures were characterized in detail by a combination of laboratory‐ and synchrotron‐based methods. As main result, both the epitaxial Si(111) and Ge(111) films were shown to be atomically smooth and single crystalline (i.e. free of stacking twins). Defect engineering approaches need to be applied in future to reduce stacking faults (e.g. microtwins) which are identified as the major defect mechanism in the epitaxial Si(111) and Ge(111) films. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Formation process of high-purity Ge-on-insulator layers by Ge-condensation technique

Formation process of Ge-on-insulator (GOI) layers by Ge condensation with very high purity of Ge is clarified in terms of diffusion behaviors of Si and Ge in a SiGe layer. It is shown that the diffusion behavior affects the Ge condensation process, and the purity of GOI layer can be determined by the relation between oxidation and diffusion of Si. Experimental results support a model of GOI formation that the selective oxidation of Si in SiGe continues until the formation of a GOI layer with the residual Si fraction of less than 0.01%. Based on this model, we quantitatively clarify the reason why GOI layers can reach very low residual Si fraction without oxidizing Ge by calculating the diffusion behavior of Si during the Ge condensation process. As a result, we have found that the thermal diffusion of Si is sufficiently fast so that the selective oxidation of Si can continue during the GOI formation process until the averaged residual Si fraction in the SGOI layer becomes lower than 0.03%, which is essentially consistent with the experimental results. In addition, we have found that, even if the GOI layer is thick, the Ge purity of GOI layer can approach 100% infinitely in principle by enhancing the Si diffusion in SGOI compared to the oxidation rate of SGOI.

Influence of top surface passivation on bottom-channel hole mobility of ultrathin SiGe- and Ge-on-insulator

Bottom-channel hole mobility was examined by a pseudo-metal-oxide-semiconductor field-effect transistors method for ultrathin SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI), which were fabricated using Ge condensation by dry oxidation. By comparing samples with and without a top SiO2 layer, we investigated the influence of top surface passivation on bottom-channel hole mobility. Mobility degradation was found in an ultrathin SGOI/GOI layer without top SiO2 and became more serious with a decrease in the thickness of the SGOI/GOI layer, which strongly suggested that top surface passivation is necessary to evaluate accurate channel mobility. A 13-nm-thick GOI with passivation showed a high mobility value of 440 cm2/V s.

Drive current of ultrathin Ge‐on‐insulator n‐channel MOSFETs

AbstractIn this paper, we study a drive current of ultrathin Ge‐on‐Insulator (GOI) n ‐channel MOSFETs based on a quantum‐corrected Monte Carlo device simulation. We found that the drive current of GOI n ‐channel MOSFETs significantly decreases by considering electron transfer to the higher X valleys from the lowest L valleys due to the phonon scattering. However, under quasi‐ballistic transport, the GOI n ‐channel MOSFETs with Ge (111) surface orientation are demonstrated to provide substantially higher drive current than the Si‐based MOSFETs. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Molecular beam epitaxy growth of metamorphic high electron mobility transistors and metamorphic heterojunction bipolar transistors on Ge and Ge-on-insulator/Si substrates

A direct growth approach using composite metamorphic buffers was employed for monolithic integration of InP-based high electron mobility transistors (HEMTs) and heterojunction bipolar transistors (HBTs) on Ge and Ge-on-insulator (GeOI)/Si substrates using molecular beam epitaxy. GaAs layers nucleated on these substrates and grown to a thickness of 0.5μm were optimized to minimize the nucleation and propagation of antiphase boundaries and threading dislocations, and exhibited an atomic force microscopy rms roughness of ∼9Å and x-ray full width at half maximum of ∼36arcsec. A 1.1μm thick graded InAlAs buffer was used to transition from the GaAs to InP lattice parameters. The density of threading dislocations at the upper interface of this InAlAs buffer was ∼107cm−2 based on cross-sectional transmission electron microscopy analyses. HEMT structures grown metamorphically on GeOI/Si substrates using these buffer layers demonstrated transport properties equivalent to base line structures grown on InP substrates, with room temperature mobility greater than 10000cm2∕Vs. Similarly, double heterojunction bipolar transistors (D-HBTs) grown metamorphically on GeOI/Si substrates and fabricated into large area devices exhibited dc parameters close to reference D-HBTs grown on InP substrates.

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

Ultrathin Ge-on-Insulator Metal Source/Drain p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated By Low-Temperature Molecular-Beam Epitaxy

We demonstrate the enhancement of hole mobility in an ultrathin Si/Ge/Si-on-insulator (SOI) channel metal–oxide–semiconductor field-effect transistor (MOSFET) with a metal source and drain (S/D). The ultrathin Si/Ge structure is fabricated on a SOI substrate by low-temperature molecular-beam epitaxy (LTMBE). We examined the impact of the Si/Ge/Si structural parameters and the crystal quality on the electrical characteristics of MOSFETs, particularly from the viewpoints of the Ge thickness and the annealing temperature. As a result, the hole mobility of the fabricated Ge-on-insulator (GOI)-pMOSFETs after annealing at 600 °C was found to be 1.2 times larger than the Si universal hole mobility. For the Ge thickness dependence of hole mobility, the MOSFETs with the Ge thicknesses of 8, 12, and 16 nm had almost the same mobility. On the other hand, the sample with 4 nm Ge thickness had lower mobility. For the annealing temperature dependence, the hole mobility had a maximum value at 600 °C and decreased with increasing annealing temperature above 700 °C.