Ge-on-insulator Research Articles

PIC-integrable, uniformly tensile-strained Ge-on-insulator photodiodes enabled by recessed SiNx stressor

Mechanical strain engineering has been promising for many integrated photonic applications. However, for the engineering of a material electronic bandgap, a trade-off exists between the strain uniformity and the integration compatibility with photonic-integrated circuits (PICs). Herein, we adopted a straightforward recess-type design of a silicon nitride ( SiN x ) stressor to achieve a uniform strain with enhanced magnitude in the material of interest on PICs. Normal-incidence, uniformly 0.56% tensile strained germanium (Ge)-on-insulator (GOI) metal-semiconductor-metal photodiodes were demonstrated, using the recessed stressor with 750 MPa tensile stress. The device exhibits a responsivity of 1.84 ± 0.15 A / W at 1550 nm. The extracted Ge absorption coefficient is enhanced by ∼ 3.2 × to 8340 cm − 1 at 1612 nm and is superior to that of In 0.53 Ga 0.47 As up to 1630 nm limited by the measurement spectrum. Compared with the nonrecess strained device, additional absorption coefficient improvement of 10%–20% in the C -band and 40%–60% in the L -band was observed. This work facilitates the recess-strained GOI photodiodes for free-space PIC applications and paves the way for various (e.g., Ge, GeSn or III-V based) uniformly strained photonic devices on PICs.

Tailoring bolometric properties of a TiOx/Ti/TiOx tri-layer film for integrated optical gas sensors.

In this paper, we systematically investigated tailoring bolometric properties of a proposed heat-sensitive TiOx/Ti/TiOx tri-layer film for a waveguide-based bolometer, which can play a significant role as an on-chip detector operating in the mid-infrared wavelength range for the integrated optical gas sensors on Ge-on-insulator (Ge-OI) platform. As a proof-of-concept, bolometric test devices with a TiOx single-layer and TiOx/Ti/TiOx tri-layer films were fabricated by varying the layer thickness and thermal treatment condition. Comprehensive characterization was examined by the scanning transmission electron microscopy (STEM), X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS) analyses in the prepared films to fully understand the microstructure and interfacial properties and the effects of thermal treatment. Quantitative measurements of the temperature- and time-dependent resistance variations were conducted to deduce the minimum detectable change in temperature (ΔTmin) of the prepared films. Furthermore, based on these experimentally obtained results, limit-of-detection (LoD) for the carbon dioxide gas sensing was estimated to demonstrate the feasibility of the proposed waveguide-based bolometer with the TiOx/Ti/TiOx tri-layer film as an on-chip detector on the Ge-OI platform. It was found that the LoD can reach ∼3.25 ppm and/or even lower with the ΔTmin of 11.64 mK in the device with the TiOx/Ti/TiOx (47/6/47 nm) tri-layer film vacuum-annealed at 400 °C for 15 min, which shows great enhancement of ∼7.7 times lower value compared to the best case of TiOx single-layer films. Our theoretical and experimental demonstration for tailoring bolometric properties of a TiOx/Ti/TiOx tri-layer film provides fairly useful insight on how to improve LoD in the integrated optical gas sensor with the bolometer as an on-chip detector.

Electrical Properties of Ultra-Thin Body (111) Ge-On-Insulator n-Channel MOSFETs Fabricated by Smart-Cut Process

We have systematically examined electrical characteristics of ultra-thin body (UTB) (111) Ge-on-insulator (GOI) n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) fabricated by the smart-cut process and have compared their electrical properties with those of (100) ones. The (111) GOI thickness was varied from 29.4 to 7.3 nm. The normal MOSFET operation of a 7.3 nm-thick (111)-oriented GOI nMOSFET has been demonstrated with a reasonable ON/OFF ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> . However, degradation in the effective electron mobility and subthreshold swing (SS) of the (111) GOI nMOSFETs with decreasing the GOI thickness ( T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GOI</sub> ) was observed. Raman analyses and electrical characteristics of GOI nMOSFET under back-gate operation has suggested that a high interface state density at (111) GOI/buried oxide interfaces as well as low GOI film quality near the back interfaces can be an origin of this degradation of the electrical properties with thin body channels.

Optical study of electron and acoustic phonon confinement in ultrathin-body germanium-on-insulator nanolayers

Nanoelectronics require semiconductor nanomaterials with high electron mobility like Ge nanolayers. Phonon and electron states in nanolayers undergo size-dependent changes induced by confinement and surface effects. Confined electrons and acoustic phonons determine layer optical, electric and thermal properties. Despite scientific and practical significance, their experimental studies in individual nanolayers are still lacking. Thanks to recent progress in the fabrication of high-quality nanolayers, here, we report the thickness dependencies of Raman spectra of acoustic phonons and optical spectra of electrons confined in germanium-on-insulator (GeOI) nanolayers with thicknesses TGeOI = 1-20 nm. We show that for TGeOI > 5 nm, both GeOI acoustic phonon Raman spectra and the E1 electron energy gap display dependencies on TGeOI which are reasonably described by the corresponding phonon and electron confinement theories. Accordingly, TGeOI can be probed using acoustic phonon Raman spectra at TGeOI > 5 nm. However, both confinement theories fail to describe GeOI thickness dependencies at TGeOI < 5 nm. We attribute this discrepancy to an increased influence of the Ge-GeO2 interface disorder with TGeOI reduction. The acoustic phonon data suggest a decrease of Ge normal-to-the-layer longitudinal sound velocity. Generation of interface-disorder-induced dispersionless phonons might contribute to this. The change in GeOI phonon properties at TGeOI < 5 nm might influence E1(TGeOI) dependence via a change in the GeOI electron-phonon interaction. We demonstrate that the Al2O3 coating improves the agreement between experimental and confinement theories, probably, via reduction of disorder at the Ge-GeOx-Al2O3-interface. Our results are important for control of nanolayer-confined electrons and phonons with benefits for modern and future nanoelectronic devices.

Ge-on-insulator lateral p-i-n waveguide photodetectors for optical communication.

We report high-performance lateral p-i-n Ge waveguide photodetectors (WGPDs) on a Ge-on-insulator (GOI) platform that could be integrated with electronic-photonic integrated circuits (EPICs) for communication applications. The high-quality Ge layer affords a low absolute dark current. A tensile strain of 0.144% in the Ge active layers narrows the direct bandgap to enable efficient photodetection over the entire range of C- and L-bands. The low-index insulator layer enhances optical confinement, resulting in a good optical responsivity. These results demonstrate the feasibility of planar Ge WGPDs for monolithic GOI-based EPICs.

Isotropic Wet Etching and Improving Surface Flatness of Ge for Etchback Ge-on-Insulator Fabrication

1. Introduction Ge has been received much attention as the next generation semiconductor materials due to its attractive characteristics such as high carrier mobility[1] and narrow bandgap corresponding near infrared wavelength[2]. In order to utilize its characteristics for the applications, Ge-on-Insulator (GOI) structure is necessary. Several fabrication methods for GOI have been suggested such as wafer bonding and mechanical thinning[3], Smart-CutTM[4,5], and SiGe condensation[6]. It is well known Smart-CutTM is widely used for commercial Si-on-Insulator (SOI) fabrication. However, Ge is more sensitive to damages caused by ion implantation and difficult to recover damages completely. Therefore, the best way for GOI fabrication have not been developed.In early stage of SOI R&D, many approaches were proposed, too[7]. Wafer bonding and etchback is one of the simplest technique, and the advantage of this method is any damages due to ion implantation or mechanical stress are not induced to the top semiconductor layer. Therefore, we focused on etchback technique for GOI fabrication. It is necessary to develop appropriate Ge etching method with moderate etching rate and keeping or improving surface flatness. In this study, we aim to develop appropriate etching method of Ge for etchback GOI fabrication. 2. Experimental and results We used single side mirror polished Ge wafer with a thickness of 500 μm. Figure 1 shows the experimental procedure in this study. The original polished top surface was covered by photoresist to avoid etching from this side. Firstly, we confirmed HF + HNO3 mixture solution for Ge etching because it is widely known as etching solution for Si. Figure 2 shows optical microscope images for the back side (non-polished side) of (100)-oriented Ge wafer (a) before etching and (b) after etching by HF + HNO3 for 7 minutes. By etching, surface uniformity drastically improved. So, wet etching can be used for Ge thinning and planarization. However, this solution reacts handle Si substrate of GOI, too. As an alternative etching solution, we selected HF + H2O2 mixture[8]. Figure 3 shows the etching result of (100)-oriented Ge etched by HF + H2O2 + H2O (7:7:6) solution. Although Ge was etched similar to Fig. 2(b), surface uniformity was inferior to HF + HNO3 etching. To improve surface uniformity, CH3COOH was added as diluent instead of H2O because politic amount of CH3COOH into HF + HNO3 solution leads isotropic etching and mirror plane on Si surface[9]. Figures 4 shows the etching results of (100)-oriented Ge by HF + H2O2 + CH3COOH (1:1:1) solution. Surface uniformity improved than Fig. 3 and there is no orientation dependence (data not shown). Therefore, isotropic etching occurs on Ge surface. The average etching rate in the first 20 minutes calculated from the lost masses was 7.9 μm/min. It should be noted any agitation was not carried out during etching and longer etching time leads decreasing of etching rate. Possible etching reaction is expressed as[10]:2CH3COOH + 2H2O2 → 2CH3COOOH + 2H2O (1)Ge + 2CH3COOOH + 2e - → Ge2+ + 2CH3COO- + 2OH- (2)As further investigation of surface uniformity, atomic force microscope (AFM) observation was carried out. Figure 5 shows AFM images for backside of (100)-oriented Ge etched for 110 minutes. The RMS of 30×30 μm2 area is 0.48 nm. Compared with the RMS of original backside (> 5 μm), the surface flatness is improved drastically. In the conference, electrical characteristics of etched surface will be presented. 3. Conclusions For etchback GOI fabrication, we study isotropic etching for Ge. HF + H2O2 + CH3COOH mixture solution can etch Ge isotropic and improving surface uniformity. This solution has a potential as etching solution for etchback to make GOI structure. Acknowledgements This work was supported by JSPS KAKENHI Grant Numbers 19K15028 and 19H05616. Appendix Original concentrations of the chemicals in this study are HF: 49 wt%, HNO3: 69 wt%, H2O2: 30 wt%, and CH3COOH: 99.7 wt%. All compounding ratios in this article are volume rate.

(Invited) Epitaxial Growth of Ge/III-V Films and Hetero-Layer Lift-off for Ultra-Thin GeOI Fabrication

Ge have been considered as an alternative channel material to Si as well as a promising base material for optical components, adding new functions into current Si-LSI. It is necessary to form high quality Ge layers onto Si substrate for realization of Si/Ge monolithic 3D (M3D) devices. Combing high quality hetero-epitaxial growth of Ge/III-V semiconductors, low-temperature bonding, and an advanced lift-off technique, we have achieved Ge layer transfer on Si substrate, possessing excellent Ge crystallinity and electrical properties. The advanced HEtero-Layer-Lift-Off (HELLO) technique utilizing SiGe-based hetero-epitaxy and dozens digital etching (DDE) processes are demonstrated to realize high quality and ultra-thin Ge-on-insulator (GeOI) structures for ultimately scaled CMOS devices on Si platform.

Operation of (111) Ge-on-Insulator n-Channel MOSFET Fabricated by Smart-Cut Technology

In this letter, we demonstrate the well-behaved operation of (111) Ge-on-insulator (GOI) n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with excellent electrical characteristics. High crystal quality (111) GOI substrates for the fabrication of (111) GOI nMOSFETs were prepared by a smart-cut process combined with an annealing process at 550 °C. Excellent electrical properties of the (111) GOI substrates were achieved by using relatively low ion implantation (I/I) dose condition of ${4}\times {10}^{{16}}$ cm−2. (111) GOI nMOSFETs were fabricated on these substrates, and the electrical characteristics were compared to those of the (100) GOI and (111) bulk ones. It is experimentally proved that the (111) GOI nMOSFET provides higher drive current and higher mobility than those of (100) GOI ones. In particular, the record high effective electron mobility of 943 cm2/Vs among reported GOI nMOSFETs is achieved for the present (111) GOI nMOSFETs.

Efficient Mid-Infrared Germanium Variable Optical Attenuator Fabricated by Spin-on-Glass Doping

We demonstrated an efficient carrier-injection germanium (Ge) variable optical attenuator (VOA) operating at 1.95 μm on a Ge-on-insulator (GeOI) platform for mid-infrared (MIR) integrated photonics. Numerical analysis illustrated that the Ge VOA can realize a significantly higher modulation efficiency than a Si VOA owing to the larger free-carrier absorption in Ge at MIR wavelengths. We proved that by introducing phosphorus-doped spin-on-glass (P-SOG) doping technology into the formation of a Ge lateral PIN junction, we can improve the doping concentration in the n+ region as compared with P ion implantation, resulting in improved modulation efficiencies of 380–460 dB/A for Ge VOAs. The P-SOG-doped Ge VOA exhibited a comparable modulation efficiency to a Si VOA operating at 1.55 μm despite the shorter carrier lifetime of 0.4–0.8 ns determined by numerical fitting. Thus, the Ge VOA formed by SOG doping has promising applications in communication and sensing at MIR wavelengths.

Enhanced photoluminescence from strained Ge-on-Insulator surface-passivated with hydrogenated amorphous Si

We study influences of the Ge-on-Insulator (GOI) fabrication and its surface passivation by deposition of a hydrogenated amorphous Si (a-Si:H) layer on light emission properties from a strained Ge. It is shown that the GOI fabrication leads to drastic enhancements of room temperature photoluminescence (PL). One of the origins is elimination of a defective Ge layer inevitably formed due to strain-relaxation. We also find that the surface passivation with the a-Si:H layer can further enhance the PL intensity provided that the dopant type, p or n, of the a-Si:H matches that of the Ge. As a result, we obtain the PL intensity enhancements up to 15 times compared to as-grown Ge-on-Si, which indicates that the GOI surface-passivated with a-Si:H is a promising structure toward Ge-based high efficient light emitters on the Si platform.

Photo-Responsible Synapse Using Ge Synaptic Transistors and GaAs Photodetectors

In this letter, we propose the photo-responsible synaptic devices by using stackable GaAs photodetectors (PDs) and Ge-on-insulator (Ge-OI) synaptic transistors for the future three-dimensional (3D) artificial vision sensors. The photo-responsible synapse showed good photo-responding synaptic behaviors depending on the incident light to GaAs PD, which changes the hole injection into the Ge-OI transistors, resulting in the change in potentiation/depression characteristics. The training simulation highlighted the fabricated photo-responsible synapse can provide high colored pattern recognition tasks for semiconductor-based hardware systems.

Bubble evolution mechanism and defect repair during the fabrication of high-quality germanium on insulator substrate

We investigate the effect of the annealing temperature and annealing time on the bubble evolution on the hydrogen ion (H+)-implanted germanium (Ge) substrate. It is found that the H2 aggregates gradually with the increase of the annealing time, and the aggregation rate of the H2 increases with the increase of the annealing temperature. Low-temperature Ge/Si wafer bonding (a-Ge interlayer) and Smart-Cut™ technique are applied to fabricate high-quality Ge-on-insulator (GOI). It is proved that thick Ge film is more difficult to be exfoliated from the Ge substrate. As long as the pressure in the bubbles is high enough, although the bubbles do not burst on the Ge surface, the lateral diffusion of H2 may occur to trigger the exfoliation of the Ge film. The contact of the wafers leads to the lateral merging of the small bubbles, resulting in the increase of the bubble size at the edge of the big void. It is believed that high bonding strength between Ge and SiO2 is essential to resist the high pressure in the bubble for the successful exfoliation of the Ge film. The point defects in the Ge film can be totally eliminated either by high-temperature annealing or by nanosecond pulse laser annealing, resulting in the improvement of the Ge film quality.

Effects of hydrogen ion implantation dose on physical and electrical properties of Ge-on-insulator layers fabricated by the smart-cut process

We experimentally evaluate the influence of a hydrogen ion implantation (I/I) dose on the physical and electrical properties of Ge-on-insulator (GOI) films fabricated by the smart-cut process with the two doses of 1 × 1017 cm−2 and 4 × 1016 cm−2. It is found that thermal annealing is effective in improving the crystallinity of the GOI layers and that the defect-less GOI layers can be realized under the optimized annealing temperature of 550 °C, irrespective of the I/I dose. However, the reduction of Hall hole mobility is observed in GOI substrates fabricated with higher I/I dose condition. This mobility reduction is not observed for GOI p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) under the back-gate operation. On the other hand, n-channel MOSFETs fabricated on the smart-cut GOI substrates with As-doped S/D junctions are found to exhibit the higher effective electron mobility for the low I/I dose than that for the high I/I dose. As a result, it can be concluded that the high H+ I/I dose of 1 × 1017 cm−2 causes the degradation in the mobility of smart-cut GOI substrates and that the choice of the hydrogen I/I dose is important in the fabrication of GOI wafers for MOSFET applications.

Technology and Modeling of Nonclassical Transistor Devices

This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

Fabrication and modeling of SiGe and Ge nanowires on insulator by three-dimensional Ge condensation method

In this work, three-dimensional (3D) Ge condensation was carried out to explore the merits of Ge condensation method in fabricating low-dimensional SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) structures. Through varying the width of SGOI wires from 220 nm to 50 μm before Ge condensation, the Ge content of SiGe wires can be easily modulated from 1.0 to 0.55 after 3D Ge condensation facilitating fabrication of SiGe/Ge heterojunction nanowires (NWs). Based on the volume change of Si, Ge and SiO2 with consideration of a geometry factor, a simple 3D Ge condensation model was built. It is found that the enrichment of Ge content mainly comes from condensation effect along directions with small dimensions. The proposed 3D condensation model can be a guidance to design and fabricate low-dimensional SGOI, GOI and even SiGe/Ge heterostructures on insulator materials.

Conduction Type Control of Ge-on-Insulator: Combination of Smart-Cut™ and Defect Elimination

We electrically characterized Ge-on-Insulator (GOI) fabricated by Smart-Cut™ method. Annealing improved electrical characteristics of the p-GOI. On the other hand, conduction type of the n-GOI changed to p-type after annealing. Structural analysis showed many defects were introduced near the bottom interface and it cannot be recovered by annealing. We suggest alternative ways to avoid defects for n-GOI fabrication.

Integrating GeSn photodiode on a 200 mm Ge-on-insulator photonics platform with Ge CMOS devices for advanced OEIC operating at 2 μm band.

High-performance GeSn multiple-quantum-well (MQW) photodiode is demonstrated on a 200 mm Ge-on-insulator (GeOI) photonics platform for the first time. Both GeSn MQW active layer stack and Ge layer (top Ge layer of GeOI after bonding) were grown using a single epitaxy step on a standard (001)-oriented Si substrate (donor wafer) using a reduced pressure chemical vapor deposition (RPCVD). Direct wafer bonding and layer transfer technique were then employed to transfer the GeSn MQW device layers and Ge layer to a 200 mm SiO2-terminated Si handle substrate. The surface illuminated GeSn MQW photodiode realized on this platform exhibits an ultra-low leakage current density of 25 mA/cm2 at room temperature and an enhanced photo sensitivity at 2 μm of 30 mA/W as compared to a GeSn MQW photodiode on Si at 2 μm. The underlying GeOI platform enables monolithic integration of a complete suite of photonics devices operating at 2 μm band, including GeOI strip waveguides, grating couplers, micro-ring modulators, Mach-Zehnder interferometer modulators, etc. In addition, Ge CMOS circuits can also be realized on this common platform using a "photonic-first and electronic-last" processing approach. In this work, as prototype demonstration, both Ge p- and n-channel fin field-effect transistors (FinFETs) were realized on GeOI simultaneously with decent static electrical characteristics. Subthreshold swings of 150 and 99 mV/decade at |VD| = 0.1 V and drive currents of 91 and 10.3 μA/μm at |VG-VTH| = 1 V and |VD| = 0.75 V were achieved for p- and n-FinFETs, respectively. This works illustrates the potential of integrating GeSn (as photo detection material) on GeOI platform for Ge-based optoelectronics integrated circuits (OEICs) targeting communication applications at 2 μm band.

Impact of Bottom-Gate Biasing on Implant-Free Junctionless Ge-on-Insulator n-MOSFETs

In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility ( $\mu _{\text {eff}}$ ) of 160 cm2/ $\text {V} \cdot \text {s}$ was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher ${V}_{\text {th}}$ tunability and improvement of $\mu _{\text {eff}}$ by bottom-gate biasing.

Nanoscale n++-p junction formation in GeOI probed by tip-enhanced Raman spectroscopy and conductive atomic force microscopy

Ge-on-Si and Ge-on-insulator (GeOI) are the most promising materials for the next-generation nanoelectronics that can be fully integrated with silicon technology. To this day, the fabrication of Ge-based transistors with a n-type channel doping above 5 × 1019 cm−3 remains challenging. Here, we report on n-type doping of Ge beyond the equilibrium solubility limit (ne ≈ 6 × 1020 cm−3) together with a nanoscale technique to inspect the dopant distribution in n++-p junctions in GeOI. The n++ layer in Ge is realized by P+ ion implantation followed by millisecond-flashlamp annealing. The electron concentration is found to be three times higher than the equilibrium solid solubility limit of P in Ge determined at 800 °C. The millisecond-flashlamp annealing process is used for the electrical activation of the implanted P dopant and to fully suppress its diffusion. The study of the P activation and distribution in implanted GeOI relies on the combination of Raman spectroscopy, conductive atomic force microscopy, and secondary ion mass spectrometry. The linear dependence between the Fano asymmetry parameter q and the active carrier concentration makes Raman spectroscopy a powerful tool to study the electrical properties of semiconductors. We also demonstrate the high electrical activation efficiency together with the formation of ohmic contacts through Ni germanidation via a single-step flashlamp annealing process.

Ge field-effect transistor with asymmetric metal source/drain fabricated on Ge-on-Insulator: Schottky tunneling source mode operation and conventional mode operation

An asymmetric Schottky tunneling source field-effect transistor (STS FET) is a prospective device structure to suppress the short-channel effect. Recently, we succeeded in the fabrication and operation of a Ge-STS n-channel FET with TiN and PtGe asymmetric metal source/drain (S/D) on a bulk Ge substrate. However, the Ge-STS p-channel FET has not been demonstrated yet. In this study, we fabricated an asymmetric metal S/D FET with the same S/D structure on a bulk Ge and a Ge-on-Insulator (GOI) substrate. The GOI was made by using the Smart-CutTM technique. The device fabricated on a bulk Ge did not operate. On the other hand, the fabricated FET on a GOI, which has a taper-shaped TiN/Ge source interface, showed STS p-FET behavior. These results suggest that the carrier injection can be improved by the optimization of the device structure. As an auxiliary effect, conventional metal-oxide-semiconductor (MOS) FET operation was also observed, thanks to GOI introduction. We demonstrated both STS mode and MOSFET mode operation in the same device on GOI.