Growth Of Ge Research Articles

High Quality Ge Growth on Si (111) and Si (110) by Using Reduced Pressure Chemical Vapor Deposition

Heteroepitaxial growth of Ge on Si has great interest for various optoelectronic applications such as Ge photodiodes(1). However 4.2% of lattice mismatch causes dislocation formation and island growth. High quality Ge(001) growth techniques are reported in ref.(2-4). Moreover, Ge(111) surface is also interesting because of higher carrier mobility(5). Furthermore, Ge(110) is preferred orientation of virtual substrates for epitaxial graphene growth(6). In the case of the Ge deposition on Si(111) and Si(110) substrates, it seems that the process conditions used for Ge growth on Si(001) are not suitable to realize high crystallinity and smooth surface (7). In this paper, we present a method of high quality and smooth Ge layer growth on Si(111) and Si(110), which is the same level as the Ge growth on Si(001).Epitaxial growth of Ge on Si(111) and Si(110) is carried out using a reduced pressure chemical vapor deposition system. After HF last clean, a wafer is baked at 1000°C and cooled down to 600°C in H2 and further to 300-550°C in N2 to form a hydrogen-free Si surface. Then a 100 nm thick Ge layer is deposited as a seed layer using GeH4 with N2 carrier gas. Afterward the wafer is heated up to 450-650°C in H2 and the main part of Ge is deposited using a H2-GeH4 gas mixture. For threading dislocation density (TDD) reduction, annealing at 800°C in H2 is performed for several times (cyclic annealing) by interrupting the Ge growth. Atomic-force microscopy (AFM) is used for surface roughness analysis. Scanning transmission electron microscopy (STEM) and X-ray diffraction (XRD) are used for structural characterization of the Ge layer. Secco defect etching combined with angle view scanning electron microscopy (SEM) or optical microscope is used for TDD evaluation.Figure 1(a,b) summarize the root mean square (RMS) roughness of Ge(111) and Ge(110) seed layers grown at 300-550°C before and after postannealing at 600-800°C. If the growth temperature is lower than 350°C for Ge(111) and 400°C for Ge(110), a significant increase of the surface roughness is observed after postannealing at 700°C and 800°C, respectively. For both crystal orientations, the lowest RMS roughness is observed by depositing at 450°C for as deposited and postannealed samples. The maintained RMS roughness even after postannealing at 800oC may be indicating good crystal quality even at as deposited condition.To confirm the influence of the growth temperature on the crystallinity, cross section TEM images of the Ge(111) and the Ge(110) seed layers deposited at 300°C and 450°C are shown in Fig. 2(a-d). In the case of Ge growth at 300°C (Fig. 2(a,b)), a very high density of stacking faults (SF) and high surface roughness are observed for both crystal orientations. In contrast, by depositing at 450°C (Fig. 2(c,d)), lower SF density in the Ge layer is observed compared to that at 300°C. By postannealing, an improvement of crystallinity is observed for the Ge seed layers deposited at 450°C. However, in the case of 300°C, the crystallinity cannot be improved by the postannealing, because a too high density of dislocations and SF may cause irregular Ge atom migration. As the result, surface roughening occurs.Figure 3(a,b) show AFM surface roughness images after 5 μm-thick Ge(111) and Ge(110) deposited with cyclic annealing at 800°C, respectively. Clear terraces of ~0.3 and ~0.2 nm, whose heights are close to those of Ge(111) bilayer and Ge(110) monolayer, are observed, respectively. RMS roughness of the Ge(111) and the Ge(110) are 0.51 and 0.35 nm, respectively. These RMS roughnesses are comparable to a level reported for Ge (001) in ref.(1).Figure 4 shows TDD of Ge(111) and Ge(110) surfaces as a function of the Ge thickness deposited with cyclic annealing on Si(111) and Si(110) substrates. For both orientations, TDD of ~4×108 cm-2 is obtained for 500 nm-thick samples. With increasing the Ge thickness, the TDD is reduced and levels below TDD of ~5×106 cm-2 are achieved for both Ge (111) and Ge(110) for 5 μm-thick Ge.These methods enable high quality virtual substrate fabrication not only for (001) surfaces but also for (111) and (110) orientation without a chemical mechanical polishing process. References Lischke et al. Nature Photonics15 (2021) 925Yamamoto et al. Solid-State Electron. 60 (2010) 2Yamamoto et al. Semicond. Sci. Technol. 33 (2018) 124007 M. Hartmann et al. J. Appl. Phys. 95 (2004) 5905 H. Lee et al. IEDM Tech. Digest (2009) 09-457J-H. Lee et al. Science 344 6181(2014) 286M. Hartmann et al. J. Cryst. Growth 310 (2008) 5287 Figure 1

(Digital Presentation) Epitaxially Grown of SiGe on Ge Microbridge and Observation of Strong Resonant Light Emission

Introduction Ge has been attracting attention for the realization of intra chip optical integrated circuits. In particular, the introduction of tensile strain by epitaxial growth of Ge on Si substrate improves the direct transition probability by shifting the Γ-valley, resulting in an increase in luminescence efficiency. Furthermore, by forming Ge microbridge structure, the larger uniaxial tensile strain can be induced into the freestanding Ge, which is expected to further improve the luminescence efficiency [1]. However, when the stronger tensile strain is applied to Ge, the emission wavelength shifts significantly to the longer wavelength. In order to arbitrary control the emission wavelength to the shorter, especially within the telecommunication wavelength band, introduction of SiGe/Ge heterostructures in the microbridge is considered to be one of the most proper ways. In this work, we attempt to grow the strained SiGe layer on the Ge microbridge and observe the shorter wavelength light emission from the strained SiGe. Moreover, it has been shown that Fabry-Perot resonance takes place in the Ge microbridge structure owing to the side wall reflection [2], leading to the strong resonant luminescence peaks. Here also we observe the resonant light emission from the SiGe/Ge microbridge structure. Experimental Methods A Ge layer was grown on a Si(100) wafer by solid-source molecular beam epitaxy (MBE) with using so-called two-step growth method. First, a 40-nm-thick buffer layer was grown at a low temperature of 350 °C. Then, 500 nm thick Ge layer was grown at 600 °C. Finally, thermal annealing was performed in situ at a temperature of 800 °C for 10 min to reduce the threading dislocation density in Ge layers. After the MBE growth, patterning of the microbridge structure was performed by standard photolithography process and inductively coupled plasma reactive-ion dry etching. Si beneath the microbridge was then removed to form freestanding structures by KOH wet etching. After fabrication of the Ge microbridge, 60 nm thick Si0.2Ge0.8 layer was directly grown on the Ge microbridge at 350 °C. Results and Discussion SEM observation showed that fine microbridge structure remains unchanged after the Si0.2Ge0.8 layer overgrowth on the Ge microbridge. Raman measurements confirmed that the grown SiGe has tensile strain originated from the lattice mismatch between the Si0.2Ge0.8 and underneath Ge, indicating that elastic strain relaxation did not occur. A PL spectrum obtained from the central position of the Si0.2Ge0.8 microbridge exhibits strong light emission in the wavelength range from 1500 to 2000 nm. This is thought to be originated both from SiGe and Ge layers. The PL intensity around shorter wavelength region is significantly increased after the Si0.2Ge0.8 epitaxial growth compared to that before the growth, indicating that the SiGe growth is contributing to the light emission at the telecommunication band. It is noted that a PL spectrum obtained in the unpatterned area from the same sample has almost no light emission, indicating that the microbridge structure is very promising for obtaining the strong light emission. Also it is remarkable that the resonance peaks can be obviously observed. The calculation confirmed this resonance is due to the reflection between side walls of the microbridge. From these results, we can say that the SiGe/Ge heterostructure based microbriges serve as wavelength-controllable high efficiency light sources on Si.This work was partially supported by JSPS KAKENHI (Nos. 19H02175, 19H05616 and 20K21009).[1] M. J. Suess et al, Nat. Photonics 7: 466, 2013[2] Peiji Zhou et al 2018 Jpn. J. Appl. Phys. 57 04FH10 Figure 1

Ge Nano-Heteroepitaxy: From Nano-Pillars to Thick Coalesced Layers

Ge co-integration with Si has always attracted a lot of attention. Thanks to its superior electronic properties, Ge can be used as a channel material in p-type Metal Oxide Semiconductor transistors (high hole mobility) or low power devices such as tunnelling field effect transistors (steep sub-threshold swing operation). Furthermore, Ge is a key enabler in numerous optoelectronic devices (light emitters and photo-detectors). The epitaxial growth of Ge on Si is far from being lattice matched, with a 4.2% difference between Si and Ge, making high quality growth difficult, especially for thick layers.Several schemes have been explored in the literature to obtain thick, good crystalline quality Ge layers, such as a low temperature/high temperature approach followed by a cyclic anneal which yielded flat, slightly tensile strained thick Ge layers with threading dislocation densities around 107 cm-2. Other methods based on epitaxial lateral overgrowth, aspect ratio trapping and 3D heteroepitaxy of Ge films on patterned Si substrates have shown promising results thanks to defect blocking against sidewalls or their containment in certain directions. However, some planar defects were still present at the coalescence fronts with those growth methods.Another interesting method is to perform a heteroepitaxy of Ge in nanometer-size Si windows surrounded by SiO2. Lee et al [1] succeeded in obtaining high quality Ge layers using nano-heteroepitaxy but did not go further in the analysis of defects generated with such an approach. In a previous work [2], we were able to obtain smooth, fully strain relaxed Si0.76Ge0.24 layers with heteroepitaxial growth in nanometer-size Si windows surrounded by SiO2. In that case, SiGe epitaxial growth was carried out on a patterned substrate with a regular array of nanometre-size seed pillars, and growth fronts from individual nano-pillars coalesced to form complete 2D layers. However, planar defects such as stacking faults and twins were present in the final layers. In this work, we wanted to test this growth approach for pure Ge and provide an in-depth analysis of any defects generated.An original process flow based on diblock copolymer patterning was thus used to fabricate nanometer-size SiO2 based templates for growth (Figure 1a). The nano-heteroepitaxy of 2D Ge layers on these templates was performed at 90 Torr, using GeH4 as a precursor, and compared to growth on blanket Si.Ge nano-pillar growth was first investigated, with a delayed Ge growth found at 400°C. Nano-pillars obtained after the growth of 35 nm of Ge were not as homogeneous and well-defined as the 20 nm high SiGe nano-pillars in Ref. [3]. Raising the growth temperature to 600°C resulted in a highly selective and uniform process, with homogeneous and well-defined Ge nano-pillars for growth nominally 20 nm thick. The expected nano-pillar coalescence scheme was also observed at this growth temperature [3]. Transmission Electron Microscopy (TEM) imaging of the 20 nm sample grown at 600°C showed facetted Ge nano-pillars, with numerous 90° edge dislocations at the Ge/Si interface as expected given the low critical thickness of Ge on silicon (4 nm, typically) and the 20 nm nano-pillar width (Figure 1b).Ge thick layers were then grown with a low temperature/high temperature strategy on bulk and nano-patterned substrates for a benchmark of the nano-heteroepitaxy approach. Atomic Force Microscopy (AFM) showed micrometric-size holes at the surface for Ge layers grown on nano-patterned substrates. This might be due to an incomplete coalescence of the thick Ge layers, which were by contrast very smooth on bulk Si (Figure 1c). TEM analysis of a 600 nm thick Ge layer grown on Ge nano-pillars suggested that coalescence resulted in planar defects such as twins and stacking faults starting at the oxide walls, as found for SiGe pillars in previous studies, in addition to edge dislocations at the Ge/Si interface. Despite these morphological differences, similar structural properties (in terms of degree of strain relaxation and Full Width at Half Maximum of the Ge spot along the in-plane direction) were inferred from X-Ray Diffraction (XRD) for layers grown on nano-patterned and bulk substrates (Figure 1d).[1] J. Lee et al., J. Cryst. Growth 301–302, 330 (2007).[2] M. Mastari et al., Nanotechnology 29, 275702 (2018).[3] M. Mastari et al., ECS J. Solid State Sci. Technol. 8, 180 (2019). Figure 1

(G03 - Best Student Presentation Award) Lateral Selective SiGe Growth for Dislocation-Free Virtual Substrate Fabrication

SiGe virtual substrates (VS) having low-surface roughness with less defects are essential for fabricating emerging quantum devices such as qubits. Various techniques to grow VS are reported e.g. conventional graded buffers (1,2) and reverse graded buffers (3). However, these methods require several micrometer-thick buffer layers, having threading dislocations (TDs) network and develop crosshatch patterns resulting in high surface roughness, needing chemical mechanical polishing for planarization. In our previous work, lateral-selective Ge growth (4) was performed in a cavity formed by selective vapor phase etching (VPE) of Si from side of mesa-patterned SiO2 /Si structures fabricated on buried oxide (BOX) to create smooth and dislocation-free local Ge by horizontal aspect ratio trapping (ART). In this work, we demonstrate lateral-selective SiGe growth to realize smooth and dislocation-free local SiGe VS by lateral ART and discuss its surface morphology, strain and dislocations.Lateral-selective SiGe growth is done in a reduced-pressure chemical vapor deposition (RPCVD) system. Thermally oxidized silicon-on-insulator (SOI) wafers with 300 nm SiO2/300 nm Si/2 μm BOX are used. For the sample preparation, 6.3 μm square checkerboard SiO2/Si mesa structure with [110] oriented sidewalls is fabricated by photolithography patterning and reactive ion etching. After standard RCA cleaning followed by HF dip, the wafer is loaded into RPCVD reactor and pre-baked at 850oC in H2 to remove residual oxide. Thereafter, lateral HCl VPE of Si is performed at 850oC from side of mesa. Si pillar remains at center of the mesa. Then, SiGe is selectively deposited in the cavity around the Si pillar using a SiH2Cl2-GeH4-HCl gas mixture at 750oC. Finally, the top SiO2 is removed by HF. Atomic force microscopy (AFM) is used to measure the surface roughness. Energy dispersive X-Ray spectroscopy (EDX) is used for measuring Ge content distribution in SiGe. Micro-Raman spectroscopy is used to analyze strain distribution in Si and SiGe. Nano-beam diffraction (NBD) is employed for estimating the relative change of in- and out-of-plane SiGe lattice parameters. Plan-view transmission electron microscopy (TEM) is used for imaging dislocations.Fig. 1 shows the AFM image for surface morphology of lateral-selective Si0.6Ge0.4 around the Si pillar. SiGe has root mean square roughness of ~0.16 nm, which is similar to blanket Si(001) (~0.14 nm), because the SiGe surface roughness is determined by interface roughness of top SiO2 and sacrificially etched Si. Uniform Ge content of ~40% in SiGe layer is observed by EDX analysis (Fig. 2). In the Si pillar part of Fig. 3, relative uniform tensile-strain of ~0.4% is observed. Since Si is negligibly strained in unpatterned area of SOI (taken as reference), hence during HCl VPE at 850oC, Si pillar/SiO2 interface could slip by higher thermal expansion of Si as interface decreases. Tensile-strain in Si pillar could be formed during cooling process. Ideally, ~1.68% lattice mismatch strain should exist in fully-relaxed ~40% SiGe on Si. However, higher tensile-strain (~2.5%) in SiGe is observed at corners along [010]. To clarify the reason of higher strain at corners, in- and out-of-plane SiGe lattice parameters near Si pillar (as marked in Fig 4(a)) are investigated by NBD. Higher in-plane lattice parameter in [110] is observed in the edge part of the SiGe lamella as compared to the center part (Fig. 4(b)). However, out-of-plane lattice parameter in [001] is homogeneous across entire SiGe (Fig. 4(c)). Because SiGe has uniform Ge concentration as shown in Fig. 2, higher lattice parameter in the edge part of Fig. 4(b) is caused by strain difference. This is because SiGe lamella edge (away from Si pillar) is more relaxed as compared to SiGe lamella center (beside Si pillar) which is confirmed by vertically grown ~700 nm 40% SiGe on blanket Si(110). Symmetric strain distribution does also exist in 90° rotated direction. Therefore, the tensile-strain in [010] is induced from both [110] and [-110]. In Fig. 5, stacking faults of SiGe on (111) plane are observed along [110] and [1-10]. TDs are present along [111], terminated by top SiO2/BOX and located up to first ~400 nm from Si while misfit dislocations are at Si/SiGe interface. Wide dislocation-free area in SiGe is present along [010].This technique enables dislocation-free local SiGe-on-insulator substrate fabrication which can be applied for thin and high quality VS for the quantum devices. References E. A. Fitzgerald et al., J. Appl. Phys., 63, 693 (1988).E. A. Fitzgerald et al., Appl. Phys. Lett., 59, 811 (1991).V. A. Shah et al., Appl. Phys. Lett., 93, 192103 (2008).Y. Yamamoto et al., ECS J. of Solid State Sci. and Technol., 3, 353 (2014). Figure 1

High Quality Ge Growth on Si (111) and Si (110) by Using Reduced Pressure Chemical Vapor Deposition

A method for high quality epitaxial growth of Ge on Si (111) and Si (110) is investigated by reduced pressure chemical vapor deposition. Two step Ge epitaxy (low temperature Ge seed and high temperature main Ge growth) with several cycles of annealing by interrupting the Ge growth (cyclic annealing) is performed. In the case of Ge seed layer growth below 350 °C for (111) and 400 °C for (110) orientation, huge surface roughening due to too high dislocation density is observed after the following annealing step. For both crystal orientations, a high crystallinity Ge seed layer is realized by combination of 450 °C growth with 800 °C annealing. Once the high-quality Ge seed layer is deposited, high crystal quality Ge can be grown at 600 °C on the seed layer for both crystal orientations. For the 5 µm thick Ge layer deposited with the cyclic annealing process at 800 °C, a Si diffusion length of ~400 nm from the interface, RMS roughness below 0.5 nm and threading dislocation density of 5×106 cm-2 are achieved for both (111) and (110) substrates.

Metal-induced crystallization of amorphous semiconductor films: Nucleation phenomena in Ag-Ge films

The initial stages of interfacial interactions between Ag nanoparticles and amorphous Ge (a-Ge) films, in particular the mechanism and kinetics of metal-induced crystallization (MIC) of a-Ge films are investigated herein. Unsupported Ag-Ge films formed by PVD were used as a model. In situ high-resolution (S)TEM and low-loss monochromated STEM-EELS techniques were used for real-time observation of the nucleation and growth of crystalline Ge and intermediate phases, as well as mapping of chemical elements at the reaction zone. We show that crystallization is activated at the metal–semiconductor interface around ≈200 °C, followed by lateral crystallization of a-Ge film at temperatures above ≈400 °C. It was revealed that the MIC process occurs through intermediate phases. Metastable Ag0.8Ge0.2 hcp phase was identified at the reaction front at elevated temperatures, thus revealing the non-equilibrium melting of a eutectic alloy as the most probable mechanism of Ag-induced crystallization of a-Ge film. We show that the MIC process is activated only if the size of Ag nanoparticles exceeds a critical value, which is ≈8 nm in our case and equal to the thickness of the a-Ge film.

A thermally erasable silicon oxide layer for molecular beam epitaxy

We present a systematic study of the oxidation and deoxidation behaviours of several kinds of ultrathin silicon oxide layers frequently used in silicon (Si) technology, which in this work serve as surface protecting layers for molecular beam epitaxy (MBE). With various characterization techniques, we demonstrate that a chemically grown silicon oxide layer is the most promising candidate for subsequent removal in an ultra-high vacuum chamber at a temperature of 1000 ∘C, without making use of a reducing agent. As a demonstration, a tensile-strained Ge(100) layer is epitaxially grown on the deoxidised wafer with an atomically flat surface and a low threading dislocation density of 3.33 × 108 cm−2. Our findings reveal that the ultra-thin oxide layer grown using a chemical approach is able to protect Si surfaces for subsequent MBE growth of Ge. This approach is promising for the growth of III/V-on-Si (using Ge as a buffer) and all group-IV related epitaxy for integration on the Si photonics platforms.

Dual-Step Selective Homoepitaxy of Ge with Low Defect Density and Modulated Strain Based on Optimized Ge/Si Virtual Substrate.

In this manuscript, a novel dual-step selective epitaxy growth (SEG) of Ge was proposed to significantly decrease the defect density and to create fully strained relaxed Ge on a Si substrate. With the single-step SEG of Ge, the threading defect density (TDD) was successfully decreased from 2.9 × 107 cm−2 in a globally grown Ge layer to 3.2 × 105 cm−2 for a single-step SEG and to 2.84 × 105 cm−2 for the dual-step SEG of the Ge layer. This means that by introducing a single SEG step, the defect density could be reduced by two orders of magnitude, but this reduction could be further decreased by only 11.3% by introducing the second SEG step. The final root mean square (RMS) of the surface roughness was 0.64 nm. The strain has also been modulated along the cross-section of the sample. Tensile strain appears in the first global Ge layer, compressive strain in the single-step Ge layer and fully strain relaxation in the dual-step Ge layer. The material characterization was locally performed at different points by high resolution transmission electron microscopy, while it was globally performed by high resolution X-ray diffraction and photoluminescence.

Single-Step Electrochemical Liquid–Liquid–Solid-Assisted Growth of Ge–Sn Nanostructures as a Long-Life Anode Material with Boosted Areal Capacity

Single-Step Electrochemical Liquid–Liquid–Solid-Assisted Growth of Ge–Sn Nanostructures as a Long-Life Anode Material with Boosted Areal Capacity

Investigation of the Integration of Strained Ge Channel with Si-Based FinFETs.

In this manuscript, the integration of a strained Ge channel with Si-based FinFETs was investigated. The main focus was the preparation of high-aspect-ratio (AR) fin structures, appropriate etching topography and the growth of germanium (Ge) as a channel material with a highly compressive strain. Two etching methods, the wet etching and in situ HCl dry etching methods, were studied to achieve a better etching topography. In addition, the selective epitaxial growth of Ge material was performed on a patterned substrate using reduced pressure chemical vapor deposition. The results show that a V-shaped structure formed at the bottom of the dummy Si-fins using the wet etching method, which is beneficial to the suppression of dislocations. In addition, compressive strain was introduced to the Ge channel after the Ge selective epitaxial growth, which benefits the pMOS transport characteristics. The pattern dependency of the Ge growth over the patterned wafer was measured, and the solutions for uniform epitaxy are discussed.

Growth, Electronic and Electrical Characterization of Ge-Rich Ge-Sb-Te Alloy.

In this study, we deposit a Ge-rich Ge–Sb–Te alloy by physical vapor deposition (PVD) in the amorphous phase on silicon substrates. We study in-situ, by X-ray and ultraviolet photoemission spectroscopies (XPS and UPS), the electronic properties and carefully ascertain the alloy composition to be GST 29 20 28. Subsequently, Raman spectroscopy is employed to corroborate the results from the photoemission study. X-ray diffraction is used upon annealing to study the crystallization of such an alloy and identify the effects of phase separation and segregation of crystalline Ge with the formation of grains along the [111] direction, as expected for such Ge-rich Ge–Sb–Te alloys. In addition, we report on the electrical characterization of single memory cells containing the Ge-rich Ge–Sb–Te alloy, including I-V characteristic curves, programming curves, and SET and RESET operation performance, as well as upon annealing temperature. A fair alignment of the electrical parameters with the current state-of-the-art of conventional (GeTe)n-(Sb2Te3)m alloys, deposited by PVD, is found, but with enhanced thermal stability, which allows for data retention up to 230 °C.

Tuning the configuration of quantum dot molecules grown on stacked multilayers of heteroepitaxial islands

Arrays of Ge quantum dot molecules were grown by molecular beam epitaxy using a template, composed of a multilayer structure with layers of vertically aligned three-dimensional (3D) Ge islands buried in an Si crystal matrix with the Si capping layer on top. Depending on preparation conditions, the molecules assume various configurations, including a square frame with [001]–[010]-oriented sides. It was shown by scanning tunneling microscopy that the 3D islands are located closer to the buried SiGe mound centers with the increase of the capping layer thickness. The mechanism of the quantum dot molecule formation is ascribed to strain relaxation. It was confirmed by Monte Carlo simulations of heteroepitaxial Ge growth on the template, containing the buried Ge mound.

Distribution of charge carrier concentrations in epitaxial Ge and GeSn layers grown on n-=SUP=-+-=/SUP=--Si(001) substrates

Heteroepitaxial Ge or Ge1-xSnx layers were grown by hot-wire chemical vapor deposition on Si(001) substrates doped heavily with a donor (As or Sb) impurity. The same layers were also grown on high-resistance Si(001) substrates for comparison. The depth profiles of carrier concentration were measured in both types of layers using the capacitance-voltage method, and carrier mobilities were measured additionally by the Hall effect method in layers on high-resistance silicon. It was found that the layers grown on high-resistance substrates were p-type, while the layers grown in the same regimes on heavily doped substrates were n-type with electron concentration n=(4-9)·1016 cm-3 in Ge layers and n=(2-4)·1017 cm-3 in GeSn layers. It was established experimentally and theoretically that the effect of autodoping of Ge and GeSn layers is lacking in the hot-wire chemical vapor deposition method. In our view, the growth of n-type Ge and GeSn layers on n+-Si(001) substrates doped heavily with a donor (As or Sb) impurity is associated with the segregation of this impurity in the process of growth of a buffer Si layer and its subsequent incorporation into growing Ge or GeSn layers. Keywords: epitaxy, doping, Ge, Si, Sn, concentration.

Segregation control for ultrathin Ge layer in Al/Ge(111) system

An impact of the vacuum anneal of Al/Ge(111) structure on the Ge segregation has been investigated to get an insight into the precise control of ultrathin Ge crystalline growth. The Al/Ge(111) structure was prepared by thermal evaporation of Al on wet-cleaned Ge(111) and then vacuum annealed without air exposure to promote Ge formation on the Al surface. The Ge formation and its chemical bonding features were evaluated by X-ray photoelectron spectroscopy analysis. In addition, changes in the average Ge thickness depending on annealing temperature and time were crudely estimated. We found that the annealing temperature had a greater effect than time on the control of sub-nanometer scale Ge growth.

Improvement of crystal quality and surface morphology of Ge/Gd2O3/Si(111) epitaxial layers by cyclic annealing and regrowth

The role of post-growth cyclic annealing (PGCA) and subsequent regrowth, on the improvement of crystal quality and surface morphology of (111)-oriented Ge epitaxial layers, grown by low temperature (300 °C) molecular beam epitaxy on epi-Gd2O3/Si(111) substrates, is reported. We demonstrate that PGCA is efficient in suppressing rotational twins, reflection microtwins and stacking faults, the predominant planar defect types in Ge(111) epilayers. Continuing Ge growth after PGCA, both at low (300 °C) and high (500 °C) temperatures, does not degrade the crystal quality any further. By promoting adatom down-climb, PGCA is observed to also heal the surface morphology, which is further improved on Ge re-growth. These results are promising for development of high-quality Ge(111) epitaxial layers for photonic and electronic applications.

Enhanced van der Waals epitaxy of germanium by out-of-plane dipole moment induced from transferred graphene on TiN/AlN multilayers

Recent advances in 3D/2D heterostructures have opened up tremendous opportunities in building highly flexible and durable optoelectronic devices. However, the inherit lack of interfacial bonding and low surface energy of van der Waals surfaces limit the nucleation and growth of 3D materials. Enhancing wettability by providing a porous buffer is effective in growing compound semiconductors on graphene while van der Waals epitaxy of Ge remains challenging. Here, the nucleation of Ge has been significantly improved from an islanded mode to granular modes by using a TiN/AlN multilayered buffer prior to Ge/graphene integration. Highly textured Ge growth with dominating (111), (220), and (311) peaks are identified by x-ray diffraction. The microstructure of the buffer TiN/AlN demonstrates a polycrystalline quality with clean interfaces between each interlayer and the substrate. Kelvin probe force microscopy measurements along the lateral TiN/AlN interface identify a potential drop corresponding to the AlN phase. This contact potential difference between TiN and AlN is the key in generating the out-of-plane dipole moment that modifies the surface energy of the monolayer graphene, resulting in enhanced wettability of the Ge adatoms nucleated on top. Surface dipole induced nucleation of 3D semiconductor thin films on 2D materials via the proper design of buffer layer is fundamentally important to enhance the 3D/2D growth toward flexible optoelectronic applications.

In-Situ Transmission Electron Microscopy Observation of Germanium Growth on Freestanding Graphene: Unfolding Mechanism of 3D Crystal Growth During Van der Waals Epitaxy.

Breakthroughs in cutting-edge research fields such as hetero-integration of materials and the development of quantum devices are heavily bound to the control of misfit strain during heteroepitaxy. While remote epitaxy offers one of the most intriguing avenues, demonstrations of functional hybrid heterostructures are hardly possible without a deep understanding of the nucleation and growth kinetics of 3D crystals on graphene and their mutual interactions. Here, the kinetics of such processes from real-time observations of germanium (Ge) growth on freestanding single layer graphene (SLG) using in-situ transmission electron microscopy are unraveled. This powerful technique provides a unique opportunity to observe new and yet unexplored phenomena, which are not accessible to the standard ex situ characterizations. Through direct observations, remote interactions are elucidated between Ge crystals through the graphene layer in double heterostructures of Ge/graphene/Ge. Notably, the data show real-time evidence of vertical Ge atoms diffusion through the graphene layer. This phenomenon is attributed to the remote interactions of Ge atoms through the graphene lattice, due to its interatomic interaction transparency. Additionally, key mechanisms governing nucleation and initial growth in graphene were systematically determined. These findings enlighten the growth mechanism of graphene and provide a new pathway for disruptive hybrid semiconductor-graphene devices.

(Invited) Selective Epitaxy of Submicron Ge Wire Structures for Photodetectors and Optical Modulators in Si Photonics

A selective-area epitaxial growth of Ge on the submicron scale is studied using chemical vapor deposition (CVD) on Si in terms of the fabrication of integrated photonic devices operating at the optical communication wavelengths of around 1.55 μm. A mesa structure of Ge on the micron scale, having a vertical pin junction, is effective for fabricating a waveguide-integrated photodetector in the optical receiver. A 3-dB cutoff frequency is obtained up to approximately 50 GHz. For a higher frequency operation, a narrower structure of submicron-wide Ge wire, having a lateral pin junction, is required. Such a wire structure is also important for the application to an electro-absorption optical intensity modulator in the optical transmitter. Structural and optical properties are investigated for a submicron-wide Ge wire on Si selectively grown by CVD.

Point defect formation near the epitaxial Ge(001) growth surface and the impact on phosphorus doping activation

First-principles calculations are used to systematically investigate the impact of surface effects on the energetic cost to incorporate point defects near the growing surface [Ge(001)] and its consequence on the dopant activation in P-doped Ge layers. We illustrate the formation enthalpy ΔHf for the incorporation of a mono-vacancy, which is the dominant point defect responsible for the electrically inactive dopant incorporation in P-doped Ge. The calculated values point toward a significant lowering of ΔHf near the growing surface in comparison to the bulk cubic Ge supercell. The impact of the surface almost vanishes beyond the sixth atomic monolayer located below the surface and the calculated ΔHf values overlap with the ones computed for a bulk cubic Ge supercell. For epitaxial Ge:P layers, grown at low growth temperatures (<450°C) using the deposition method such as the Chemical Vapor Deposition, the dopant-vacancy clusters are formed within the first few monolayers close to the growing surface. The low ΔHf values for the incorporation of a mono-vacancy near the growing surface suggest that the concentration of vacancies can be significantly enhanced with respect to the bulk Ge, which can subsequently trap more dopants and deactivate them at the surface itself. Our first-principles calculation results are in line with previously reported experimental positron annihilation spectroscopy analysis on Ge:P layers grown at 440 °C using GeH4 as gas precursor. At P concentrations above 1×1020cm−3, the mono-vacancy sized open-volume defects are passivated by at least three P atoms.

A Review of Self-Seeded Germanium Nanowires: Synthesis, Growth Mechanisms and Potential Applications.

Ge nanowires are playing a big role in the development of new functional microelectronic modules, such as gate-all-around field-effect transistor devices, on-chip lasers and photodetectors. The widely used three-phase bottom-up growth method utilising a foreign catalyst metal or metalloid is by far the most popular for Ge nanowire growth. However, to fully utilise the potential of Ge nanowires, it is important to explore and understand alternative and functional growth paradigms such as self-seeded nanowire growth, where nanowire growth is usually directed by the in situ-formed catalysts of the growth material, i.e., Ge in this case. Additionally, it is important to understand how the self-seeded nanowires can benefit the device application of nanomaterials as the additional metal seeding can influence electron and phonon transport, and the electronic band structure in the nanomaterials. Here, we review recent advances in the growth and application of self-seeded Ge and Ge-based binary alloy (GeSn) nanowires. Different fabrication methods for growing self-seeded Ge nanowires are delineated and correlated with metal seeded growth. This review also highlights the requirement and advantage of self-seeded growth approach for Ge nanomaterials in the potential applications in energy storage and nanoelectronic devices.