Gaussian Normal Basis Research Articles

Squeezing Area of the Versatile GF (2 m ) GNB Arithmetic Operators

Cryptography primitives have a prominent role in securing applications that may require low-area realizations, for example portable devices and other resource constrained devices. A given system may require support for different cryptography based protocols/ primitives. Many standardized and/or published primitives rely on arithmetic operations over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$GF\left(2^m\right)$</tex-math> </inline-formula> that occupy major area footprint. Therefore, versatile operators have been of interest to reduce the area penalty, in particular bit-serial multipliers. This paper introduces a novel scheme for versatile multiplication by the normal element in the Gaussian Normal Basis (GNB) leading to new low-area versatile GNB multiplier and inverter architectures that are presented for the first time, as far as we know. Specifically, the proposed inverters are the first versatile GNB inversion in open literature, to the best of our knowledge. Field Programmable Gate Arrays (FPGA) implementation results demonstrate that the proposed versatile multiplication and inversion techniques save almost 30% and 46%, and for Application Specific Integrated Circuits (ASIC) implementation the savings are up-to 29% and 35% respectively, in terms of area when compared to other counterparts.

Input-Latency Free Versatile Bit-Serial GF(2 m ) Polynomial Basis Multiplication

Cryptography and error correction codes are widely used for information security and data integrity services in modern digital computing and communications systems. A number of standardized and published cryptography, and error correction algorithms utilize arithmetic operations over <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula>. The polynomial basis (PB) representation of <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> elements is suitable for the support of multiple <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> fields (that is, versatility). This article considers the problem of reduced hardware efficiency of versatile <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> PB multipliers as a result of increased loading latency of the inputs and irreducible polynomial. In this context, to the best of our knowledge, this article proposes the first input-latency free versatile bit-serial <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> multiplier using PB. The superiority of the proposed versatile PB multiplier is demonstrated for the case where the multiplication&#x2019;s inputs arrive serially in terms of higher output throughput and hardware efficiency compared to existing versatile PB and Gaussian normal basis (GNB) counterparts based on the application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) realizations, respectively. The proposed versatile PB multiplier improves hardware efficiency by factors of 1.8 and 2.5, respectively, compared to the versatile PB and versatile GNB counterparts.

Secure and Efficient Exponentiation Architectures Using Gaussian Normal Basis

Exponentiation in finite fields is an essential operation used in many applications ranging from error control coding to cryptographic computations, while representation in Gaussian normal basis (GNB) offers low complexity arithmetic, especially in hardware architectures. In this article, we propose several new hardware architectures for binary exponentiation in GNB. The proposed architectures make use of different levels of precomputation and the efficient digit-level parallel-in parallel-out, and hybrid-double multipliers. We support our new designs with novel countermeasures against side-channel analysis that require minimal implementation overhead. Moreover, we obtain implementation results for all architectures and provide realistic and fair comparisons with the previously known works available in the literature. It is shown that our newly proposed architectures outperform the existing hardware architectures in terms of area and time complexities and security.

Novel GF($2_m$) Digit-Serial PISO Multipliers for the Self-Dual Gaussian Normal Bases

Security protocols such as Transport Layer Security implement the Elliptic curve digital signature algorithm (ECDSA) over different binary extension fields defined by the National Institute of Standards and Technology (NIST). Specifically, such multiple cipher-suite support is a security recommendation. Binary extension field arithmetic processors are expensive, especially if more than one field is supported. In this context, this article introduces a novel lightweight digit-serial parallel-in-serial-out (DS-PISO) design for versatile multiplication (DS-VPISO) targeting the NIST-like fields in resource constrained embedded systems where the crypto module allocation is limited. The proposed DS-VPISO multiplier offers competitive area (up to 40 percent area savings) compared to existing multiple field multiplier schemes based on results conducted on bit-serial implementations using Intel's Field programmable gate arrays. The article first presents a DS-PISO self-dual Gaussian normal basis multiplication architecture based on the trace mapping. After this, the article extends the new trace based DS-PISO multiplier to construct an architecture for the first versatile DS-PISO multiplication (DS-VPISO) targeting NIST's binary fields. The latter extension to versatile multiplication is based on novel architectures for versatile cyclic shifts and versatile multiplication by normal elements.

Subquadratic Space Complexity Multiplier Using Even Type GNB Based on Efficient Toeplitz Matrix-Vector Product

Multiplication schemes based on Toeplitz matrix-vector product (TMVP) have been proposed by many researchers. TMVP can be computed using the recursive two-way and three-way split methods, which are composed of four blocks. Among them, we improve the space complexity of the component matrix formation (CMF) block. This result derives the improvements of multiplication schemes based on TMVP. Also, we present a subquadratic space complexity $GF(2^m)$ multiplier with even type Gaussian normal basis (GNB). In order to design the multiplier, we formulate field multiplication as a sum of two TMVPs and efficiently compute the sum. As a result, for type 2 and 4 GNBs, the proposed multipliers outperform other similar schemes. The proposed type 6 GNB is the first subquadrtic space complexity multiplier with its explicit complexity formula.

High‐throughput Dickson basis multiplier with a trinomial for lightweight cryptosystems

In this study, the authors propose a high-throughput systolic Dickson basis multiplier over GF(2m). Use of the Dickson basis seems promising when no Gaussian normal basis exists for the field, and it can easily carry out both squaring and multiplication operations. Many squaring operations and multiplications are needed when computing the digital signatures of elliptic curve digital signature algorithm. The proposed systolic Dickson basis multiplier can concurrently compute a great number of multiplications with a high-throughput rate, thereby substantially increasing the speed of computation for digital signatures.

A class of Gaussian normal bases and their dual bases

Optimal normal bases of 𝔽3n are desirable in pairing based cryptography for the fast implementation of arithmetic in the ternary finite fields. But for the finite fields 𝔽3n optimal normal bases are not possible for every n. Therefore the low complexity normal bases are desirable in such cases. There are low complexity Gaussian normal bases which are obtained from Gauss periods. We discuss the existence of Gaussian normal bases and their dual bases for a specific class of the finite fields with characteristic 3.

Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications

This study presents an efficient and high‐speed very large‐scale integration implementation of point multiplication on binary Edwards curves over binary finite field GF(2m) with Gaussian normal basis representation. The proposed implementation is a low‐cost structure constructed by one digit‐serial multiplier. In the proposed scheduling of point multiplication, the field multiplier is busy during point addition and point doubling computations. In the field multiplier structure, by using the logical effort technique the delay is optimally decreased and the drive ability of the circuit in the point multiplication architecture is increased. Also, to reduce area and number of transistors of the point multiplication circuit, all components are selected based on low‐cost structures. The design is implemented in 0.18 μm CMOS technology over binary finite field GF(2233). The results confirm the validity of the proposed structure and its high performance in terms of delay and area cost.

Decomposition of symmetric matrix–vector product over GF (2 m )

Toeplitz matrix–vector product (TMVP) decomposition is an important approach for designing and implementing subquadratic multiplier. In this Letter, a symmetric matrix (SM), which is the sum of a symmetric TM and Hankel matrix, is proposed. Applying the symmetry property, 2-way, 3-way and n-way splitting methods of SMVP is presented. On the basis of 2-way splitting method, the recursive formula of SMVP is presented. Using the two cases n = 4 and 8, the SMVP decomposition approach has less space complexity than 2-way TMVP, TMVP block recombination and symmetric TMVP for even-type Gaussian normal basis multiplication.

Low-Complexity Digit-Level Systolic Gaussian Normal Basis Multiplier

Normal basis multiplication over $GF(2^{m})$ is widely used in various applications such as elliptic curve cryptography. As a special class of normal basis with low complexity, Gaussian normal basis (GNB) has received considerable attention recently. In this paper, we propose a novel decomposition algorithm to develop a digit-level (DL) low-complexity systolic structure for GNB multiplication over $GF(2^{m})$ . First, we propose two algorithms separately to achieve a systolic GNB multiplier with low critical path delay and low register complexity. Next, we present the corresponding structure according to the proposed algorithm (combination of previous two proposed algorithms). Compared with the existing systolic DL GNB multipliers (through both the theoretical and application-specific integrated circuit comparison), the proposed multiplier achieves significantly less area-delay product (ADP), e.g., for a systolic structure of digit size of 8 for $GF(2^{409})$ , the proposed structure has 12.3% less ADP compared to the best of the existing designs, for the same digit size.

Gaussian normal basis multiplier over GF(2m) using hybrid subquadratic‐and‐quadratic TMVP approach for elliptic curve cryptography

In recent years, subquadratric‐and‐quadratric Toeplitz matrix–vector product (TMVP) computations are widely used for the implementation of binary field multiplication in elliptic curve cryptography. Pure subquadratric TMVP structure involves significantly less space complexity and long computational delay, while quadratric TMVP structure involves larger space complexity and less computation delay. To optimise the tradeoff between time and space complexities, this study presents a novel hybrid multiplier for Gaussian normal basis (GNB) in GF(2m) which combines subquadratic and quadratic structures. From the theoretical analysis, it is shown that the proposed hybrid multiplier can save ∼18% space complexity and 12% time complexity than the existing GNB multiplier with pure TMVP decomposition.

High-speed hardware implementation of Gaussian normal basis inversion algorithm over [formula omitted]

In this paper a high-speed hardware structure for implementation of Itoh-Tsujii Inversion Algorithm (ITA) based on Gaussian normal basis hybrid-double multiplier is presented. To reduce the latency of the inversion operation, a hybrid-double multiplication with the number of clock cycles equal to a single multiplication is applied. Based on an efficient addition chain, double multiplication instead of single multiplication is used for implementation of inversion computations. In this case, two field multiplications are computed in parallel structure by hybrid-double multiplier. The proposed architecture is simple, low-cost and also the number of clock cycles in the structure are reduced compared to existing works. The proposed method over the binary finite fields F2163 and F2233 has been successfully verified and implemented on Virtex-4 XC4VLX100 and Virtex-5 XC5VLX110 FPGAs. The computation time of the structure on Virtex-5 FPGA family are 116.25ns and 128.065ns over two finite fields F2163 and F2233 respectively. The comparison results with other previous implementations of the inversion operation verify that the proposed method has better improvement in terms of execution time and performance.

Efficient and low‐complexity hardware architecture of Gaussian normal basis multiplication over GF(2 m ) for elliptic curve cryptosystems

In this paper, an efficient high-speed architecture of Gaussian normal basis (GNB) multiplierover binary finite field GF(2m) is presented. The structure is constructed by using some regular modules for computation of exponentiation by powers of 2 and low-cost blocks for multiplication by normal elements of the binary field. For the powers of 2 exponents, the modules are implemented by some simple cyclic shifts in the normal basis representation. As a result, the multiplier has a simple structure with a low critical path delay. The efficiency of the proposed multiplier is examined in terms of area and time complexity based on its implementation on Virtex-4 field programmable gate array family and also its application specific integrated circuit design in 180 nm complementary metal–oxide–semiconductor technology. Comparison results with other structures of the GNB multiplier verify that the proposed architecture has better performance in terms of speed and hardware utilisation.

New Architectures for Digit-Level Single, Hybrid-Double, Hybrid-Triple Field Multiplications and Exponentiation Using Gaussian Normal Bases

Gaussian normal bases (GNBs) are special set of normal bases (NBs) which yield low complexity $GF\left(2^{m}\right)$ arithmetic operations. In this paper, we present new architectures for the digit-level single, hybrid-double, and hybrid-triple multiplication of $GF\left(2^{m}\right)$ elements based on the GNB representation for odd values of $m > 1$ . The proposed fully-serial-in single multipliers perform multiplication of two field elements and offer high throughput when the data-path capacity for entering inputs is limited. The proposed hybrid-double and hybrid-triple digit-level GNB multipliers perform, respectively, two and three field multiplications using the same latency required for a single digit-level multiplier, at the expense of increased area. In addition, we present a new eight-ary field exponentiation architecture which does not require precomputed or stored intermediate values.

On the Complexity of the Dual Bases of the Gaussian Normal Bases

In this paper, we study the complexity of the dual bases of the Gaussian normal bases of type (n, t), for all n and t = 3, 4, 5, 6, of 𝔽qn over 𝔽q and provide conditions under which the complexity of the Gaussian normal basis of type (n, t) is equal to the complexity of the dual basis over any finite field.

High-Performance Two-Dimensional Finite Field Multiplication and Exponentiation for Cryptographic Applications

Finite field arithmetic operations have been traditionally used in different applications ranging from error control coding to cryptographic computations. Among these computations are normal basis multiplications and exponentiations which are utilized in efficient applications due to their advantageous characteristics and the fact that squaring (and subsequent powering by two) of elements can be obtained with no hardware complexity. In this paper, we present 2-D decomposition systolic-oriented algorithms to develop systolic structures for digit-level Gaussian normal basis multiplication and exponentiation over $ {GF}({2}^{m})$ . The proposed high-performance architectures are suitable for a number of applications, e.g., architectures for elliptic curve Diffie–Hellman key agreement scheme in cryptography. The results of the benchmark of efficiency, performance, and implementation metrics of such architectures through a 65-nm application-specific integrated circuit platform confirm high-performance structures for the multiplication and exponentiation architectures presented in this paper are suitable for high-speed architectures, including cryptographic applications.

Subquadratic space complexity Gaussian normal basis multipliers overGF(2m) based on Dickson–Karatsuba decomposition

Gaussian normal basis (GNB) of the even-type is popularly used in elliptic curve cryptosystems. Efficient GNB multipliers could be realised by Toeplitz matrix-vector decomposition to realise subquadratic space complexity architectures. In this study, Dickson polynomial representation is proposed as an alternative way to represent an GNB of characteristic two. The authors have derived a novel recursive Dickson–Karatsuba decomposition to achieve a subquadratic space-complexity parallel GNB multiplier. By theoretical analysis, it is shown that the proposed subquadratic multiplier saves about 50% bit-multiplications compared with the corresponding subquadratic GNB multiplication using Toeplitz matrix-vector product approach.

Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications

Normal basis multiplication in finite fields is vastly utilized in different applications, including error control coding and the like due to its advantageous characteristics and the fact that squaring of elements can be obtained without hardware complexity. In this brief, we present decomposition algorithms to develop novel systolic structures for digit-level Gaussian normal basis multiplication over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ). The proposed architectures are suitable for high-performance applications, which require fast computations in finite fields with high throughputs. We also present the results of our application-specific integrated circuit synthesis using a 65-nm standard-cell library to benchmark the effectiveness of the proposed systolic architectures. The presented architectures for multiplication can result in more efficient and high-performance VLSI systems.

High-performance elliptic curve cryptoprocessors over $$\varvec{GF(2^{m})}$$ G F ( 2 m ) on Koblitz curves

Efficient computation of the finite field arithmetic is required for elliptic curve cryptography over $$G\!F\!(2^{m})$$GF(2m). In order to achieve the above, this paper presents the design of high-performance cryptoprocessors over $$G\!F\!(2^{163})$$GF(2163) and $$G\!F\!(2^{233})$$GF(2233) using finite field multipliers with digit-level processing. The arithmetic operations were implemented in hardware using Gaussian normal bases representation and the scalar point multiplication kP was performed on Koblitz curves using window-$$\tau $$?NAF algorithm with w = 2, 4 and 8. The cryptoprocessors were designed using VHDL description, synthesized on the FPGA Stratix-V using Quartus II 13.0, and verified using ModelSIM and Matlab. The simulation results show that the cryptoprocessors present a very good performance using low area. In this case, the processing times for calculating the scalar point multiplication over $$G\!F\!(2^{163})$$GF(2163) and $$G\!F\!(2^{233})$$GF(2233) for w = 2, 4 and 8 were 9.1, 6.7 and 5.1, and 12.9, 9.5 and 6.8 $$\upmu $$μs, respectively.

Parallel and High-Speed Computations of Elliptic Curve Cryptography Using Hybrid-Double Multipliers

High-performance and fast implementation of point multiplication is crucial for elliptic curve cryptographic systems. Recently, considerable research has investigated the implementation of point multiplication on different curves over binary extension fields. In this paper, we propose efficient and high speed architectures to implement point multiplication on binary Edwards and generalized Hessian curves. We perform a data-flow analysis and investigate maximum number of parallel multipliers to be employed to reduce the latency of point multiplication on these curves. Then, we modify the addition and doubling formulations and employ a newly proposed digit-level hybrid-double Gaussian normal basis multiplier to remove the data dependencies and hence reduce the latency of point multiplication. To the best of our knowledge, this is the first time that one employs hybrid-double multiplication technique to reduce the computation time of point multiplication. Moreover, we have implemented our proposed architectures for point multiplication on FPGA and obtained the results of timing and area. Our results indicate that the proposed scheme is one step forward to improve the performance of point multiplication on binary Edward and generalized Hessian curves.