Gate Work Function Research Articles

Highly sensitive N+ pocket doped vertical tunnel FET biosensor with wide range work function modulation gate electrodes

This manuscript addresses the first time implementing binary metal alloy’s wide range work function gate electrodes along with N+ Si0.55Ge0.45 pocket in charge plasma dielectric modulated vertical TFET (LGW-CPDM-VTFET) for label-free biomolecules sensing application utilizing the single ZnO cavity. The ZnO cavity is covalently functionalized with the intended biomolecules injected in the cavity. Then the variation in the electrical characteristics and performance parameters of LGW-CPDM-VTFET are perceived for their correct recognition. Drain current sensitivity, Ion/Ioff sensitivity, and Sub-threshold Slope (SS) sensitivity are estimated and analyzed utilizing the proposed biosensor structure to identify biomolecules present in the cavity. The designed biosensor manifests higher sensitivity for immobilizing higher dielectric constant biomolecules. The attained results exhibit that Keratin (k = 8) has to drain current sensitivity of 9707, which is 44% and 93% greater than the drain current sensitivity of Bacteriophage T7 (k = 6.3) and Glucose Oxidase (k = 3.46). In contrast, its drain current sensitivity is 55% and 108% lower than the drain current sensitivity of Staphylococcal nuclease (k = 10) and Gelatin (k = 12), respectively. The designed biosensor can extend the bio-sensing applicability due to its high performance, and it would be a better alternative for CMOS biosensor and FET Biosensor.

A label-free dielectric-modulated biosensor using SiGe-heterojunction dual cavity dual metal electrically doped TFET

The detection of biomolecules has been accomplished in this article by using the tunnel field effect transistor’s (TFET) bipolar nature. The fabrication procedure has been made simpler, the prices have gone down, and random dopant fluctuation (RDFs) have been eliminated using the charge plasma concept. The objective of this work is to investigate the performance of a DopingLess- Dual Metal Gate- Dual Cavity- HeteroJunction- Tunnel Field Effect Transistor (DL-DMG-DC-HJ-TFET) biosensor that can sense biomolecules in both the ON and ambipolar states. It is feasible to recognize many types of biomolecules concurrently by taking into account the cavities at both tunneling junctions. The suggested biosensor’s OFF state current has been reduced and its sensitivity has been increased via the use of gate workfunction engineering and bandgap engineering. It has been investigated how the presence of proteins in the cavities affects electrical properties such as energy band diagram (EBD), surface potential (SP), subthreshold Swing (SS), threshold voltage , and current ratio The impact of temperature, germanium mole fraction, and position of biomolecules is also analyzed in this work. A comparative analysis for drain current sensitivity is presented considering different previous works.

Study of Electrical Characteristics for Dual-Gate TFTs With Asymmetric Defect Distributions and Gate Work Functions

Combined effects of asymmetric defect distributions and asymmetric gate work functions (WFs) on the performances of self-aligned dual-gate poly-Si TFTs are investigated. Normally, small grains with plentiful grain boundaries (GBs) or other structural defects appear at different positions of the poly-Si film, which is dependent on the growth process of the film. Subgap states of acceptor-like tail, acceptor-like deep-level, donor-like tail, and donor-like deep-level states are used to emulate the defects. Two sets of density of states (DOS) are employed. We find that defects at different positions of the source-side and drain-side channels exhibit different influences on TFT performance and the influences are dependent on the WFs of the gates. TFTs with a higher gate WF can have a higher tolerance to the depth of the defect region. Besides the electrical characteristics, the combined effects of defects and gate WFs on current density distributions and electric field distributions in the channel regions are explored. The performance variations caused by the asymmetric defects along with asymmetric gate WFs can be explained.

Design technique co-optimization approach to GAA FETs for inverter design at advanced technology node

Gate-all-around Nanosheet field-effect transistor (GAA-NSFET) is a potential replacement for the state-of-art FinFET devices at advanced technology nodes. In this article, the impact of process-induced variability such as gate work function variation (WFV) on NSFETs using 3D TCAD numerical device simulation is studied. The WFV of NSFETs and NWFETs using multiple stack channels are also analyzed. The fluctuation in the threshold voltage (σVTH) and on-current (σION) of NSFETs is mainly affected by the WFV of the metal gate. It is investigated that single and 3-stacked NSFET shows superior immunity to WFV compared to NWFET. Furthermore, a layout-based NSFET inverter design using the DTCO technique is followed and the advantages of the stacked NSFET in terms of delay, power dissipation and switching energy are also reported.

Design and simulation of junctionless nanowire tunnel field effect transistor for highly sensitive biosensor

This paper investigates symmetrical design of a Junctionless Nanowire Tunnel-Field-Effect-Transistor (JL-NWTFET) for highly sensitive biosensor. JL-NWTFET deployed using Gate-All-Around (GAA) structure and Dielectric-Modulation (DM) technique to detects the bio-logical molecules such as uricase, streptavidin, protein, biotin, uriease, Amino-propyl triethoxysilane (APTS), ChOx etc. The variation in the drain current (ID), subthreshold slope (SS), transconductance (gm), and ION/IOFF ratio considered as the sensitivity parameters of the JL-NWTFET to detect different biological molecules in the cavity area. The cavity area is formed by a layer in between the source-gate oxides and source-gate electrodes. The JL-NWTFET shows the reduced leakage currents in terms of Short-Channel-Effects (SCEs) and superior controllability over the channel. The proposed JL-NWTFET has been designed with uniform doping concentration (1 × 10−19 cm−3), and gate work-function (φgate = 4.8eV). The high sensitivity (∼109) is observed for APTS biomolecule with dielectric constant (K = 3.57).

Total ionizing dose effect of bulk and SOI P-FinFET with linear workfunction modulation technology

The effect total ionizing dose on a linear gate workfunction modulated SOI P-FinFET is analyzed and compared with the bulk P-FinFET. This technique improves the device electrostatic integrity for pre and post radiation condition. A decade improvement in IOFF is obtained for both the bulk and proposed devices. Moreover, both the SOI devices offer 35% and 29% less subthreshold swing for pre-rad condition. After irradiation trap charges are accumulated in oxide and semiconductor/insulator interfaces, which makes threshold more negative. The linear gate workfunction modulation gives more Vth for both devices. At high radiation of 2000 krad dose proposed SOI device shows 39% more threshold voltage as compared to LGWM bulk P-FinFET. The maximum Vth shift is observed in single workfunction bulk P-FinFET. Based on the simulation results, the proposed SOI P-FinFET is proved to be better TID tolerant and reliable.

Performance analysis of metal gate engineered junctionless nanosheet fet with a ft/fmax of 224/342ghz for beyond 5g (b5g) applications

This manuscript for the first time investigates the effect of Dual Metal on Gate Junctionless Nanosheet FET (DMG-JL-NSFET) for analog/RF applications. The entire analysis is performed for gate length (Lg) = 16 nm at 10μA/μm to focus the weak/moderate inversion region of operation. The results show a whooping amount of reduction in terms of output conductance (gds) (∼88.8%) due to the screening effect thereby enhancing the intrinsic gain (AV) (∼28.97%) of the DMG-JL-NSFET as compared to SMG-JL-NSFET. It is also found that the cut-off frequency (fT) and maximum oscillation frequency (fMAX) are increased by an amount of ∼11.82% and ∼2.91% respectively for DMG-JL-NSFET. Furthermore, it is elucidated that increasing the metal gate work function work difference (ΔW = φms-φmd) reduces the analog/RF performance of the DMG-JL-NSFET. The analysis revealed that increasing the ΔW from 0.3eV to 0.7eV deteriorates AV, fT, fMAX by an amount of ∼17.35%, ∼19.21%, and ∼37.57% respectively. Moreover, the implementation of HfO2 as high-k gate dielectric as a replacement for SiO2 degrades the analog/RF efficiency of DMG-JL-NSFET. Moreover, the DMG-JL-NSFET has provided a greater fT (∼224 GHz)/fMAX (∼342 GHz) indicating a promising candidature for future beyond 5G (B5G) applications.

Investigation of Breakdown in Vertical E-Mode Ga2O3 MOSFET with Different Structural Parameters

In order to control drain-induced barrier lowering (DIBL) and thus premature breakdown in enhancement-mode (E-mode) Ga2O3 MOSFETs, the effect of structure and process parameters on the breakdown voltage (VBK) and DIBL is systematically investigated. The results show that the small gate work function, the small oxide dielectric constant, the thick oxide thickness, the excessive doping concentration of the epitaxial layer, and the wide and short channel will lead to a severe DIBL effect, causing the device to breakdown prematurely. On the other hand, the thickness of the drift region has a marginal effect on the DIBL, and after excluding other structural parameters that generate a strong DIBL effect, a reasonable increase in the thickness of the drift region is beneficial to improve the VBK of devices. This study can contribute to the design of Ga2O3 MOSFETs in the application scenario with high VBK reliability requirements.

Performance Assessment of a Junctionless Heterostructure Tunnel FET Biosensor Using Dual Material Gate

Biosensors based on tunnel FET for label-free detection in which a nanogap is introduced under gate electrode to electrically sense the characteristics of biomolecules, have been studied widely in recent years. In this paper, a new type of heterostructure junctionless tunnel FET biosensor with an embedded nanogap is proposed, in which the control gate consists of two parts, namely the tunnel gate and auxiliary gate, with different work functions; and the detection sensitivity of different biomolecules can be controlled and adjusted by the two gates. Further, a polar gate is introduced above the source region, and a P+ source is formed by the charge plasma concept by selecting appropriate work functions for the polar gate. The variation of sensitivity with different control gate and polar gate work functions is explored. Neutral and charged biomolecules are considered to simulate device-level gate effects, and the influence of different dielectric constants on sensitivity is also researched. The simulation results show that the switch ratio of the proposed biosensor can reach 109, the maximum current sensitivity is 6.91 × 102, and the maximum sensitivity of the average subthreshold swing (SS) is 0.62.

Application of a Charge Plasma Tunnel FET with SiGe Pocket as an Effective Hydrogen Gas Sensor

In this article, we have investigated the potential applications of a charge plasma TFET with a source pocket (SP-CPTFET) as a hydrogen gas sensor. The Si0.6Ge0.4 source pocket and HfO2 gate dielectric together greatly enhance the drain current. The presence of an intrinsic silicon body in the channel and drain controls the leakage current. Palladium (Pd) is considered the top and bottom gate catalyst for hydrogen (H2) gas sensing. The flat band voltage and CV properties of the sensor change as a result of the adsorption of H-atoms at the Pd-HfO2 and Pd surfaces. As a result, the gate work-function () modulates, affecting the drain current. The electrical analysis of the sensor is carried out in terms of transfer characteristics, band energy, current ratio, interband tunneling rate, and electric field. Additionally, the suggested sensor’s drain current sensitivity and current ratio sensitivity are estimated for various H2 pressure concentrations. The scope of the investigation has been expanded to include the effect of variation in the H2 gas pressure, germanium mole fraction, temperature, pocket length, interface trap charges (ITC), oxide thickness variation, and comparison of different catalytic metals on the drain current performance. The reported sensor exhibits a much-improved drain current sensitivity and current ratio sensitivity compared to the CPTFET gas sensor.

Investigation of Si 1−X GeX source dual material stacked gate oxide pocket doped hetero-junction TFET for low power and RF applications

ABSTRACT In this paper, the applicability of dual material stacked gate-oxide-Pocket doped-hetero-junction tunnel field effect transistor (DMSGO-PD-HTFET) for low power switching and radio frequency (RF) applications is investigated. In this context, gate workfunction engineering, the stacked-gate-oxide (+) approach, and asymmetrical doping at the P+ source () and N+ drain regions are considered. N+ pocket at source-channel interface implements DMSGO-PD-HTFET and improves interband tunnelling rate. This research aims to improve the device’s switching ratio (/), average subthreshold swing (), and radio frequency (RF) performance. For this, the control gate work function, mole fraction (X), pocket thickness, and doping concentration are optimised. Next, the DC, analog/RF and linearity figure of merits of the proposed device is analysed and the performance is compared with conventional all-silicon dual-material stack gate oxide tunnel field effect transistor (DMSGO-TFET) and dual-material stacked gate oxide-hetero-junction tunnel field effect transistor (DMSGO-HTFET) with source using technology computer-aided design (TCAD) device simulator. Based on the comparative analysis, the optimised design with exhibits an average subthreshold swing () of 28.8 mV/decade, switching ratio (/) of 2 × 1012, cut-off frequency () of 216 (GHz), and other significant improvements in analog/RF and linearity performance parameters. The proposed device is therefore suitable for switching and RF applications.

Ambipolar performance improvement of the C-shaped pocket TFET with dual metal gate and gate–drain underlap

Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET). The effects of gate work function and gate–drain underlap length on the DC characteristics and analog/RF performance of CSP-TFET devices, such as the on-state current (I on), ambipolar current (I amb), transconductance (g m), cut-off frequency (f T) and gain–bandwidth product (GBP), are analyzed and compared in this work. Also, a combination of both the dual-metal gate and gate–drain underlap designs has been proposed for the C-shaped pocket dual metal underlap TFET (CSP-DMUN-TFET), which contains a C-shaped pocket area that significantly increases the on-state current of the device; this combination design substantially reduces the ambipolar current. The results show that the CSP-DMUN-TFET demonstrates an excellent performance, including high I on (9.03 × 10−9 A/μm), high I on/I off (∼1011), low SSavg (∼13 mV/dec), and low I amb (2.15 × 10−2 A/μm). The CSP-DMUN-TFET has the capability to fully suppress ambipolar currents while maintaining high on-state currents, making it a potential replacement in the next generation of semiconductor devices.

An intensive study on effects of lateral scaling and gate metals on the RF/DC performance of recessed T-gated Fe-doped AlN/GaN/SiC HEMTs for future RF and microwave power applications

In this simulation work, the effect of AlxGa1-xN and InxGa1-xN back barriers (BB) on the RF & DC performances of recessed T-gated Fe-doped AlN/GaN/SiC HEMT device is investigated. The novel HEMT achieved a peak GM of 435.9 mS/mm, the highest ID of 1.89 A/mm, and a maximum fT of 197.4 GHz with Al0.18Ga0.82N BB which can be attributed to enhanced mobility and carrier confinement in the quantum well (QW) due to the integration of BB, presence of Fe-doping in the GaN buffer in conjunction with recessed T-gate approach. On the other hand, the device with In0.20Ga0.80N BB recorded a peak GM of 434.9 mS/mm, a peak ID of 1.83 A/mm, and a maximum fT of 196.4 GHz. The flatness GM is attributable to the applied high drain bias of 5 V. The device performance deteriorated with an increase of Al and In mole fractions of the BB layers following an increased dislocation density which influenced the epitaxial quality of the heterostructures. This paper also investigates the impact of gate metals on the electrical performance of the Al0.18Ga0.82N and In0.20Ga0.80N BB devices. In both cases, the TCAD results revealed that the HEMT with lower ϕm (work function) gate metal i.e., Al-gate exhibited superior DC/RF performance. Owing to an uplift of the conduction band edge the performance degraded following the raise of the Schottky barrier that leads to the collection of the least number of carriers at the AlN/GaN interface hence resulting in poor sheet carrier density. Besides, the gate metal Pt with the highest work function of 5.65 eV is suitable to pursue E-Mode operation. In addition, the simulation to explore the impact of scaling source-drain spacing (LSD) revealed that limiting gate-to-drain distance (LGD) and gate-to-source distance (LGS) is the key to achieve enhance RF/DC performance. It is no surprise that this device is at the forefront of the future 5G/6G, military, defense, and RF power applications.

Design and sensitivity estimation of linear graded work function gate electrode hetero junction vertical TFET biosensor

Design and sensitivity estimation of linear graded work function gate electrode hetero junction vertical TFET biosensor

Performance Analysis of Gate Engineered High-K Gate Oxide Stack SOI Fin-FET for 5 nm Technology

Abstract: This paper analyses the performance of 5 nm gate length gate engineered oxide stack silicon on insulator (SOI) fin field-effect transistor (OS-Fin-FET) for the first time. The high dielectric (High-K) value of the material-based gate oxide stack structure increases both the analog and the radio frequency (RF) performance of the Fin-FET device when compared to standard single gate oxide material structures. The work function of the engineered gate structure further helps in advancing the performance of the device in terms of on current (Ion), off current (Ioff) and the ratio of Ion/Ioff. The proposed OS-FinFET device improves on current (Ion) of the device by 12% in comparison to the high-K dielectric gate oxidebased FinFET device. Simulation of the device is further extended to study different electrical characteristics of the proposed device under other biasing conditions, to estimate enhanced analog and RF performance where the device is highly suitable for low power and high-speed applications. Overall, the proposed device shows improvement in existing architectures of the devices. Technology computer-aided design (TCAD) tool is used to perform entire simulations of the proposed device with 5 nm gate length. Aim: To enhance analog and RF performance of the Fin-FET device at 5 nm gate length. Background: Design of the sub-10 nm Fin-FET device undergoes charge shearing phenomena because of the minimum distance between source and drain. This problem is addressed by using High-K spacer over substrate but it leads to increase in the channel resistance and adverse short channel effects. A combination of different high-K dielectric materials can eliminate this performance. Hence most of the studies concentrated on spacer region and failed to consider channel region. This study tries to improve analog performance of the device using the approach of gate engineering with gate stack approach. Objective: The main objective of this study is to increase on current (Ion) of the device by implementing gate engineering approach, by choosing dual work function-based gate with oxide stack approach. The High-K dielectric material-based gate oxide reduces leakage current, decreases off current which will increase the ratio of Ion/Ioff. Methods: The dual work function gate material is taken with gate oxide stack approach by considering different High-K dielectric materials like HfO2, TiO2 with thin SiO2 layer as the interactive layer. Simulation of the device is carried out using TCAD Tool and results are compared with existing literature, to validate the results. Results: The proposed architecture of the Fin-FET device delivers excellent results in terms of on current and subthreshold characteristics compared to existing literature. The proposed device gives high on current of 0.027 A and current ratio of 1.08X104. Conclusion: A complete comparative analysis is carried out with existing literature on the proposed device, where the proposed device resulted in high performance. The proposed device improves 12% compared to existing literature, which is highly suitable for low power applications.

Design and Performance Assessment of Split Gate Dielectric Modulated Junction less TFET Variation of Hfo2 by the Divided Gate Insulator for High Sensitivity Using Tcad Simulation

A number of more recent discoveries in microbiology have made reliable identification of nano-biomolecules and extensive analyses of them necessary. A variety of proteins, including DNA, biotin-streptavidin, amino acids, as well as many types of bacteria and viruses, must be found and analyzed in order to fully comprehend any odd behavior occurring inside of live cells. Rapid testing and detection are essential steps in preventing undiscovered biohazards from eradicating the human race and other terrestrial living things. Since many decades ago, developing an accurate, affordable biosensor has been a struggle for scientists [1]. When compared to pricey laboratory-based sensors and detection methods, FET-based lab-on-chip nano biosensors appear to be a promising substitute. It is significantly more dependable than conventional bulk sensors because of its size, affordability, low power consumption, resilience, faster response time, and better sensitivity [1]. Due to their precision, adaptability, and compatibility with embedded systems, dielectrically modulated FET biosensors with Nano cavities are emerging as a promising research area that can yield useful data on bio-analyses. As an alternative to conventionally doped TFET devices, using a charge plasma SiGe-heterojunction double gate TFET, a label-free biosensor can be produced, bypassing the need for conventional semiconductors, which require a large thermal budget and are susceptible to random dopant fluctuations (RDFs). The effect of changing the dielectric constant (k), the positive and negative charge density, the gate work function, and the cavity size has been investigated to better understand how these factors affect the performance of the proposed biosensor. These parameters modify the biosensor's electric characteristics, improving detection [2]. There is also discussion of how these factors influence the device's drain current, electric field, surface potential, sub-threshold swing (SS), insulator-to-metal film (ION/IOFF) ratio, and electron tunneling rate (ETR). The sensitivity of the drain current in the proposed biosensor is also investigated. There is no restriction on whether or whether the proposed structure is used for charged or neutral molecules.Under lower supply voltages, it is discovered that the SG-DM current JLFET's sensitivity is high, measuring 1.2 *10^3, with a potential sensitivity of 1.4 V. A result, the SG-DM [2] JLFET exhibits good application potential while consuming little power and having ahigh sensitivity.

Extended Work Function Shift of Large‐Area Biofunctionalized Surfaces Triggered by a Few Single‐Molecule Affinity Binding Events

AbstractFew binding events are here shown to elicit an extended work function change in a large‐area Au‐surface biofunctionalized with ≈108 capturing antibodies. This is demonstrated by Kelvin probe force microscopy (KPFM), imaging a ≈105 µm2 wide Au‐electrodes covered by a dense layer (≈104 µm−2) of physisorbed anti‐immunoglobulin‐M (anti‐IgM). A 10 min incubation in 100 µL phosphate buffer saline solution encompassing ≈10 IgM antigens (10−19 mole L−1  102 × 10−21 m) produces a work function shift ΔW ≈ –60 meV. KPFM images prove that this shift involves the whole inspected area. Notably, no work function change occurs upon incubation in highly concentrated (3 × 10−15 m) nonbinding IgG solutions. The ΔW measured by KPFM is in quantitative agreement with the threshold voltage shift of an electrolyte‐gated single‐molecule large‐area transistor (SiMoT). The findings provide direct experimental evidence for the SiMoT ultrahigh sensitivity, by imaging the extensive shift of the gate work function, likely arising from collective surface phenomena, elicited by single‐molecule binding events.

Study of an asymmetry tunnel FET biosensor using junctionless heterostructure and dual material gate

In recent years, label-free sensors have been studied extensively for biomolecule detections. Label-free biosensors based on MOSFETs could achieve high detection sensitivity, the subthreshold swing of such sensors cannot break the limitation of 60 mV Dec−1 due to the physical mechanism of thermal electron emission. However, subthreshold swing less than 60 mV Dec−1 can be achieved in biosensors based on tunnel FETs working in band to band tunneling (BTBT) mode. Usually, label-free biosensors have a nanogap under the gate electrode both in MOSFET and tunnel FET (TFET), which can electrically sense the characteristics of biomolecules by dielectric constant modulation effect. In this article, we propose a novel nanogap embedded and dielectric modulated asymmetry tunnel FET biosensor with junctionless heterostructure and dual material gate, where different biomolecules can be detected effectively by adjusting the workfunctions for gate electrodes. Influences of tunnel gate, auxiliary gate and back gate workfunctions on sensitivities are explored. In addition, device-level gate effects are simulated by considering neutral and charged biomolecules. The influence of different dielectric constant at fixed charge density is also studied. Simulation results show that asymmetry dual material gate junctionless heterostructure tunnel FET (ADMG-HJLTFET) biosensor can provide higher switch ratio and higher sensitivity.

(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration

Monolithic 3D-IC is one of the solutions to relieve Moore’s law with vertically integrating circuits for sub-1nm technology nodes. Therefore, thin-film transistors (TFTs) play an important role in this trend because of their low fabrication temperature to realize back-end circuits. On the other hand, 3D integrating filter, duplexer, switch, and so on is necessary as antennas array requirements increase in 5G or beyond. Consequently, it is foreseeable to adopt TFTs to implement radio frequency (RF) devices. Fig. 1 shows the schematic ideal 3D SoC for sub-1nm technology. Our previous research tried to demonstrate high-frequency back-end devices based on the gate-all-around stacked nanosheet low-temperature polycrystalline silicon channel (GAA NS LTPS). Fig.2 shows the current-voltage transfer characteristics of different width designs of LTPS and α-IGZO devices. The only way to enhance GAA NS LTPS RF devices with the same process is by increasing channels. However, it leads to a larger footprint, and the frequency doesn’t boost with increasing channels in proportion because of the capacitance between the multiple channels. In the meantime, the LTPS gate controllability becomes poor, and threshold voltage shifts significantly when the drive current is improved by widening channel width. Consequently, a-IGZO is adopted as the channel material of RF devices to solve the problem mentioned above. The a-IGZO film is back-end compatible and has transparency and high uniformity. The most important is that the gate controllability decay phenomenon is negligible no matter what the channel width is, which is helpful for different width designs. In contrast, IGZO devices can keep their threshold voltage and have ultra-low leakage current due to a large bandgap. According to the system on panel (SoP) trend, we attempt to integrate RFIC with the peripheral circuit on a substrate. Therefore, a-IGZO is also introduced as a pull-down transistor in a CMOS for power reduction and process simplicity. To further minimize the footprint, the a-IGZO devices are nanoscale and stacked on the p-type LTPS as the defined heterogeneous CFET (HCFET), which is demonstrated in the previous study [1]. In this talk, we will discuss HCFET architecture in detail. We compared junctionless mode (JL) and inversion mode (IM) for bottom p-type LTPS in HCFET. In our results, IM is better than JL as the junction structure for bottom PMOS because the requirement of the bottom channel in a HCFET is thin and width flexible for design. In addition, a trench gate of the bottom device plays an important role in HCFET. The trench tri-gate structure can avoid gate dielectric damage by plasma in the etching process, keep the top IGZO layer continuously and enhance performance compared to the general tri-gate structure. On the other hand, the gate of top n-type IGZO can be bottom gate only or dual gate for different requirements. Finally, HCFET can significantly reduce the distance between IGZO and p-type LTPS channels to save power and lower latency in the circuit.[1] S. -W. Chang et al., "First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications," in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 2101-2107, April 2022, doi: 10.1109/TED.2021.3138947. Figure 1

(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration

System-on-panel and monolithic 3D integration must be the main trend in the future. Heterogeneous channel materials need to be integrated on a chip for the different requirements. In the previous work, we innovated an advanced process to combine double gate IGZO high-frequency device and dual work function gate heterogeneous IGZO/Si CFET inverter/SRAM on a substrate. However, the heterogeneous CFET architecture is pretty complicated. Subsequently, the channel design, gate structure, and operation mode for both bottom polysilicon and top IGZO transistor are discussed in detail in this study.