Gate Voltage Characteristics Research Articles

Barrier Height, Ideality Factor and Role of Inhomogeneities at the AlGaN/GaN Interface in GaN Nanowire Wrap-Gate Transistor.

It is essential to understand the barrier height, ideality factor, and role of inhomogeneities at the metal/semiconductor interfaces in nanowires for the development of next generation nanoscale devices. Here, we investigate the drain current (Ids)-gate voltage (Vgs) characteristics of GaN nanowire wrap-gate transistors (WGTs) for various gate potentials in the wide temperature range of 130-310 K. An anomalous reduction in the experimental barrier height and rise in the ideality factor with reducing the temperature have been perceived. It is noteworthy that the variations in barrier height and ideality factor are attributed to the spatial barrier inhomogeneities at the AlGaN/GaN interface in the GaN nanowire WGTs by assuming a double Gaussian distribution of barrier heights at 310-190 K (distribution 1) and 190-130 K (distribution 2). The standard deviation for distribution 2 is lower than that of distribution 1, which suggests that distribution 2 reflects more homogeneity at the AlGaN/GaN interface in the transistor's source/drain regions than distribution 1.

Hysteresis-free high mobility graphene encapsulated in tungsten disulfide

High mobility is a crucial requirement for a large variety of electronic device applications. The state of the art for high-quality graphene devices is based on heterostructures made with graphene encapsulated in >40 nm-thick flakes of hexagonal boron nitride (hBN). Unfortunately, scaling up multilayer hBN while precisely controlling the number of layers remains an outstanding challenge, resulting in a rough material unable to enhance the mobility of graphene. This leads to the pursuit of alternative, scalable materials, which can be used as substrates and encapsulants for graphene. Tungsten disulfide (WS2) is a transition metal dichalcogenide, which was grown in large (∼mm-size) multi-layers by chemical vapor deposition. However, the resistance vs gate voltage characteristics when gating graphene through WS2 exhibit largely hysteretic shifts of the charge neutrality point on the order of Δn∼ 3 × 1011 cm−2, hindering the use of WS2 as a reliable encapsulant. The hysteresis originates due to the charge traps from sulfur vacancies present in WS2. In this work, we report the use of WS2 as a substrate and overcome the hysteresis issues by chemically treating WS2 with a super-acid, which passivates these vacancies and strips the surface from contaminants. The hysteresis is significantly reduced by about two orders of magnitude, down to values as low as Δn∼ 2 × 109 cm−2, while the room-temperature mobility of WS2-encapsulated graphene is as high as ∼62 × 103 cm2 V−1 s−1 at a carrier density of n ∼ 1 ×1012 cm−2. Our results promote WS2 as a valid alternative to hBN as an encapsulant for high-performance graphene devices.

Highly Tunable Negative Differential Resistance Device Based on Insulator-to-Metal Phase Transition of Vanadium Dioxide.

Negative differential resistance (NDR) based on the band-to-band tunneling (BTBT) mechanism has recently shown great potential in improving the performance of various electronic devices. However, the applicability of conventional BTBT-based NDR devices is restricted by their insufficient performance due to the limitations of the NDR mechanism. In this study, we develop an insulator-to-metal phase transition (IMT)-based NDR device that exploits the abrupt resistive switching of vanadium dioxide (VO2) to achieve a high peak-to-valley current ratio (PVCR) and peak current density (Jpeak) as well as controllable peak and valley voltages (Vpeak/valley). When a phase transition is induced in VO2, the effective voltage bias on the two-dimensional channel is decreased by the reduction in the VO2 resistance. Accordingly, the effective voltage adjustment induced by the IMT results in an abrupt NDR. This NDR mechanism based on the abrupt IMT results in a maximum PVCR of 71.1 through its gate voltage and VO2 threshold voltage tunability characteristics. Moreover, Vpeak/valley is easily modulated by controlling the length of VO2. In addition, a maximum Jpeak of 1.6 × 106 A/m2 is achieved through light-tunable characteristics. The proposed IMT-based NDR device is expected to contribute to the development of various NDR devices for next-generation electronics.

Sub‐Band Filling and Hole Transport in Polythiophene‐Based Electrolyte‐Gated Transistors: Effect of Side‐Chain Length and Density

AbstractThe relationship between hole density and conductivity in electrochemically gated polythiophene films is examined. The films are integrated into electrolyte‐gated transistors (EGTs), so that hole accumulations can be electrochemically modulated up to ≈0.4 holes per thiophene ring (hpr). Polythiophenes include poly(3‐alkylthiophenes) (P3ATs) with four different side chain lengths – butyl (P3BT), hexyl (P3HT), octyl (P3OT), or decyl (P3DT) – and poly[2,5‐bis(3‐dodecylthiophen‐2‐yl)thieno[3,2‐b]thiophene] (PBTTT) and poly(3,3′′′‐didodecyl[2,2′:5′,2′′:5′′,2′′′‐quaterthiophene]‐5,5′′′‐diyl) (PQT). Analysis of the drain current – gate voltage (ID–VG) and gate current – gate voltage (IG–VG) characteristics of the EGTs reveals that all six polythiophene semiconductors exhibited reversible conductivity peaks at 0.12 – 0.15 hpr. Conductivity is suppressed beyond ≈0.4 hpr.The maximum carrier mobilities of the P3AT semiconductors increase, and hysteresis of the conductivity peaks decreases, with increasing alkyl side‐chain length. PBTTT and PQT with reduced side chain densities exhibit the largest hysteresis but have higher hole mobilities. The results suggest that at ≈0.4 hpr, a polaronic sub‐band is filled in all cases. Filling of the sub‐band correlates with a collapse in the hole mobility. The side‐chain dependence of the peak conductivity and hysteresis further suggests that Coulombic ion‐carrier interactions are important in these systems. Tailoring ion‐carrier correlations is likely important for further improvements in transport properties of electrochemically doped polythiophenes.

Gate-Bias-Induced Threshold Voltage Shifts in GaN FATFETs

The threshold voltage (V TH) stability in GaN fat field-effect transistors (FATFETs) with a large channel area of ∼6.2 × 104 μm2 was studied using drain current vs gate voltage (I D–V G) characteristics. Each measurement was found to positively shift the previous I D–V G curve, and V TH eventually saturated with increasing number of measurements. The saturated V TH was ∼0.8 V for measurements in which V G ranged from −10 to 25 V and was ∼8 V for measurements in which the V G ranged from −10 to 40 V. Moreover, the positive gate bias stress increased V TH to 12.3 V. These shifts of V TH can be explained by electron trapping; according to charge-pumping measurements, the traps cannot exist in the oxide or the oxide/p-GaN interface but can exist near the surface region in p-GaN layers in GaN FATFETs. Scanning transmission electron microscopy and electron energy-loss spectroscopy analyses revealed the presence of oxygen within several atomic layers of p-GaN from the oxide/p-GaN interface. This intermixed oxygen might be the origin of the n-type behavior of the p-GaN surface; furthermore, the oxygen is speculated to be related to the traps. Surprisingly, similar incorporated oxygen was observed even in the surface region of as-grown p-GaN layers.

Electrical Control of Uniformity in Quantum Dot Devices.

Highly uniform quantum systems are essential for the practical implementation of scalable quantum processors. While quantum dot spin qubits based on semiconductor technology are a promising platform for large-scale quantum computing, their small size makes them particularly sensitive to their local environment. Here, we present a method to electrically obtain a high degree of uniformity in the intrinsic potential landscape using hysteretic shifts of the gate voltage characteristics. We demonstrate the tuning of pinch-off voltages in quantum dot devices over hundreds of millivolts that then remain stable at least for hours. Applying our method, we homogenize the pinch-off voltages of the plunger gates in a linear array for four quantum dots, reducing the spread in pinch-off voltages by one order of magnitude. This work provides a new tool for the tuning of quantum dot devices and offers new perspectives for the implementation of scalable spin qubit arrays.

Combining Freestanding Ferroelectric Perovskite Oxides with Two-Dimensional Semiconductors for High Performance Transistors.

We demonstrate the fabrication of field-effect transistors based on single-layer MoS2 and a thin layer of BaTiO3 (BTO) dielectric, isolated from its parent epitaxial template substrate. Thin BTO provides an ultrahigh-κ gate dielectric effectively screening Coulomb scattering centers. These devices show mobilities substantially larger than those obtained with standard SiO2 dielectrics and comparable with values obtained with hexagonal boron nitride, a dielectric employed for fabrication of high-performance two-dimensional (2D) based devices. Moreover, the ferroelectric character of BTO induces a robust hysteresis of the current vs gate voltage characteristics, attributed to its polarization switching. This hysteresis is strongly suppressed when the device is warmed up above the tetragonal-to-cubic transition temperature of BTO that leads to a ferroelectric-to-paraelectric transition. This hysteretic behavior is attractive for applications in memory storage devices. Our results open the door to the integration of a large family of complex oxides exhibiting strongly correlated physics in 2D-based devices.

Tuning the Surface Molecular Charge of Organic Photoelectrochemical Transistors with Significantly Improved Signal Resolution: A General Strategy toward Sensitive Bioanalysis.

Nature makes use of molecular charges to operate specific biological synthesis and reactions. Targeting advanced opto-bioelectronic sensors, organic photoelectrochemical transistors (OPECTs), taking advantage of the light fuel substituting an external gate potential, is now debuting and expected to serve as a universal platform for studying the rich light-biomatter interplay for new bioanalytics. Given the ubiquity of charged biomolecules in nature, molecular charge manipulation should underpin a generic route for innovative OPECT regulation and operation, which nevertheless has remained unachieved. Herein, this work manifests the biological tuning of surface charge toward the OPECT biosensor, which was exemplified by a light-sensitive CdS quantum dot (QD) gate electrode interfaced by a smart DNA superstructure with adenosine triphosphate (ATP) responsiveness. Highly negative-charged supramolecular DNA concatemers were self-assembled via sequential hybridization, and the ATP-triggered disassembly of the DNA concatemers would cause a tandem change of the effective gate voltage and transfer characteristics with significantly improved resolution. The present opto-bioelectronic device translates the events of charged molecules into amplified electrical signals and outlines a generic format for the future exploitation of rich biological tunability and light-biomatter interplay for innovative bioanalytics and beyond.

Comparative Study of Double Gate and Silicon on Insulator MOSFET by Varying Device Parameters

A comparative study of the single gate MOSFET (SG MOSFET), double-gate MOSFET (DG MOSFET) and silicon-on-insulator MOSFET (SOI MOSFET) is done using MOSFET simulation tool. Device simulation is done by varying different physical parameters of the device structure such as oxide thickness, channel length, temperature and different gate electrodes. Contour plots of SOI and DG MOSFET for electron concentration and potential at initial and final bias are simulated. The drain current vs gate voltage (Id-Vg) characteristics performance simulations show that DG MOSFET is better than SOI MOSFET for different oxide thickness and channel length. It was further noticed that with an increase in the oxide thickness, drain current decreases for DG and SOI MOSFETs. When oxide thickness is reduced from 10 to 7 nm keeping all other parameters same, in DG MOSFET drain current increased by 49.49 % and in SOI MOSFET drain current increased by 66.6 %. When channel length is reduced from 80 to 75 nm in DG MOSFET drain current increased by 1.35 % and in SOI MOSFET drain current increased by 2 %. The performance simulations show that aluminium (Al) gate electrode is better than n+ poly silicon (Si) and tungsten (W) for every MOSFET devices. With respect to aluminium gate electrode in DG MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.89 and 30.5 %, respectively and in SOI MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.84 and 34.61 %, respectively.
 HIGHLIGHTS
 
 Comparative study of Double Gate and Silicon on Insulator MOSFET
 Simulation of DG and SOI MOSFET using MOSFET simulation tool on nanohub.org
 Performance analysis of DG and SOI MOSFET by varying different physical parameters like oxide thickness, channel length, temperature and gate electrodes
 Drain current vs gate voltage (Id-Vg) characteristics performance simulation of DG and SOI MOSFET
 Contour plot for electron concentration and potential
 
 GRAPHICAL ABSTRACT

Multi-level 2-bit/cell operation utilizing Hf-based metal/oxide/nitride/oxide/silicon nonvolatile memory with HfO2 and HfON tunneling layer

This paper investigated the multi-level 2-bit/cell operation utilizing a Hf-based metal/oxide/nitride/oxide/silicon (MONOS) nonvolatile memory (NVM) device with a HfO2 and HfON tunneling layer (TL). The 2-bit/cell operation is realized by utilizing the localized charge injection method. It was found that drain-current–gate-voltage (I D–V G) characteristics of the programmed states were affected by asymmetry localized in a trapped location along the channel direction. Moreover, the amount of localized trapped charge is strongly affected by drain-source voltage (V DS) in the case of HfON TL. HfON TL shows distinguishable separated all programmed states compared to HfO2 TL. Finally, it was found that all programmed states of HfO2 and HfON TL show similar characteristics according to the channel length and width (L/W) of 2–10/15–90 μm.

USING PERCOLATIVE CRYSTALLINE 0.3 CUO/PVDF NANOCOMPOSITE GATE DIELECTRIC FOR FABRICATING HIGH-EFFECT MOBILITY THIN FILM TRANSISTOR OPERATING AT LOW VOLTAGE

Thin-film transistor (TFT) with various layers of crystalline Poly-vinylidene fluoride (PVDF)/CuO percolative nanocomposites based on Anthracene as a gate dielectric insulator have been fabricated. A device with excellent electrical characteristics at low operating voltages (<1V) has been designed. Different layers (L) of the film were also prepared to achieve the best optimization of ideal gate insulator with various static dielectric constants (εr). Capacitance density, leakage current at 1V gate voltage and electrical characteristics of OFETs with a single and multi layer films have been investigated. This device was showed highest field effect mobility of 2.27 cm2/Vs, a threshold voltage of -1.6V, an exceptionally low sub threshold slope of 380 mV/decade and an on/off ratio of 106. Such a High-ε three layered (3L) PVDF/CuO gate dielectric appears to be highly promising candidates for organic non-volatile memory, sensor and field-effect transistors (FETs).

Accurate determination of threshold voltage shift during negative gate bias stress in 4H-SiC MOSFETs by fast on-the-fly method

The threshold voltage shift in NO-annealed 4H-SiC MOSFETs during negative gate bias stress was investigated with a fast on-the-fly method for p-channel devices while considering the stress–time dependence of the slope of the drain current–gate voltage characteristics. With the proposed method, the threshold voltage shift was accurately measured over a wide time range from hundreds of nanoseconds. The negative threshold voltage shift exhibited power-law time dependence at room temperature and logarithmic time dependence at 423 K, suggesting that interface trap generation is observable at room temperature and thermally-assisted hole trapping in SiO2 dominates at high temperatures.

Inversion channel MOSFET on heteroepitaxially grown free-standing diamond

We successfully fabricated the inversion-type p-channel metal–oxide–semiconductor field-effect transistor (MOSFET) on heteroepitaxially grown free-standing diamond using silicon-based substrates. The drain current–drain voltage (Ids–Vds) and drain current–gate voltage (Ids–Vgs) characteristics were examined. The maximum drain current density and the peak field effect mobility (μFE) were around 0.35 mA/mm and 2.7 cm2 V−1s−1, which were lower than our reported results of the homoepitaxial diamond MOSFETs fabricated on high-pressure, high-temperature (HPHT) substrates. The interface state density (Dit) extracted from the subthreshold region was around 5.5 × 1012 cm−2eV−1, comparable to our reported results of the homoepitaxial diamond MOSFET. To further examine the reason for the low μFE, atomic force microscopy (AFM) measurements were performed for the n-type body of the heteroepitaxial diamond MOSFET, and we found that the surface roughness was much larger than our reported ones of the homoepitaxial diamond MOSFET. It can be deduced that the surface roughness would be one main limiting factor for the field effect mobility of the heteroepitaxial diamond MOSFET. The imperfect diamond heteroepitaxy would also degrade the field effect mobility. This work explores the potential of the inversion-type p-channel heteroepitaxial diamond MOSFETs, which would facilitate the practical application of diamond power devices.

Structural and electrical properties of Al/BiFeO3/ZrO2/n-Si structure for non-volatile memory application

In this communication, the structural and electrical properties of metal–ferroelectric–insulator–silicon (MFIS) capacitor structure have been reported for non-volatile memory applications. Sol–gel with spin coating and rf sputtering process have been used for depositing BiFeO3 (BFO) and ZrO2 films, respectively. It has been observed that BFO film shows pure ferroelectric phase, uniform grain size and maximum refractive index at annealing temperature of 500 °C. Thermo-gravimetric analyzer and differential scanning calorimetry analysis indicate good agreement with X-ray diffraction of BFO film. In ZrO2 thin film, it has been observed that ZrO2 is in amorphous state at all annealing temperatures and the maximum refractive index has been found at annealing temperature of 400 °C. Al/ZrO2/n-Si (MIS), Al/BiFeO3/n-Si (MFS) and Al/BiFeO3/ZrO2/n-Si (MFIS) structures have been fabricated to investigate the electrical characteristics. The memory window has been observed by capacitance–voltage (C–V) characteristics and it improves from 1.9 V in MFS structure to 5.4 V in MFIS structure with 8 nm dielectric layer. Leakage current density has been observed by current density–gate voltage (J–V) characteristics and it is order of 10−5 A/cm2 in MF150 nmI8 nmS structure. No charge value degrades up to 1012 iteration cycles in MF150 nmI8 nmS structure.

Demonstration of Tunneling Field-Effect Transistor Ternary Inverter

We demonstrate tunnel FET (TFET)-based ternary CMOS (T-CMOS) which can operate at supplyvoltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) <; 0.6 V. The TFET T-CMOS consists of the vertical n/p TFETs and their drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> )-gate voltage(V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) characteristics have sub-60 mV/dec steep subthreshold swing (SS) and hump as the gate and source are overlapped. To verify the formation mechanism of the third output voltage state (V3rd) in the TFET T-CMOS, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> s are analyzed with respect to various drain voltages (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ). As a result, it is revealed that I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> s of the n/p TFETs can have the wider flat ON-current regions at smaller V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> by drain-side channel inversion and stable V3rd can be formed through the voltage dividing between them. Furthermore, it is found that the hump plays a role to make the steeper output voltage transitions by increasing the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> difference between the n/p TFETs.

(Invited) Junctionless Device Cross-Section: A Key Aspect for Overcoming Boltzmann Tyranny

The demonstration of higher impact generate rate at relatively lower applied biases in a junctionless transistor (JLT) [1-2] has renewed interest in its device physics, operation and technology downscaling. This phenomenon is particularly interesting as it can lead to an associated steep current switching from off-to-on state with a subthreshold swing lower than 60 mV/decade [3-4]. A 3dimensional tri-gate JLT while offering immunity from short channel effects due increased gate controllability offers an additional degree of freedom apart from gate length and drain bias to tune the impact generation rate. Since JLT is a heavily doped device (figure 1(a)), the cross-section governs the concentration of carriers in the channel available for impact ionization and steep switching. Hence, the cross-section of a 3d JLT is expected to serve as a key facilitator for steep switching.Figure 1(b) shows the comparison of the 3d simulations exhibiting a sharp increase in current in a JLT with the available experimental data [1]. The default models of TCAD simulation tool [5] were calibrated to ensure a reasonable agreement with published results. Figure 1(c) shows the drain current (I ds) – gate voltage (V gs) characteristics of JLT for two different device cross-sections. The lower aspect ratio (AR = 0.2) JLT exhibits a lower subthreshold swing (SS) of 3 mV/decade while a JLT with AR of 1 showcases a conventional SS of 60 mV/decade. As shown in figure 1(d), results clearly indicate that device cross-section of a 3d JLT is crucial for overcoming the Boltzmann tyranny, and should be a crucial component for device design and operation. The research work demonstrates new possibilities through the optimization of 3d cross-section of a JLT for attaining a sharp enhancement of drain current at shorter gate lengths.

Subthreshold Characteristics of a Metal-Oxide–Semiconductor Field-Effect Transistor with External PVDF Gate Capacitance

An organic ferroelectric capacitor, using polyvinylidene difluoride (PVDF) as the dielectric, was fabricated. By connecting the PVDF capacitor in series to the gate of a commercially purchased metal-oxide–semiconductor field-effect transistor (MOSFET), drain current (ID)–drain voltage (VD) characteristics and drain current (ID)–gate voltage (VG) characteristics were measured. In addition, the subthreshold slopes of the MOSFET were determined from the ID–VG curves. It was found that the subthreshold slope could be effectively reduced by 23% of its original value when the PVDF capacitor was added to the gate of the MOSFET.

Inversion channel mobility and interface state density of diamond MOSFET using N-type body with various phosphorus concentrations

We investigated the phosphorus concentration (NP) dependence of the field-effect mobility μFE and interface state density Dit in inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs). The inversion channel diamond MOSFETs are potentially applicable in high-frequency, high-current, and high-voltage devices because of the material's excellent properties such as a wide bandgap, high breakdown electric field, high carrier mobility, and high thermal conductivity. However, the influences of device design parameters, such as NP in an n-type body and the oxide layer material, on the electrical characteristics of inversion channel diamond MOSFETs have not yet been reported. In this study, we fabricated inversion channel diamond MOSFETs using n-type bodies with various NP values. For decreased NP in the n-type body, μFE was increased, while Dit was decreased. Using the n-type body with the lowest NP of 2 × 1015 cm−3, the maximum μFE of 20 cm2/V·s and the minimum Dit of 1 × 1013 cm−2·eV−1 were obtained. In addition, an inverse correlation was found between μFE and Dit. Specifically, in the low-gate-voltage region of the drain current–gate voltage characteristics, μFE and Dit were strongly inversely correlated. The high Dit suggests that most holes are trapped in the interface state as strong scattering factors in the low-gate-voltage region. Lower Dit values are therefore important for obtaining higher μFE values, the same as in Si and SiC.

Highly Sensitive Detection of Protein Biomarkers Using Graphene Field-Effect Transistor Integrated with a Microfluidic Platform

In this work, we present a highly sensitive biosensing platform for the detection of protein biomarkers by utilizing aptamer-modified graphene field-effect transistors (GFETs) contained within a microfluidic chip. We have chosen thrombin as a model biomarker and its corresponding DNA-based aptamer as a target receptor which is anchored to the graphene surface to modulate the drain current of the GFET. The proposed biosensing platform has the potential to be used in early-stage disease diagnosis and in applications related to lab-on-a-chip-based health monitoring technology. Aptamer-based biosensing offers many advantages including low-cost, chemical and thermal stability, mass producibility, long shelf-life and reusability. Among different target analytes, protein biomarker detection is critical in early screening and diagnostics of diseases. Thrombin is an important protein biomarker which is produced by the body and plays a significant role in blood clotting or coagulation process or regulation of tumor growth [1]. Therefore, detection of thrombin is key to monitoring a number of cardiovascular diseases. Graphene-based FET (GFET) has become a highly promising candidate as next-generation biosensors due to the various inherent advantages it offers such as facile integration with the existing planar technology due to its 2-dimensional structure, label-free sensing, and high sensitivity. However, one of the major challenges with GFET-based biosensing is the lack of reproducibility due to each graphene layer having different physical dimensions and therefore electronic properties. Moreover, since GFET is highly sensitive to the charge disturbances at the FET channel, the sample liquid that is in contact with the graphene surface must be controlled. Therefore, integration of GFET biosensor with a microfluidic device is expected to enhance the sensing performances in terms of sensitivity and reproducibility. In this work, we have implemented a microfluidic chip integrated with GFET device to build a miniaturized platform for aptamer-based detection of a protein biomarker. The GFET devices were fabricated by transferring CVD (chemical vapor deposition) grown graphene onto the microfabricated gold electrodes on the Si/SiO2substrate where the electrodes form the source and the drainas schematically depicted in Figure 1. The FET devices were then sealed with a PDMS block containing a microfluidic channel as shown in Figure 2. The graphene channel was then functionalized with amine reactive 1-pyrene butyric acid N-hydroxysuccinimide ester (PBASE) by delivering the PBASE dissolved in dimethyl formamide through the microfluidic channel. The PBASE was immobilized on graphene surface via the π-π stacking interaction between graphene and the pyrene group of PBASE. The graphene channel was then further functionalized with the aptamers by flowing the amine terminated thrombin-binding aptamer solution through the microfluidic chip. The aptamers were crosslinked with the PBASE on graphene surface via the covalent linkage between the amine-reactive succinimide group of PBASE and the amine group of the aptamers [2]. For the biomarker detection, various concentrations of thrombin solutions were introduced to the GFET device through the microfluidic flow system. For a given concentration of thrombin, the drain current (IDS) vs. gate voltage (VGS) characteristics were measured in order to observe the shift in the Dirac voltage (VDirac). Figure 3 shows the Raman spectra of graphene on Si/SiO2 substrate before and after PBASE functionalization. The additional peak at 1618 cm-1 in Figure 3(a) represents the pyrene group resonance peak due to π – π stacking interaction [3] between the aromatic pyrenyl group of PBASE and the basal plane of graphene, confirming the immobilization of PBASE on graphene. Figure 4 shows the UV-vis spectra of the device sample before and after the aptamer immobilization. The peak at 260 nm indicates the presence of aptamers on the device surface. The resulting measurements are presented in Figure 5. It can be seen that introduction of thrombin causes the Dirac voltage to shift to the right suggesting p-doping of the graphene surface [4]. This is consistent with the cationic nature of thrombin at neutral pH. The corresponding calibration curve is shown in Figure 6. The sensor shows a linear behavior over a wide range of concentrations from 1 nM to 1µM.

Frequency multiplier based on back-gated graphene FETs with M-shaped resistance characteristics

The ambipolar graphene field-effect transistors (GFETs) usually exhibit Λ-shaped resistance versus gate voltage characteristics (R-Vg curve) with the n- and p-type regions switching at the neutrality points of graphene. However, M-shaped R-Vg curves were frequently observed in our back-gated GFETs without intentional doping. Here, we proposed an implementation of a frequency multiplier using the M-like shape of the R-Vg curve. We first investigated the effect of the channel length and the contact transfer length in a GFET on the shape of the R-Vg curve and then evaluated the influence of the various shapes of R-Vg curves on the performance of the frequency multiplier (including tripler and quadrupler). Finally, a frequency tripler based on a single GFET has been experimentally demonstrated. When applying a sinusoid input signal with a fundamental frequency at a suitable operation area, around 80% output signal power is concentrated at the third harmonic. The excellent output spectral purity makes GFETs with the M-shaped R-Vg curve promising candidates for the frequency multiplier.