Demonstration of Tunneling Field-Effect Transistor Ternary Inverter

Abstract

We demonstrate tunnel FET (TFET)-based ternary CMOS (T-CMOS) which can operate at supplyvoltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) <; 0.6 V. The TFET T-CMOS consists of the vertical n/p TFETs and their drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> )-gate voltage(V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) characteristics have sub-60 mV/dec steep subthreshold swing (SS) and hump as the gate and source are overlapped. To verify the formation mechanism of the third output voltage state (V3rd) in the TFET T-CMOS, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> s are analyzed with respect to various drain voltages (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ). As a result, it is revealed that I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> s of the n/p TFETs can have the wider flat ON-current regions at smaller V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> by drain-side channel inversion and stable V3rd can be formed through the voltage dividing between them. Furthermore, it is found that the hump plays a role to make the steeper output voltage transitions by increasing the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> difference between the n/p TFETs.