Gate Tunneling Leakage Current Research Articles

Performance Analysis of InAs/AlSb MOS-HEMT by Self-Consistent Capacitance-Voltage Characterization and Direct Tunneling Gate Leakage Current

In this paper, Capacitance-Voltage (CV) characteristics and direct tunneling gate leakage performance of InAs/AlSb Metal Oxide Semiconductor High Electron Mobility Transistor (MOS-HEMT) are investigated. 1-D coupled Schrӧdinger-Poisson equations are solved for electrostatic characterization of InAs/AlSb MOS-HEMT considering wave function penetration and strain effects. Using modified Wentzel–Kramers–Brillouin (WKB) method for transmission probability, direct tunneling gate leakage current is also calculated for the MOS-HEMT structure. Dependence of CV characteristics and direct tunneling gate leakage current on some important process and physical parameters such as oxide thickness, channel thickness, capping layer composition, gate dielectric material, doping concentration of delta layer and temperature are studied in this work. Our simulation results agree the pattern of variation with the experimental results reported by H. K. Lin et al.

Performance Analysis of InAs/AlSb MOS-HEMT by Self-Consistent Capacitance-Voltage Characterization and Direct Tunneling Gate Leakage Current

Recently, III-V materials have attracted great interest among researchers in exploring the substitution of the Si channel in scaled logic field-effect transistors [1]. To enhance mobility and speed, High Electron Mobility Transistors (HEMTs) are being experimented with III-V materials. As a result, different material systems for HEMTs are appearing. InAs/AlSb HEMTs have appeared as a promising device as it has electron mobility as high as 30000 cm2/Vs, fT and fMAX exceeding 230 GHz [2]. However, technological limitations are the low breakdown voltage associated with the narrow bandgap of the InAs channel and additional gate leakage current due to staggered band alignment at the InAs/AlSb heterojunction. Recently high breakdown field of 5MV/cm and reduced gate leakage current of e-beam evaporated Al2O3on top of conventional InAs/AlSb HEMT structure has been reported experimentally by H. K. Lin et al [3]. But a complete self-consistent study and gate leakage current analysis of this device are yet to be done. In this work, we have performed a complete study of Capacitance-Voltage (CV) characteristics and Direct Tunneling (DT) gate leakage current using self-consistent Schrӧdinger-Poisson method in InAs/AlSb Metal-Oxide-Semiconductor HEMT (MOS-HEMT) by varying different process parameters as well as physical parameters like oxide thickness, channel thickness, capping layer composition, dielectric variation, delta doping concentration and temperature. We have investigated CV characteristics and DT gate leakage performance of the structure shown in figure 1 [3] by self-consistent simulation of 1-D coupled Schrӧdinger and Poisson equation [4]. We have used finite difference method for solving Poisson equation [5] and hamiltonian matrix formalism [6] for solving Schrӧdinger equation numerically. Strain effect is also incorporated in this simulator [7]. DT gate leakage current is obtained using the method where transmission probability is calculated using modified Wentzel–Kramers–Brillouin (WKB) method [8]. In our work, we have calculated transmission probability using transmission line analogy [9]. The conduction band diagram and carrier profile of the device obtained from the simulation are illustrated in figure 2. Figure 3 shows the CV characteristics for different channel thicknesses. There are two cross-over points in the curve which can be justified by the change of slope of sheet carried density with respect to the gate voltage. The gate leakage current decreases with channel thicknesses and this variation is shown in figure 4. This behavior can be explained by the upshift of eigen energies in the well as channel thickness is decreased which further causes reduction of transmission probability. CV characteristics are not affected by the change in dielectric material having same Equivalent Oxide Thickness (EOT) as shown in figure 5. However, gate leakage current is significantly reduced with the replacement of high-k HfO2 in place of Al2O3shown in figure 6. This can be justified by the fact that channel sheet carrier density remains same with the variation whereas gate leakage reduces due the reduction in transmission probability with the replacement of high-k dielectric. We have investigated CV characteristics and DT gate leakage current with self-consistent method for InAs/AlSb MOS-HEMT. We have observed that gate leakage current can be significantly reduced by using high-k dielectrics or thick channel layer. Our simulation work provides consistent trends of variations with the experiments [3] and shows how the performance of InAs/AlSb MOS-HEMT can be improved by varying appropriate physical/process parameters.

Gate leakage current partitioning in nanoscale double gate MOSFETs, using compact analytical model

This paper presents a compact gate leakage current partitioning model for nanoscale Double Gate (DG) MOSFETs, using analytical models of the direct tunneling gate leakage current. Gate leakage current becomes important and an essential aspect of MOSFET modeling as the gate oxide thickness is scaled down to 1nm and below in advanced CMOS processes. We considered an ideal interface (ideal case without an interfacial layer) and two layers high k dielectric materials as gate insulators. In the case of two layers, a thin layer of SiO2 as an interfacial layer is considered. The results of the gate current partitioning components into drain and source show good agreement with 2D TCAD numerical device simulation (Silvaco Atlas).

MODELING GATE CURRENT FOR NANO SCALE MOSFET WITH DIFFERENT GATE SPACER

Dimensions of metal–oxide–semiconductor field effect transistor (MOSFET) have been scaled down for decades to maintain the performance. So, as a result of aggressive scaling, gate oxide thickness approaches its manufacturing and physically limiting value of less than 2 nm in nano regime. Under such circumstances, gate leakage (tunneling) current has become a critical problem in nano domain as compared to subthreshold leakage current. Consequently, accurate quantitative understanding of gate tunneling leakage current is very important especially in context of low power VLSI application. In this work, gate tunneling currents have been modeled including the inevitable nano scale effects for a MOSFET having different high-k dielectric spacer such as SiO2 , Si3N4 , Al2O3 , HfO2 . The gate current model is compared and contrasted with santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed that neglecting nano scale effects may lead to large error in the calculated gate current. It is found in the results that gate leakage current decreases with the increase of dielectric constant of the gate spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering, and subthreshold slope of the device.

Modeling and Simulation of High-κ Gate GaSb Nanowire Field Effect Transistor for Ultra High Speed and Low Power Applications

In this work, we have presented a numerical model for calculating drain current, gate capacitance, gate leakage current and several other important metrics of GaSb nanowire field effect transistor (NWFET). A 2-D simulator is used to calculate gate capacitance, surface potential, charge profile and direct tunneling gate leakage current under different gate biases. Drain current is simulated using a 3-D simulator based on mode-space approach. Dependence of drain current on several device parameters like film thickness, gate length and source/drain Fermi level is also investigated. Gate delay, power-delay and energy-delay products are calculated to show these devices' applicability in ultra high speed and low power applications. To investigate the effects of using ternary alloys of GaSb and InSb, the same metrics are also calculated for GaxIn1-xSb NWFET.

Gate tunneling current predicting model of strained Si for scaled metal-oxide semiconductor field effect transistor

For scaled metal-oxide semiconductor field effect transistor (MOSFET) devices, normal operation is seriously affected by the static gate tunneling leakage current due to the ultra-thin gate oxide of MOSFET, and the novel MOSFET devices based on strained Si are similar to bulk Si devices in the effects. To illustrate the impact of gate leakage current on performance of novel strained Si device, a theoretical gate tunneling current predicting model by integral approach following the analysis of quasi-two-dimensional surface potential is presented in this study. On the basis of theoretical model, performance of MOSFET device was quantitatively studied in detail using ISE simulator, including different gate voltages and gate oxide thickness. The experiments show that simulation results agree well with theoretical analysis, and the theory and experimental data will contribute to future VLSI circuit design.

Leakage Minimization of SRAM Cells in a Dual-$V_t$ and Dual-$T_{\rm ox}$ Technology

Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicrometer regime. As a result, reducing the subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> and dual- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> assignment to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different configurations of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. The leakage saving achieved by using this technique is a function of the values of the high threshold voltage and the oxide thickness, as well as the number of rows and columns in the cell array. Simulation results with a 65-nm process demonstrate that this technique can reduce the total leakage power dissipation of a 64 times 512 SRAM array by 33% and that of a 32 times 512 SRAM array by 40%.

Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies

The asymmetric source/drain extension (ASDE) transistor can be a suitable option because of improved short channel effects in technology nodes beyond 32 nm. In this paper, we have analyzed the impact of asymmetric drain extension reduction on the device metrics, namely, gate-to-drain capacitance, drain current, subthreshold leakage, and gate tunneling leakage current. Also, analytical models have been developed to model the effect of the ASDE devices. Based on our proposed analytical model, SPICE-compatible transistor models have been developed to include the ASDE device structure as possible design options. With our SPICE-compatible transistor models, large-scale circuit simulation can be performed to evaluate the benefits and the overheads associated with the ASDE devices. It is observed from circuit simulations that there is an optimal drain extension length which is different from the source extension length. With the ASDE devices, the circuit power delay product can effectively be reduced by almost 35% with respect to the conventional symmetric devices.

Analysis of Scaling Strategies for Sub-30 nm Double-Gate SOI N-MOSFETs

State-of-the-art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the ultrathin silicon body (UTB) double-gate (DG) MOSFET and considering the main figures of merit (FOM) for the high-performance N-MOS transistor. The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short-channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field. As a consequence, the impact of surface roughness at the Si-oxide interface and the gate tunneling leakage current are substantially reduced compared to the case of highly doped bulk MOSFETs. According to our results, thanks to the suppression of gate leakage current, scaling of the UTB-DG MOSFET down to the 32 nm technology node appears possible adopting -based gate dielectrics. In spite of the improved mobility at given inversion charge density, the simulated on-currents are substantially lower than those required by the 2005 ITRS for the 45 and 32 nm nodes . Nonetheless, thanks to relaxed scaling of the oxide thickness, hence to reduced gate capacitance, the requirements in terms of intrinsic delay and power-delay product can be satisfied. The issue of variability is analyzed by evaluating the dependence of the key FOM on the variation of critical dimensions such as the thickness of the gate oxide and of the silicon layer.

Effect of gate-drain/source overlap on the noise in 90nm N-channel metal oxide semiconductor field effect transistors

In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10nm is recommended for the 90nm gate length transistors, in order to get the best performance in radio frequency applications.

Composition and Growth Kinetics of the Interfacial Layer for MOCVD HfO2 Layers on Si Substrates

To boost MOS transistor performance, thickness of the gate dielectric is continuously scaled down. This results in an increase of gate tunneling leakage current, which at some point prevents further downscaling. Desired parameters of alternative materials to are a higher dielectric constant (high-k materials), stability, and compatibility with silicon. A general observation for one of the prime candidates, is formation of an interfacial layer between the silicon and the high-k material that limits scalability because of its low k-value. Hence, a thorough study of the formation of this layer and its contribution to the equivalent oxide thickness is of utmost importance. We studied the composition and growth kinetics of the interfacial layer formed during the deposition of by metallorganic chemical vapor deposition using and tetrakis-diethylamidohafnium as precursor. We found the composition and thickness of the interfacial layer to be dependent on the deposition parameters as well as on the starting surface. The layer’s composition is hafnium silicate-like and its thickness increases as a function of deposition time and temperature. It is therefore controlled by deposition of the layer. © 2004 The Electrochemical Society. All rights reserved.

An effective model for analysing tunneling gate leakage currents through ultrathin oxides and high- k gate stacks from Si inversion layers

In this paper, a model for describing tunneling from Si inversion layers is discussed. The model accounts for the quantization effects at the silicon/dielectric interface and is able to closely follow the self-consistent calculation of the potential and inversion charge in an inverted MOS structure. It is also applicable to multilayer gate stacks, since a general procedure is used for calculating the transmission through dielectric stacks. Influence of both material and geometrical parameters of a dual layer stack are discussed and scaling projections are inferred.

Scaling effects on gate leakage current

Scaling effects on direct tunneling gate leakage current are analyzed by utilizing new models implemented to perform self-consistent calculation between the direct tunneling, the band-gap narrowing (BGN) and the incomplete impurity ionization. This calculation is indispensable for reproducing the measured gate current-gate voltage characteristics in the device simulation. As a result, it is concluded that the scaling of the gate width cannot suppress the gate leak, even if the specification of the threshold voltage is relaxed in order to shrink the gate width. It is also found that the scaling of the gate length cannot suppress the gate leak unless the vertical field is strong.

Comprehensive noise performance of ultrathin oxide MOSFETs at low frequencies

An analytical model and analysis of the low frequency noise performance of ultrathin oxide MOSFETs are presented. The model includes the effects of gate tunneling leakage current, low frequency noise sources, and their cross correlation coefficient between the input and the output. The correlation coefficient is not negligible in the existence of direct tunneling current through the gate oxide, and has an impact on the overall noise performance at low frequencies. Based on the partition noise theory and BSIM4 gate leakage current model with the source–drain partition, the correlation coefficient is obtained from a physical and rigorous modeling of intrinsic noise sources. The calculated results are compared with correlation noise measurements and good agreement is observed. An analytical formulation of low frequency noise performance is newly derived using the frequency-dependent noise parameters P LF, R LF, and C LF. The noise performance parameters, such as minimum noise figure, optimum source resistance and reactance, are graphically presented to accurately predict the influence of the gate leakage current on the low frequency noise performance. From quantitative results simulated with typical device parameters, it is shown that the proposed model can be used for optimum design of ultrathin oxide MOS devices and circuits at low frequencies.

Study on Nano Complementary Metal Oxide Semiconductor Gate Leakage Current

This work examines different components of the leakage current in scaled N and P-metal oxide semiconductor field-effect transistor (MOSFET) with ultra thin gate oxide. Experimental results show that the gate tunneling leakage current through the source/drain extension region (also named edge direct tunneling, EDT) is the largest component, which dominates the maximum off-state power consumption of a nano-scaled transistor. To clarify the relationship between this largest leakage component and the size of the source/drain to gate overlap region, the proposed capacitance–ratio method (C–R method) was used to precisely extract the dimensions of the source/drain to gate overlap, Lov. To reduce the gate-tunneling leakage at the source/drain edge, a modified gate dielectric structure is proposed and verified in this work.

0.15 μm gate-length AlGaN/GaN HEMTs with varying gate recess length

The effect of gate-recess length on DC and RF performance of AlGaN/GaN gate-recessed high electron mobility transistors (HEMTs) was studied. 0.15 μm gate-length AlGaN/GaN HEMTs with varying gate-recess length from 0.5 to 1.0 μm were fabricated. DC and microwave performance did not exhibit significant dependence on the gate-recess length. The devices showed a maximum drain current density as high as 1.1 A/mm, a unity gain cutoff frequency of 79 GHz, and a maximum frequency of oscillation of 125 GHz. The measured series source resistances were essentially identical for all devices. Therefore, all the gate-recessed HEMTs exhibited similar DC and RF performance. This conclusion is derived from the fact that the values of ohmic contact resistances dominated over the values of channel resistances. The nature of the breakdown in the HEMTs was also studied. The results of temperature-dependent breakdown voltage measurements suggest that the breakdown mechanism was mainly due to tunneling gate leakage currents via shallow traps.

Ultra-thin silicon nitride by hot wire chemical vapor deposition (HWCVD) for deep sub-micron CMOS technologies

Silicon nitride is considered a promising candidate to replace thermal oxide dielectrics, as the latter is reaching its scaling limits due to the excessive increase in the gate tunneling leakage current. The novel hot wire chemical vapor deposition (HWCVD) technique shows promise for gate quality silicon nitride film yields at 250 °C while maintaining their primary advantage of a higher dielectric constant of 7.1. In this paper we report the results of our efforts towards developing ultra-thin HWCVD silicon nitride as an advanced gate dielectric for the replacement of thermal gate oxides in future generations of ultra large scale integration (ULSI) devices.

Effects of incomplete ionization of impurities in poly-Si gate and band gap narrowing on direct tunneling gate leakage current

In this article the ionization rate of phosphorus doped in poly-Si gate and band gap narrowing caused by carrier–carrier interactions and carrier–ion interactions are self-consistently calculated by using a simple algorithm that is formulated phenomenologically. As a result, the ionization rate is found to be unity when the phosphorus concentration is less than 3×1019 cm−3, and becomes lower rapidly with the increase of the concentration larger than 3×1019 cm−3. Using this result, in a wide oxide voltage region, we can reproduce the oxide voltage dependence of the measured tunneling current from the gate in various samples (tOX=2.1, 2.8, and 3.4 nm) with the same tunneling mass (mOX=0.42m0), where m0 is the free electron mass. In particular, we show why the incomplete ionization can reproduce the tunneling current from the gate even in a lower oxide voltage region where the complete ionization cannot do so. Furthermore, a local band gap narrowing, which is described by an additional band gap narrowing due to exchange–correlation interactions of carriers induced by a local potential, is included in the present calculation.