Gate Tunneling Current Research Articles

Two-dimensional quantum mechanical modeling of nanotransistors

Quantization in the inversion layer and phase coherent transport are anticipated to have significant impact on device performance in “ballistic” nanoscale transistors. While the role of some quantum effects have been analyzed qualitatively using simple one-dimensional ballistic models, two-dimensional (2D) quantum mechanical simulation is important for quantitative results. In this paper, we present a framework for 2D quantum mechanical simulation of a nanotransistor/metal oxide field effect transistor. This framework consists of the nonequilibrium Green’s function equations solved self-consistently with Poisson’s equation. Solution of this set of equations is computationally intensive. An efficient algorithm to calculate the quantum mechanical 2D electron density has been developed. The method presented is comprehensive in that treatment includes the three open boundary conditions, where the narrow channel region opens into physically broad source, drain and gate regions. Results are presented for (i) drain current vs drain and gate voltages, (ii) comparison to results from Medici, and (iii) gate tunneling current, using 2D potential profiles. Methods to reduce the gate leakage current are also discussed based on simulation results.

Two silicon nitride technologies for post-SiO2 MOSFET gate dielectric

P-MOSFETs with 14 /spl Aring/ equivalent oxide thickness (EOT) were fabricated using both JVD Si/sub 3/N/sub 4/ and RTCVD Si/sub 3/N/sub 4//SiO/sub x/N/sub y/ gate dielectric technologies. With gate length down to 80 nm, the two technologies produced very similar device performances, such as drive current and gate tunneling current. The low gate leakage current, good device characteristics and compatibility with conventional CMOS processing technology make both nitride gate dielectrics attractive candidates for post-SiO/sub 2/ scaling. The fact that two significantly different technologies produced identical results suggests that the process window should be quite large.

Semiclassical and wave mechanical modeling of charge control and direct tunneling leakage in MOS and H-MOS devices with ultra-thin oxides

Charge control and gate leakage in metal-oxide-semiconductor (MOS) structures and heterojunction-MOS structures with ultrathin oxide (1 nm) are investigated using both classical and wave-mechanical calculations. In the classical approach, direct tunneling gate current is determined using the formalism of transmission probability whereas the notion of quasibound state lifetime is applied in the wave mechanical model. For conventional MOS structure, the threshold voltage V/sub T/ significantly depends on the applied model but an excellent agreement between both approaches is found about gate leakage provided that the correction of V/sub T/ is taken into account. For buried-channel H-MOS structures the quantum-induced V/sub T/-shift is smaller but the degradation of gate control efficiency dn/sub s//dV/sub g/ is increased, due to a large charge displacement from the oxide interface resulting from 2-D confinement in the buried strained layer. Using semiclassical approach the error of inversion charge distribution yields an overestimation of gate leakage compared with the more rigorous wave-mechanical calculation. It is finally shown by properly solving self-consistently Poisson and Schrodinger equations that a heterojunction-channel architecture may reduce the gate leakage by at least two orders of magnitude compared with conventional MOS design. This improvement would be in addition to the expected increase of device performance due to the strain-induced enhancement of electron transport properties.

Gate tunneling currents in ultrathin oxide metal–oxide–silicon transistors

Carrier tunneling through ultrathin (1–3 nm) SiO2 layers in MOS (metal–oxide–silicon) structures is investigated using the Bardeen–Harrison transition probability method. Quantum mechanical wave function matching at the two abrupt potential boundaries of a trapezoidal Si/SiO2/Si barrier gives an electric-field dependent preexponential factor in the Wentzel–Kramers–Brillouin tunneling probability, which significantly affects the current–voltage characteristic at low fields. An analytical theory is employed to predict the relative importance of three elastic tunneling pathways (electrons, valence electrons, and holes) and two geometrical tunneling locations (channel region and source or drain overlap regions) in MOS transistors (MOSTs), showing (1) hole tunneling dominant in p+gate pMOST (p-channel MOST) at low gate voltages, and (2) overlap regions dominant prior to base-region inversion in both p+gate pMOST and n+gate nMOST (n-channel MOST). The analytic theory is used to analyze the experimental tunneling currents measured at the gate, source, well, and substrate terminals of sourced MOS capacitors to give the oxide thickness and impurity doping concentrations in the base and source regions.

A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs

This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.

On the calculation of gate tunneling currents in ultra-thin metal–insulator–semiconductor capacitors

The calculation of gate tunneling currents in metal–insulator–semiconductor structures with ultra-thin gate stacks directly relies on quantum mechanical principles. In this paper, it is illustrated that well-known techniques based on elementary quantum physics and statistical mechanics can successfully be applied to solve some conceptual problems encountered on calculating the gate current and the charge distribution.

Influence of defects on elastic gate tunneling currents through ultrathin SiO2gate oxides: predictions from microscopic models

We study theoretically the influence of neutral oxygen vacancies on the magnitude of elastic tunneling currents through the ultrathin (1.3 nm) gate oxide of a prototypical metal-oxide field-effect transistor with a channel length of 50 nm. For the calculation of the gate currents, we have used transmission coefficients obtained from three-dimensional semiempirical tight-binding calculations for a model Si–SiO2–Si junction, and electron distribution functions based on full-band Monte-Carlo transport simulations. The positions of the atoms in the junction were determined by first-principles density-functional calculations. It is found that the gate currents increase significantly (by typically one to three orders of magnitude) in the presence of vacancies having a density around 1012cm−2, provided that the resonant energy levels lie less than 1 eV above the Si conduction band edge.

Calculation of direct tunneling gate current through ultra-thin oxide and oxide/nitride stacks in MOSFETs and H-MOSFETs

This theoretical work investigates some aspects of direct tunneling gate current in ultra-thin gate MOSFET, as influence of bias, oxide thickness, and oxide thickness fluctuations. We study two alternative device architectures to reduce this effect. They consist in either increasing the insulator thickness using a high permittivity nitride/oxide stack or burying the channel, due to a tensile strained IV–IV heterostructure. The presented calculations have been performed by coupling a semi-classical approach of direct tunneling computation with the 2D Monte Carlo device simulation.

A comparative study of gate direct tunneling and drain leakage currents in n-MOSFET's with sub-2 nm gate oxides

This work examines different components of leakage current in scaled n-MOSFET's with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents.

Study of direct tunneling through ultrathin gate oxide of field effect transistors using Monte Carlo simulation

Direct tunneling gate currents of ultrathin gate oxide thickness metal oxide semiconductor field effect transistors (MOSFETs) are modeled in a two-step calculation procedure based on the treatment of physical microscopic data acquired during Monte Carlo device simulation. Gate currents are obtained by weighting the carrier perpendicular energy distribution at the Si/SiO2 and N+-poly–Si/SiO2 interfaces by the electron transmission probability, which is calculated by the one-dimensional Schrödinger equation resolution with the transfer-matrix method. The procedure is applied to a 0.07 μm gate length and 1.5 nm gate oxide thickness transistor, for which the gate and drain voltage influences on gate currents are studied by assuming at first a uniform gate oxide layer. It is shown that the maximum gate current is obtained for one of the two static points of complementary metal oxide semiconductor inverters: VGS=VDD and VDS=0, which raises a severe problem of standby power consumption. The contribution of hot carriers to the tunnel current is evaluated and is found to be small in case of such ultrathin oxide n-MOSFETs: contrary to thick (>5 nm) gate oxide transistors, the maximum gate current is not linked to the carrier energy peak in the channel but is located near the source well where the electron concentration is the largest. Oxide thickness fluctuations are then considered by meshing the oxide surface area and assuming a Gaussian law for the local oxide thickness deviation to the mean value. It is shown that a correct agreement is achieved with experimental published data when the oxide film nonuniformity is included in the calculation. Gate currents mapping for different bias conditions are given and analyzed, which show that very high current densities run through the oxide layer in the vicinity of weak points. An estimate of the surface through which flows the major part of the current is made, and a link between the highly nonuniform current leakage and the soft-breakdown mechanism of the oxide layer is proposed.

Comparison of Valence-Band Tunneling in Pure SiO2, Composite SiO2 /Ta2O5, and Pure Ta2O5, in Mosfets with 1.0 nm-Thick SiO2-Equivalent Gate Dielectrics

ABSTRACTThe gate tunneling current in ultrathin gate dielectric NMOSFETs with positive gate bias is due to the tunneling of electrons from the conduction and valence bands of the substrate. Valence-band electrons tunnel from the substrate of NMOS devices when the valence-band edge in the substrate rises above the conduction-band edge in the substrate. This paper reports experimental trends in the contribution of valence-band electrons tunneling to the gate current of NMOSFETs with gate oxides composed of pure SiO2. The large gate tunneling current can be reduced by replacing the conventional SiO2 gate dielectric with alternative dielectrics with larger dielectric constants. This paper reports the effect of replacing SiO2 with alternative dielectrics on the contribution of valence-band electron tunneling to the gate current. Simulations are carried out for composite SiO2/Ta2O5 gate dielectric structures.

Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the I/sub g/ versus V/sub g/ characteristics for the p/sup +//pMOSFET are essentially identical to those for the n/sup +//nMOSFET; however, when measured in inversion, the p/sup +//pMOSFET exhibits much lower gate current for the same |V/sub g/|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p/sup +//pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p/sup +/-polysilicon gate; and (3) conduction band electron tunneling from the p/sup +/-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p/sup +//pMOSFET, with one of them dominating in a certain voltage range.

Evaluation Of 2.0 nm Grown and Deposited Dielectrics in 0.1 μm PMOSFETs

ABSTRACTThe quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.

Impact of Tunnel Film Oxynitridation on Band-to-Band Tunneling Current and Electron Injection in Flash Memory

The impact of the use of oxynitride tunnel film on write, erase and read operations of flash memories was investigated. We found that during electron ejection from a floating gate into a drain, band-to-band tunneling currents of flash memory cells with tunnel films having a high degree of nitridation are two orders of magnitude smaller than that of flash memory cells with oxide tunnel films. Consequently, higher-nitridation tunnel films improve the endurance characteristics of flash memory. However, during electron injection from a channel into the floating gate, Fowler-Nordheim tunneling gate currents of flash memory cells with higher-nitridation tunnel films are two orders of magnitude smaller than that of flash memory cells with oxide tunnel films. Moreover, the threshold voltage of flash memory cells with oxynitride tunnel films is 0.24–0.48 V smaller than that of flash memory cells with oxide tunnel films in read operations. These results can be explained by the modification of the electric field under oxynitride tunnel films due to the formation of donor layers, which is induced by nitridation of tunnel oxide films.

A quantum gate current model

Gate current plays a critical role in the maximum gate voltage swing, the maximum transconductance, and as a direct consequence, the maximum noise margin of digital devices. A quantum gate current model based on a charge-control analysis and the WKB approximation is presented for heterostructure field effect transistors (HFETs). Both the tunneling and thermionic emission gate currents are included and treated in a unified way in this model. Along with the general model itself, a specific calculation on a semiconductor insulator semiconductor (SISFET) is presented. The model shows that for advanced HFETs with thin hetero-barrier layers, the tunneling component dominates over the thermionic component and essentially constitutes the gate current. >

Dc current-voltage characteristics of a double-quantum-well field-effect resonant tunneling transistor

We reported the observation of steplike drain current and the negative transconductance, in a field-effect transistor. Our transistor has a double-quantum-well channel, and the quantum well close to the surface is depleted. We demonstrate that the novel transistor characteristics are from tunneling of electrons in between two-dimensional quantum wells. The observed current-voltage characteristic in gate tunneling current has a large peak-to-valley ratio (380–1), which is close to an idealized delta functionlike behavior.

Resonant tunnelling gate field-effect transistor

A new negative differential resistance field-effect transistor concept, based on resonant tunnelling, is demonstrated. The gate of this novel device consists of an AlAs/GaAs double barrier. The drain current against drain and gate voltages exhibit a peak due to the quenching of the resonant tunneling gate current. Thus, in addition to negative conductance, this structure exhibits negative transconductance, a uniquie feature in an n-channel device.