Thick Gate Research Articles

Development of Vertical Structured TFT Using Interfacial Oxidation

As advancements in display technology persist, ongoing research endeavors into Thin-Film Transistors (TFTs) to move forwards display evolution endure. Among the various semiconductors in TFT technologies, oxide TFTs have garnered considerable attention due to their manifold advantages, including heightened electron mobility in comparison to a-Si, superior transmittance, and suitability for medium to large-scale applications.Recent developments in display engineering suggest that Augmented Reality (AR), Virtual Reality (VR), and flexible displays are the vanguards of next-generation displays. These rapidly expanding applications desire several specifications for TFTs, such as minimalized occupied area, high resolution, low-power operation, etc. Given the challenges associated with fulfilling these mentioned requirements using conventional TFT technologies is difficult due to the facing physical limitations. Therefore, a novel enhancement methodology becomes necessary. In response to this necessity, there has been a rapidly growing interest in Vertical TFTs (VTFTs), which represent a structural refinement of next-generation TFTs in recent years.VTFT was propounded by Professor Y. Uchida of Japan in 1984 utilizing a-Si [1]. In the V-TFT structure, the source and drain electrodes are vertically separated by an insulator spacer. The annel lies between them, attached to the spacer's sidewall, directing carrier flow vertically. Therefore, VTFTs can easily achieve short channel lengths under 1µm, larger aspect ratios W/L, and higher packaging density, greatly reducing the occupied area over conventional TFTs. Nevertheless, the development of previously proposed VTFTs facing into unresolved challenges, including process complexity attributable to the requisite spacers and interlayer dielectrics (ILDs), as well as reduced yields due to the process complexity.M. Chandra Sekhar et al., have postulated a methodology [2] employing the oxide layer formed at the interface as a leading layer during the deposition of metal and oxide, subsequently evaluating its reliability. This oxide film is termed Interfacial Oxidation.As illustrated in Figure 1, our study introduces a novel VTFT processing methodology assured to improve process complexity and low yield rates, which represent inherent challenges in conventional VTFT fabrication.Tantalum (Ta), characterized by low Gibbs's free energy, is harnessed as the gate electrode, while Indium Tin Oxide (ITO) serves as the source and drain electrodes. Concurrently, an interfacial oxide film occurs through the heat treatment-induced interfacial oxidation reaction between ITO and Ta, serving as an insulating film. This innovative VTFT processing protocol offers the following advantages: 1) Substituting the gate electrode prevents the necessity for conventional spacers and prevents the deposition of an interlayer insulating film, thereby simplifying the fabrication process considerably. 2) The insulating layer conforms to the contour of the gate electrode, obviating the deposition process for the insulating layer. This prevents defects that may emerge during additional insulating layer processing, mitigating electrode damage and averting diminished yields. 3) As a result, VTFT configuration offers an exceedingly short channel in the nm range, corresponding to the gate thickness, thereby producing a low power consumption—an outstanding advantage for driving applications.Consequently, this research holds the potential to substantially contribute to the advancement of low-power electronic devices and the realization of next-generation display applications, encompassing form factor innovations, automotive integration, and AR/VR implementation, while simultaneously addressing the challenges posed by vertical TFT technology. Figure 1

Notched Gate and Graded Gate Oxide Processing for Reduced Capacitance Application in RF MOSFETs

As the demands of RF applications are rising, optimization of internal MOSFETs capacitances is a key issue to improve the cut-off frequency. In this abstract we report the development of a novel N-MOS architecture processed on 8-inch SOI wafers. This architecture has a gate oxide with variable thickness along the channel and a reduced bottom gate length aiming at minimizing Gate to Drain/Source capacitance (1) (2). This improvement on Gate to Drain/Source capacitance mainly comes from a decrease in overlap capacitances as described in (3).The new process flow is composed as usual until Poly-Si gate etching. By controlling the species flow and process time during plasma etching steps, over etch at the bottom of the gate is performed (fig.1(a,b)). Poly-Si gate notching engineering is possible due to reduction of the passivation layer thickness at the bottom of the gate during plasma etch. As described in (4) the gate is first etched using a HBr/CL2/O2 chemistry until reaching close to the bottom of the gate, allowing the formation of a passivation layer made of SiOxCly and the anisotropy of the etch. To etch the remaining thickness HBr flow is augmented while CL2 and O2 flow are reduced, preventing formation of passivation layer. This leads to isotropic etch of the bottom gate and reduction of the gate length as regard to the top Poly-Si dimension. This over-etch reduces the physical gate length without changing the effective and the on-mask gate lengths, leading to overlap capacitance reduction.To produce gate oxide with variable thickness under gate sidewalls a two-steps process is performed. First, full plate oxide is grown before poly-Si deposition to act as middle gate thickness. Then undercut is performed, consisting of lateral etching of the gate oxide under gate sidewall after gate etch (fig.2.a). To achieve this undercut, hydrofluoric acid (HF) wet etch has been chosen. First trials with very low HF concentration become quickly saturated leading to small lengths under gate sidewalls (fig.2.b). Then more acidic solutions were used allowing satisfying undercut lengths (fig.2.c).Finally rapid thermal oxidation (RTO) is performed to obtain an oxide bird beak at both gate side as both Poly-Si gate and Si from the active region react with ambient O2 in the chamber. This leads to a gate oxide with variable thickness along the channel (fig.3(a.b)) which has both effects: to get smoother poly-Si foot and a down step in the active between channel and Source/Drain regions. During this process step, a built-in spacer on the gate sides for LDD implantation is formed. RTO process step has grown a thicker oxide over Source/Drain areas which has to be reduced to allow an accurate LDD implantation, this is done by anisotropic etching. After these new steps, the process goes back to a standard N-MOS process flow.Some early versions of the notched gate have been investigated (5), and these experiments and details on processing recipe seem promising for electrical results. As poly-Si foot has been smoothed and graded gate oxide (GGO) on top of overlaps region is formed. It would allow a reduction in parasitic capacitances improving cut-off frequency of RF applications.References RF LDMOSFET with Graded Gate Structure. Xu Shuming, Foo Pan Dow. Toronto : s.n., 2001. 1th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings. pp. 221-224. DOI:10.1109. Notched-Gate pMOSFET with ALD TiN/High-κ Gate Stack Formed by Selective Wet Etching. Zhang, D. Wu and J. Lu and P.-E. Hellström and M. Östling and S.-L. s.l. : The Electrochemical Society, Inc., 2004, Electrochemical and Solid-State Letters, Vol. 7, p. 228. 10.1149/1.1795612. A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs. Fabien Pregaldiny, Christophe Lallement,Daniel Mathiot. s.l. : Solid State Electronics, 2002, Vol. 46, pp. 2191–2198. https://doi.org/10.1016/S0038-1101(02)00248-4. Design of notched gate processes in high density plasmas. J. Foucher, G. Cunge, L. Vallier, and O. Joubert. s.l. : AVS: Science & Technology of Materials, Interfaces, and Processing, 2002, Vols. Journal of Vacuum Science & Technology B 20,. http://dx.doi.org/10.1116/1.1505959. Notched gate MOSFET for capacitance reduction in RF SOI technology. al, L. Antunes et. s.l. : 2023 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS), 2023. doi: 10.1109/DTTIS59576.2023.10348288. Figure 1

Nanometer-thick TiO2 channel thin film transistors as radical monitors for plasma enhanced atomic layer deposition

Nanometer-thick-TiO2-channel thin-film transistors (TFTs) are examined as oxidizing-agent monitors for room-temperature atomic layer deposition (RTALD). RTALD is a plasma-based process using plasma-excited humidified argon where OH radicals oxidize the precursor-gas adsorbed surface. In the TFT, the anatase TiO2 channel, with a thickness of 16 nm, is attached to a 300 nm thick gate capacitor of SiO2, while the channel surface is exposed to the ALD ambient. A heavily doped n-type Si substrate attached to the gate SiO2 is used as the gate electrode. The gate width and length are 1000 and 60 μm, respectively. When the TFT is installed in the RTALD chamber, the drain-current waveform is recorded in the course of the metal organic gas adsorption, evacuation of the residual gas, oxidization, and evacuation. In the present study, three kinds of metal organic (MO) precursors, tetrakis(dimethyl)amino titanium, tris(dimethyl)amino silane, and trimethyl aluminum are examined. The drain current exhibits strong responses upon the exposure of the plasma excited humidified argon. This suggests that OH radicals in the plasma might oxidize the adsorbed MO precursors to produce the OH moieties, where the surface polarization of OH moieties might enhance channel conductivity. The experimental results suggest the applicability of the present TFT as a plasma monitor in RTALD.

Ultra-High-k Ferroelectric BaTiO3 Perovskite in the Gate Stack for Two-Dimensional WSe2 p-Type High-Performance Transistors.

The experimental demonstration of a p-type 2D WSe2 transistor with a ferroelectric perovskite BaTiO3 gate oxide is presented. The 30 nm thick BaTiO3 gate stack shows a robust ferroelectric hysteresis with a remanent polarization of 20 μC/cm2 and further enables a capacitance equivalent thickness of 0.5 nm in the hybrid WSe2/BaTiO3 stack due to its high dielectric constant of 323. We demonstrate one of the best ON currents for perovskite gate 2D transistors in the literature. This is enabled by high-quality epitaxial growth of BaTiO3 and a single 2D layer transfer based fabrication method that is shown to be amenable to silicon platforms. This demonstration is an important milestone toward the integration of crystalline complex oxides with 2D channel materials for scaled CMOS and low-voltage ferroelectric logic applications.

On the TCAD Modeling of Non-Permanent Gate Current Increase during Short-Circuit Test in SiC MOSFETs

Under short-circuit (SC) testing SiC MOSFETs exhibit an exceptional increase of gate current (100’s mA) which is not observed in their Si counterparts. Electro-thermal TCAD simulations are capable to accurately mimic all the details of measured gate current waveforms (iG) by capturing multiple physical mechanisms. One of these mechanisms is the thermionic or Schottky emission effect occurring at extreme temperatures (>1300K) for relatively thick gate oxides (>40nm). For the first time, it is proven that TCAD tunneling models, recommended for very thin oxides (<3nm), are suitable to reproduce the thermionic effect and predict iG in SiC MOSFETs under SC test.

Integration of Vertical Graphene Onto a Tunnelling Cathode for Digital X-Ray Imaging.

As an alternative to thermionic X-ray generators, cold-cathode X-ray tubes are being developed for portable and multichannel tomography. Field emission propagating from needle structures such as carbon nanotubes or Si tips currently dominates related research and development, but various obstacles prevent the widespread of this technology. An old but simple electron emission design is the planar tunnelling cathode using a metal-oxide-semiconductor (MOS) structure, which achieves narrow beam dispersion and low supplying voltage. Directly grown vertical graphene (VG) is employed as the gate electrode of MOS and tests its potential as a new emission source. The emission efficiency of the device is initially ≈1% because of unavoidable fabrication damage during the patterning processes; it drastically improves to >40% after ozone treatment. The resulting emission current obeys the Fowler-Nordheim tunnelling model, and the enhanced emission is attributed to the effective gate thickness reduction by ozone treatment. As a proof-of-concept experiment, a clustered array of 2140 cells is integrated into a system that provides mA-class emission current for X-ray generation. With pulsed digital excitations, X-ray imaging of a chest phantom, demonstrating the feasibility of using a VG MOS electron emission source as a new and innovative X-ray generator is realized.

[formula omitted] IO buffer with [formula omitted] devices considering hot-carrier and gate-oxide reliability issues

This paper presents circuit for 2×VDD signaling I/O buffer to solve the gate-oxide and hot-carrier reliability issues without consuming any active static power. The design is verified for a range of loads varying from 4 pF to 200 pF with operating speed ranging from 12 Mbps to 500 Mbps. The proposed circuit is implemented in 16 nm FinFET technology using 1.8 V thick gate devices. The design can be used in any CMOS technology for 2×VDD signaling I/O buffer to reduce hot-carrier effect and to avoid gate-oxide reliability issues.

Parameteric optimization of SiGe S/D NT JLFET using analytical modeling to improve L‐BTBT induced GIDL

AbstractIn the present work, we investigate the impact of structure dimensional parameters on the short channel effects which occurs especially below 20 nm regime particularly gate induced drain leakage (GIDL) current. Using technology computer aided design simulation (TCAD), we have examined the GIDL for SiGe as source/drain in NTJLFET. The structural dimensional parameters such as the nanotube thickness, core and outer gates thickness and gate electrode work function shows the significant impact on the band to band tunneling in lateral direction (L‐BTBT) which induced GIDL current. It is analyzed that increase in the nanotube thickness and physical oxide thickness increase the GIDL current, while increasing the gate electrode work function, core gate and outer gate thicknesses gives reduced GIDL current. The SiGe S/D NTJLFET produce a remarkable high ION/IOFF ratio ~ 1011. A compact model for GIDL current is also developed which shows the dependency of structure parameters on leakage current. The SiGe has been incorporated as source and drain in NTJLFET which creates the energy band discontinuity. Furthermore, SiGe S/D NTJLFET is fairly compared with the conventional NT JLFET and nanowire (NW) JLFET and shows an improved performance.

Compact Modeling of Advanced Gate-All-Around Nanosheet FETs Using Artificial Neural Network.

As the architecture of logic devices is evolving towards gate-all-around (GAA) structure, research efforts on advanced transistors are increasingly desired. In order to rapidly perform accurate compact modeling for these ultra-scaled transistors with the capability to cover dimensional variations, neural networks are considered. In this paper, a compact model generation methodology based on artificial neural network (ANN) is developed for GAA nanosheet FETs (NSFETs) at advanced technology nodes. The DC and AC characteristics of GAA NSFETs with various physical gate lengths (Lg), nanosheet widths (Wsh) and thicknesses (Tsh), as well as different gate voltages (Vgs) and drain voltages (Vds) are obtained through TCAD simulations. Subsequently, a high-precision ANN model architecture is evaluated. A systematical study on the impacts of ANN size, activation function, learning rate, and epoch (the times of complete pass through the entire training dataset) on the accuracy of ANN models is conducted, and a shallow neural network configuration for generating optimal ANN models is proposed. The results clearly show that the optimized ANN model can reproduce the DC and AC characteristics of NSFETs very accurately with a fitting error (MSE) of 0.01.

Improvement of AlSiO/GaN interface by a novel post deposition annealing using ultra high pressure

In this study, a novel post-deposition annealing (PDA) technique employing ultra-high pressure was demonstrated for the first time. A 40 nm thick AlSiO gate insulator was deposited using atomic layer deposition (ALD) on n-type gallium nitride (GaN) epitaxial layers grown on free-standing GaN substrates. These PDA techniques were performed at 600 °C in a nitrogen ambient under 400 MPa, with normal pressure conditions used as the references. The annealing duration varied within the range of 10, 30, 60, and 120 min. For normal pressure annealing, the flat-band voltage of capacitance-voltage curves exhibited a shift towards the positive bias direction as the annealing time increased. Conversely, for the 400 MPa annealing, the flat-band voltage approached the ideal curve as the annealing time extended. For 400 MPa and 120 min, low interface state density of ∼5 × 1011 cm−2 eV−1 or less at E c −0.20 eV was obtained. These results suggest that post-deposition annealing under ultra-high pressure could be a viable method for improving the interfacial characteristics of AlSiO/GaN.

Degradation and Failure Mechanism of p-GaN Gate E-Mode GaN HEMTs

GaN-based power transistors are becoming pivotal devices for high power and high voltage operation due to their higher breakdown voltage, higher carrier mobility because of two-dimensional electron gas (2-DEG), better thermal resistance, higher frequency switching, and lower on-state resistance (RON) [1]. P-GaN gate E-mode GaN HEMTs have emerged as a center of extensive research to understand their operation and reliability [2]. However, one of the reasons the E-mode GaN HEMTs are not yet successfully utilized to their maximum potential is the lack of complete understanding of gate breakdown. Gate degradation of p-GaN gate E-mode GaN HEMT is less understood because of the complexities involving the operating conditions and variables such as gate length, the acceptor doping concentration in the p-GaN layer [3], p-GaN gate thickness, and design of the device [4-5]. To outline a consistent degradation mechanism, this work aims to present an electro-physical model of gate breakdown in p-GaN gate E-mode HEMTs.Lateral E-mode GaN HEMT devices with p-GaN gate configuration are used for this study. According to the Scanning Transmission Electron Microscopy (STEM) imaging of a new device, the AlGaN barrier is 10 nm thick, and the p-GaN cap is 65 nm. The gate-source and gate-drain lengths are 0.5 micrometer and 2.5 micrometer, respectively. The gate length defined by the p-GaN layer is 0.5 micrometer and the edges of the gate metal are pulled in from the top edge of the p-GaN layer by 40 nm. A 0.7 micrometer-long, source-connected field plate is over the p-GaN gate. The p-GaN gate is subjected to static stress to induce accelerated breakdown. Devices were stressed with HP 4155 Semiconductor Analyzer. The electrical measurements were performed with the source, drain, and substrate connected to the ground. FEI 200 Nova was used for Scanning Electron Microscopy (SEM) imaging and Focused Ion-Beam (FIB) milling. ARM JEM-200F with a Cs corrector was used for STEM.Our results show that time-to-fail is highly dependent on device operating conditions. We found no correlation between time-to-fail and initial gate current (IG0). Instead, a higher impact of temperature was found on the gate current of the device (IG) and time-to-fail at 100 °C. Gate failure at constant voltage stress was a single-stage failure. Under constant current stress, on the other hand, the gate shows a multi-stage failure. The breakdown mechanism depends on the impact of static stress on the gate degradation, starting with increased gate current leading to Schottky barrier leakage and finally to catastrophic contact failure. Our study shows that the metal/p-GaN interface at the gate finger becomes the weakest part of the gate stack, likely to be the initiation point of degradation. Metal/p-GaN interface and surface defects develop as percolation paths acting as leakage sources, and nano-cracks have been observed in the gate cap. FA also shows physical degradation at the metal/p-GaN cap due to electrical stress. Observed physical damage in the gate region is correlated to the gate leakage characteristics to develop an electro-physical failure model for gate breakdown in p-GaN gate E-mode GaN HEMTs.

Modulation of Ciss of a 4H-SiC Planar MOSFET With a Shorter Sidewall and a Thicker Gate

Modulation of C_iss of a 4H-SiC Planar MOSFET With a Shorter Sidewall and a Thicker Gate

Enhancement of electrical performance in indium-zinc oxide thin-film transistors with HfO2/Al2O3 gate insulator deposited via low-temperature ALD

Several studies have been conducted on amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) with the aim of applying them to the next-generation low-power displays. To improve the electrical performance of conventional AOS TFTs, which are known for their poor switching characteristics, we fabricated indium-zin oxide (IZO) TFTs with HfO2/Al2O3 gate insulator deposited via low-temperature atomic layer deposition (ALD). We optimized the electrical performance of the fabricated TFTs by varying the thickness of the IZO channel and Al2O3 insulator, respectively. Compared to the samples with a thermally grown 150 nm thick SiO2 gate insulator, the samples with a 10 nm thick IZO channel and a 10/70 nm thick HfO2/Al2O3 gate insulator exhibited the subthreshold swing of 0.24 V/dec, saturation carrier mobility of 7.49 cm2/V∙s and on–off current ratio of 1.09 × 107, which were improved by more than 47 %, 64 % and 5 times, respectively. Also, the threshold voltage shift in positive and negative bias stress conditions were improved to + 0.90 and – 1.75 V, respectively.

Investigation of the time dependent gate dielectric stability in SiC MOSFETs with planar and trench gate structures

In this work, the time-dependent dielectric breakdown (TDDB) analysis is performed to understand the gate oxide reliability in SiC MOSFETs with two different structures, i.e., planar and trench gate structures. We have discovered different gate leakage current behaviors between the SiC MOSFETs with planar gate (Sample A) and trench gate (Sample B) during the forward gate bias stress. Notably, the slight increase of the gate current during the stress and the negative activation energy (Ea = −0.07 eV) observed in Sample A suggest that the hole generation caused by the impact ionization can be occurred during the forward gate TDDB tests. Furthermore, the SiC MOSFETs with trench gate structure (Sample B) exhibit the operation voltage of 55.7 V (exponential law) and 57.3 V (power law) for the 0.001 % failure of 30 years under 175 °C, indicating that SiC trench gate MOSFETs with enough thick gate dielectric (87.1 nm (bottom) and 77.9 nm (sidewall)) can have the promising forward gate TDDB stability.

Role of Proportion of Surrounding Gate on the Improved Transient Behavior of MIS Tunnel Diode with Ultra-Thin Metal Surrounded Gate (UTMSG)

Metal-Insulator-Semiconductor tunnel diodes (MISTD) are widely used in modern integrated circuits, and have shown the potential in dynamic memory [1], [2]. To recognize the memory states more easily, efforts should be made to enhance the transient behavior. Recently, MISTD with ultra-thin metal surrounded gate (UTMSG) had been proposed in [3] and [4], presenting improved transient current and transient capacitance. In this work, we further modulated the proportion of surrounding gate, S, and found increased transient behavior for larger S.Fig. 1(a) and (b) illustrate the structure of UTMSG and planar MISTD, respectively. For UTMSG, the total gate is composed of a thick metal center gate and a resistive thin metal surrounding gate. Fig. 2 shows the process flow and the anodic oxidation system. For UTMSG, after defining the center gate by photolithography, dilute nitric acid was used to form a very thin aluminum oxide layer on the edge. 10 nm Al was then evaporated as the resistive surrounding gate. Table 1 lists the detailed parameters and the proportion of surrounding gate, S. Fig. 3(a) shows the transient read currents for UTMSG and planar, with inset illustrated the voltage program. Fig. 3(b) shows the read currents extracted at 40 ms under different read voltages after a 2 V write pulse. All UTMSG show larger transient current than planar. Besides, UTMSG with larger S would have better performance. The reason could be explained by Fig. 3(c). The insulating aluminum oxide interlayer and the resistive thin metal surrounding gate together result in a distributed resistance, leading to an RC time delay during voltage switching. During read, the electrons stored under the surrounding gate would take longer to response. Therefore, larger current could be read out, due to the edge late response. Consequently, more electrons would be delayed for larger S, and larger transient current would be expected.Fig. 4(a) and (b) show the AC signal model and the reverse-bell shape capacitance-voltage (C-V) characteristics of UTMSG, which were discussed in detail in previous work [5]. When Rsi, determined by the electron density under gate, is small enough such that the cut-off frequency 1/2πRsiCs,o is larger than the AC frequency, Cs,o could be read out. Fig. 5 shows the frequency dispersion of C-V curves. For lower frequencies, lower VG is needed for the AC signal to pass through.Fig. 6(a) shows the 10kHz C-V curves, on which ± 0.5 V voltage pulse were performed to read out two capacitance states. Fig. 6(b) shows the transient capacitance read at 0 V. When switching from + 0.5 V to 0 V, excess electron would be stored under gate initially. To balance the gate voltage, depletion region would shrink and high capacitance state would be measured, which would be more significant for UTMSG due to more delay of electron. For UTMSG at – 0.5 V and 0 V, depletion capacitance under center gate Cs,i and under total gate Cs,i + Cs,o would be read out, respectively. This means after applying a - 0.5 V pulse and then read at 0 V, UTMSG devices would experience a larger change of capacitance. Moreover, since the capacitance at - 0.5 V is lower for UTMSG with larger S, the change of capacitance would be larger. The two state capacitance windows measured at 30 ms are shown in Fig. 6(c), where larger capacitance window could be observed for UTMSG with larger S. Finally, the capacitances when sweeping voltage forwardly and backwardly and the separation between them were shown in Fig. 7(a) and (b) for UTMSG and planar devices. All UTMSG show larger separations, which further confirms the improved transient capacitance window observed in Fig. 6.In conclusion, transient behavior could be further improved by increasing the proportion of surrounding gate in UTMSG MISTD, and 17x read current and 14x capacitance window could be measured. The discovery in this work might be beneficial for the future dynamic memory design.Acknowledgement: This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 111-2221-E-192-MY3 and NSTC 111-2622-8-002-001[1] M. A. Green, F.D. King and J. Shewchun, Solid-State Electronics, 17, 6, pp. 551-561, (1974).[2] S.-W. Huang and J.-G. Hwu, IEEE Trans. on Electron Dev., 68, 12, pp. 6580-6585 (2022).[3] K.-H. Tseng, C -S. Liao and J. -G. Hwu, IEEE Trans. on Nanotech., 16, 6, pp. 1011-1015, (2017).[4] C.-D. Lin and J.-G. Hwu, ECS Trans., 85, 51, (2018).[5] S.-W. Huang and J.-G. Hwu, IEEE J. of the Electron Devices Soc., 9, pp. 1041-1048, (2021). Figure 1

High-Density Vertical Transistors with Pitch Size Down to 20nm.

Vertical field effect transistors (VFETs) have attracted considerable interest for developing ultra-scaled devices. In particular, individual VFET can be stacked on top of another and does not consume additional chip footprint beyond what is needed for a single device at the bottom, representing another dimension for high-density transistors. However, high-density VFETs with small pitch size are difficult to fabricate and is largely limited by the trade-offs between drain thickness and its conductivity. Here, a simple approach is reported to scale the drain to sub-10nm. By combining 7nm thick Au with monolayer graphene, the hybrid drain demonstrates metallic behavior with low sheet resistance of ≈100 Ω sq-1 . By van der Waals laminating the hybrid drain on top of 3nm thick channel and scaling gate stack, the total VFET pitch size down to 20nm and demonstrates a higher on-state current of 730A cm-2 . Furthermore, three individual VFETs together are vertically stacked within a vertical distance of 59nm, representing the record low pitch size for vertical transistors. The method pushes the scaling limit and pitch size limit of VFET, opening up a new pathway for high-density vertical transistors and integrated circuits.

Total ionizing dose effects of 60Co-γ ray radiation on SiC MOSFETs with different gate oxide thickness

The application of SiC power devices in the space radiation environment not only requires good resistance to Single Event Effect (SEE) but also requires certain resistance to Total Ionizing Dose (TID) and long-term reliability. Increasing the thickness of the gate oxide layer (tox) can effectively improve the ability of SiC VDMOS to resist SEE. However, it will mainly impact its resistance to TID and Gate Oxide Integrity (GOI). Therefore, this paper compares the influence of tox on the radiation resistance and long-term reliability of SiC VDMOS under the same process and irradiation conditions. The experimental results show that after being irradiated by Cobalt-60 γ-rays, the static parameters of SiC VDMOS devices degrade severely with the increase of the tox; at the same time, the thick gate oxide process will also cause more defects in the gate oxide, leading to the decrease of the gate oxide long-term reliability, but it can be significantly improved after high temperature (HT) accelerated annealing. The research results suggest that the method of increasing tox should take into account the requirements of TID resistance and long-term reliability when improving the SEE radiation resistance of SiC VDMOS. This study is based on the improvement of electrical parameters and the analysis of reliability degradation of SiC VDMOS, providing experimental data support for determining the balance point of tox.

Investigation of 4H-SiC UMOSFET Architectures for High Voltage and High Speed Power Switching Applications

A comparative TCAD (Technology Computer Aided Design) simulation study of various 4H-SiC trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (or U-shaped trench gate MOSFET abbreviated for UMOSFET) architectures for high voltage and high-speed switching applications is reported. The DC (Direct Current) and AC (Alternating Current) characteristics of the different trench gate structures are investigated. Particularly, compared to conventional 4H-SiC UMOSFETs, the breakdown voltage of the UMOSFET having a p-type implanted bottom shield is increased by 44%. However, due to the extra JFET (Junction Field Effect Transistor) region, the specific on resistance also increases by 6%. Furthermore, under 1000 V drain bias, the peak electric field at the bottom oxide of the shielded trench gate is below 0.3 MV/cm. In contrast, the peak electric field of conventional UMOSFETs can be as high as 8 MV/cm, which might cause reliability issues. On the other hand, when the bottom oxide thickness of the trench gate is increased, the UMOSFET exhibits 22% less total gate charge, leading to 76% and 71% shorter switching delay time, compared to conventional UMOSFETs and bottom shield UMOSFETs, respectively. As revealed by the simulation results, the UMOSFETs with the p-type implanted bottom shield or thick bottom oxide are advantageous for high voltage and high-speed power switching applications.

Investigation of Gate Induced Drain Leakage in Nanotube and Nanowire: A Comprehensive Study

In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon-nanotube (Si-NT JLFET), SiGe Source/Drain silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET) and conventional nanowire (NW) have been performed using technology computer-aided design simulations. We have also demonstrated that inclusion of SiGe S/D in Si-NT JLFET reduced the OFF-state current by order of [Formula: see text]3 from NT JLFET and by order of [Formula: see text]6 from NW JLFET. The impact of variation of core gate thickness ([Formula: see text], germanium (Ge) content [Formula: see text], and location of SiGe in source and drain regions of the S/D Si-NT JLFET have been studied from the GIDL perspective. We found that SiGe S/D Si-NT JLFET exhibits impressively high [Formula: see text]/[Formula: see text] ratio [Formula: see text]10[Formula: see text] with reduced lateral band-to-band tunneling (L-BTBT)-induced GIDL than the conventional nanowire device. The is due to SiGe S/D that creates a energy valence band discontinuity at source drain interfaces which limits the flow of electrons from channel to drain region in the OFF-state.

Research on high temperature performance of pressure sensor

This work proposes a molybdenum (Mo) based pressure sensor capable of operating at temperatures higher than 300 °C. The sensor utilizes a 30 μm thick rectangular pressure-sensitive film and 2 μm thick gate Mo resistors to form a Wheatstone bridge structure to enhance pressure sensing. Finite element analysis (FEA) has been performed to design the sensor and analyze the pressure and temperature effect. The developed sensor with the excitation of 1 V voltage exhibits excellent performance characteristics at room temperature (25 °C), including a sensitivity of 0.05689 mV V−1 kPa−1, 0.15% full scale (FS) accuracy, a nonlinearity of 0.79% FS, and 0.02% FS repeatability. The thermal zero shift of −0.13% FS/°C is obtained in the 25 °C to 300 °C temperature range. The simulation findings illustrate that the thermal mismatch weakens the thermal zero shift by +0.012‰ FS/°C, while the deviation of the temperature coefficient of resistance (TCR) and initial resistivity () aggravate the thermal zero shift by −0.139% FS/°C. Among both, the deviation of and TCR is the major contributor to thermal zero shift. Moreover, it was found that the Seebeck effect caused by the on-chip temperature gradient also affects the accuracy of the sensor. A temperature difference of 5.4 °C produces a thermoelectric potential of 37.95 μV equivalent to a pressure of 670 Pa loading on the chip. Besides, the response characteristics of the sensor at different temperature rates were investigated.