Gate Stack Research Articles

Enhanced quality of Al2O3/SiC gate stack via microwave plasma annealing

Enhanced quality of Al2O3/SiC gate stack via microwave plasma annealing

Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors

Ferroelectric transistors based on hafnia-based ferroelectrics exhibit tremendous potential as next-generation memories owing to their high-speed operation and low power consumption. Nevertheless, these transistors face limitations in terms of memory window, which directly affects their ability to support multilevel characteristics in memory devices. Furthermore, the absence of an efficient operational technique capable of achieving multilevel characteristics has hindered their development. To address these challenges, we present a gate stack engineering method and an efficient operational approach for ferroelectric transistors to achieve 16-level data per cell operation. By using the suggested engineering method, we demonstrate the attainment of a substantial memory window of 10 V without increasing the device area. Additionally, we propose a displacement current control method, facilitating one-shot programming to the desired state. Remarkably, we suggest the compatibility of these proposed methods with three-dimensional (3D) structures. This study underscores the potential of ferroelectric transistors for next-generation 3D memory applications.

A new stacked gate oxide L-shaped tunnel field effect transistor

A new stacked gate oxide L-shaped tunnel field effect transistor

Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study.

Since its invention in the 1960s, one of the most significant evolutions of metal-oxide semiconductor field effect transistors (MOSFETs) would be the 3D version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During recent decades, the width of fin (Wfin) and the neighboring gate oxide width (tox) in FinFETs has shrunk from about 150 nm to a few nanometers. However, both widths seem to have been leveling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting the Penn model and Maxwell-Garnett mixing formula for a dielectric constant (κ) calculation for nanolaminate structures, FinFETs with two- and three-stage κ-graded stacked combinations of gate dielectrics with SiO2, Si3N4, Al2O3, HfO2, La2O3, and TiO2 perform better against the same structures with their single-layer dielectrics counterparts. Based on this, FinFETs simulated with κ-graded gate oxides achieved an off-state drain current (IOFF) reduced down to 6.45 × 10-15 A for the Al2O3: TiO2 combination and a gate leakage current (IG) reaching down to 2.04 × 10-11 A for the Al2O3: HfO2: La2O3 combination. While our findings push the individual dielectric laminates to the sub 1 nm limit, the effects of dielectric permittivity matching and κ-grading for gate oxides remain to have the potential to shed light on the next generation of nanoelectronics for higher integration and lower power consumption opportunities.

Overlapping top gate electrodes based on low temperature atomic layer deposition for nanoscale ambipolar lateral junctions

We present overlapping top gate electrodes for the formation of gate defined lateral junctions in semiconducting layers as an alternative to the back gate/top gate combination and to the split gate configuration. The optical lithography microfabrication of the overlapping top gates is based on multiple layers of low-temperature atomic layer deposited hafnium oxide, which acts as a gate dielectric and as a robust insulating layer between two overlapping gate electrodes exhibiting a large dielectric breakdown field of >1×109V m−1 . The advantage of overlapping gates over the split gate approach is confirmed in model calculations of the electrostatics of the gate stack. The overlapping gate process is applied to Hall bar devices of mercury telluride in order to study the interaction of different quantum Hall states in the nn′, np, pn and pp′ regime.

A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing

Dielectrically modulated (DM) negative capacitance field effect transistor (NCFET)-based label-free biosensors have emerged as promising devices for accurate detection of various biomolecules, where the sensitivity of DM architectures strongly depends on the sensing mechanism as well as on the size of the nanocavity. Therefore, to achieve higher sensitivity along with reduced fabrication complexity, we propose to utilize a pre-existing drain-side spacer region as a nanocavity, in a fully depleted silicon-on-insulator-based NCFET architecture. The ferroelectric (FE) layer in the metal-ferroelectric-insulator-semiconductor configuration meaningfully alters the impact of the drain’s electric field on the source-side electrostatics, which results in higher sensitivity. Having quantified the sensitivity of an FE-dielectric (FE-DE) gate-stack-based NCFET biosensor, we now propose to include a paraelectric (PE) layer between the FE and DE materials, thus modifying the gate stack from FE-DE to FE-PE-DE with an equivalent negative capacitance seen from both stacks; here, a remarkable improvement is seen in the FE-PE-DE gate-stack-based NCFET, with nearly identical linearity performance, as seen from the high Pearson’s coefficient value ( r2⩾ 0.9). Therefore, to illustrate the efficacy of the proposed sensing mechanism and the modified gate stack (FE-PE-DE), DE constant ( kBio ) values in the range of kBio = 4.5 to kBio = 75.99 are considered. Finally, the effect of scaling the channel length ( Lg ) on the sensitivity of the FE-PE-DE NCFET device is shown, and a high value, particularly at lower permittivity, demonstrates the versatility and wide applicability of the proposed NCFET biosensor.

Impact of Oxide Charges on The Minority Carrier Response in MOS(p) Devices With Al2O3/SiO2 Gate Stacks under Strong Inversion Condition

In this study, a compact model proposed in the previous work (2) was utilized to elucidate an unusual minority carrier response time observed in MOS(p) devices with Al2O3/SiO2 gate stacks. It is supposed that the number of oxide charges increases with SiO2 thickness. The findings confirmed the heightened sensitivity of device alternating current (AC) characteristics to oxide charges in the outer region. Accordingly, we explored the dependencies of oxide thickness and quality on the transition frequency (ωm) of devices.

Density functional model of threshold voltage shifts at High-K/Metal gates

A density functional analysis of oxide dipole layers used to set the threshold voltages in high-K/metal CMOS gate stacks is given in terms of the band alignments and chemical trends of these component oxide layers. The oxides SrO, La2O3, HfO2 and Al2O3 are found to have similar band gaps and form a ‘staircase’ of band alignments, allowing them to shift the metal electrode Fermi level in both n-type and p-type directions. This analysis supersedes previous largely empirical models based on metal oxide ion densities or electronegativity scales.

Boltzmann Switching MoS2 Metal-Semiconductor Field-Effect Transistors Enabled by Monolithic-Oxide-Gapped Metal Gates at the Schottky-Mott Limit.

A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal-semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS2) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of ≈60mVdec-1 and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (EF) pinning-free gate stack at the Schottky-Mott limit. Furthermore, authors experimentally and theoretically confirm that EF depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS2 channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics.

Circuit Level Implementation of Negative Capacitance Source Pocket Double Gate Tunnel FET for Low Power Applications

This manuscript presents a pioneering study on enhancing analog and radio frequency performance through the implementation of negative capacitance source pocket double gate tunnel field-effect transistor. By integrating a ferroelectric material into the gate stack and introducing a fully depleted n-type pocket near the source/channel junction, we achieved significant enhancements in key metrics such as ON current (ION), switching ratio, subthreshold swing (SS), and various analog/RF parameters like transconductance (gm), cutoff frequency (fT) when compared to existing literature. Additionally, we extend our analysis to circuit-level applications such as inverter and 5-stage ring oscillator. Our findings reveal an impressive inverter delay of 1.09 ps with a gain of 104, as well as a ring oscillator operating at a frequency of 500 GHz. These results position the proposed device as an ideal candidate for high-speed, low-power applications.

Atom-Scaled Hafnium Doping for Strengthening the Germanium Oxide Interfacial Layer of The Gate Stack of Germanium P-Type Metal-Oxide-Semiconductor Field Effect Transistor

We have developed a method that uses a half-cycle Hf precursor adsorption to subtly dope GeO2 IL of the Hf-based gate stack through in situ plasma-enhanced atomic layer deposition. This technique can effectively reduce GeO vaporization and improve the thermal stability of the GeO2 layer. Our results indicated that the accumulation capacitance (Cacc) undergoing higher temperatures showed no noticeable increase in the capacitance-voltage (CV) curves once Hf was delicately introduced into the GeO2 layer. According to the Ge 3d spectra of X-ray photoelectron spectroscopy, we found that the IL had a signal from extra Hf-O bonds; thus, we conclude GeO evaporation can be suppressed substantially by Hf incorporation. As a result, adding metal into GeOx IL to form HfGeOx achieved a remarkably low leakage current of 9 × 10−5 A cm−2 and the lowest interface trap density (Dit) of approximately 2 × 1011 eV−1 cm−2 at 500 °C of PMA. In addition, applying this gate stack structure to device fabrication significantly reduced the leakage current of the off-state and improved the effective peak hole mobility.

Design and Simulation of Dielectrically Modulated Dual Material Gate-Stack Double-Gate FinFET Biosensor

This study developed and evaluated a dual-material gate stack double-gate FinFET-based biosensor (DM-GS-DG FinFET). The device was dielectrically modulated and investigated for molecules, such as streptavidin, gluten, zein, hen egg-white lysozyme, and acetylene tetrabromide, based on current, threshold voltage, subthreshold swing, and switching sensitivity. The influence of charged and neutral biomolecules within the nanocavity on the electric, analog, and radiofrequency parameters was recorded. This study was conducted relative to different dielectric κ-values of 12 in terms of the percentage sensitivity improvement (SI%). The results reveal that the percentage of sensitivity ION improves effectively, especially for low κ-values, compared with other sensitivity measures. All the sensitivity evaluations indicated that DM-GS-DG-FinFET combined with biomolecules is a viable option for biosensing purposes.

Performance improvements in complementary metal oxide semiconductor devices and circuits based on fin field-effect transistors using 3-nm ferroelectric Hf0.5Zr0.5O2

In this work, a conventional HfO2 gate dielectric layer is replaced with a 3-nm ferroelectric (Fe) HZO layer in the gate stacks of advanced fin field-effect transistors (FinFETs). Fe-induced characteristics, e.g., negative drain induced barrier lowering (N-DIBL) and negative differential resistance (NDR), are clearly observed for both p- and n-type HZO-based FinFETs. These characteristics are attributed to the enhanced ferroelectricity of the 3-nm hafnium zirconium oxide (HZO) film, caused by Al doping from the TiAlC capping layer. This mechanism is verified for capacitors with structures similar to the FinFETs. Owing to the enhanced ferroelectricity and N-DIBL phenomenon, the drain current (IDS) of the HZO-FinFETs is greater than that of HfO2-FinFETs and obtained at a lower operating voltage. Accordingly, circuits based on HZO-FinFET achieve higher performance than those based on HfO2-FinFET at a low voltage drain (VDD), which indicates the application feasibility of the HZO-FinFETs in the ultra-low power integrated circuits.Graphical abstract

Mechano-driven logic-in-memory with neuromorphic triboelectric charge-trapping transistor

In the post-Moore's Law era, there is a growing trend towards the development of advanced electronic devices that combine sensory perception, data storage, and computation for various applications. Two-dimensional semiconductor transistors, which utilize charge storage mechanisms, present a promising avenue for future information devices. Here, we introduce a neuromorphic triboelectric charge-trapping MoTe2 transistor with stacked high-k dielectric structure, aiming to facilitate mechano-driven logic-in-memory for neuromorphic computation. By gating through triboelectric potential, the device demonstrates superior electrical performance, including an impressive switching ratio (>105), minimal off-state current (∼0.6 pA), and robust cyclic stability. By modulating the trapped charges in the stack gate structure via tribopotential modulation, the conductivity state of the MoTe2 channel can be readily controlled, realizing an exceptional mechano-driven nonvolatile memory with a retention time of up to 104 seconds, consistent switching behavior over 100 cycles, and multi-level data storage capabilities at 8 levels. Furthermore, a mechano-driven programmable inverter can be achieved by connecting a load resistor in series. The triboelectric charge-trapping transistor also possesses the capacity to emulate typical synaptic characteristics at low energy levels (∼147 fJ). Leveraging the finely tunable conductivity through tribopotential, we demonstrate a mechano-assisted artificial neural network capable of recognizing handwritten digits with an accuracy rate of approximately 88.59%. These findings underscore the significant potential of the triboelectric charge-trapping transistor in mechanical-assisted real-time interaction, energy-efficient data storage, and neuromorphic computing.

Tunable EOT Scaling Down to 0. 55 nm for HfO2-Based Gate-Stacks on Ge Substrate by In Situ H2 Plasma Treatment

Abstract We propose a continuous fabrication method for HfO2-based gate stacks on a Ge bulk p-type metal–oxide–semiconductor capacitor (pMOSCAP) with HfGeOx interfacial layer by H2 plasma treatment through in situ plasma-enhanced atomic layer deposition. The electrical characteristics showed that the proper hydrogen plasma treatment could obtain an aggressively scaled equivalent oxide thickness of approximately 0.55 nm and a relatively low gate leakage current of 8 × 10-4 A/cm2 under PMA 500C.

Multi-Level interaction network for temporal sentence grounding in videos

Temporal sentence grounding in videos (TSGV), which aims to retrieve video segments from an untrimmed videos that semantically match a given query. Most previous methods focused on learning either local or global query features and then performed cross-modal interaction, but ignore the complementarity between local and global features. In this paper, we propose a novel Multi-Level Interaction Network for Temporal Sentence Grounding in Videos. This network explores the semantics of queries at both phrase and sentence levels, interacting phrase-level features with video features to highlight video segments relevant to the query phrase and sentence-level features with video features to learn more about global localization information. A stacked fusion gate module is designed, which effectively captures the temporal relationships and semantic information among video segments. This module also introduces a gating mechanism to enable the model to adaptively regulate the fusion degree of video features and query features, further improving the accuracy of predicting the target segments. Extensive experiments on the ActivityNet Captions and Charades-STA benchmark datasets demonstrate that the proposed method outperforms the state-of-the-art methods.

High-κ Dielectric (HfO2)/2D Semiconductor (HfSe2) Gate Stack for Low-Power Steep-Switching Computing Devices.

Herein, a high-quality gate stack (native HfO2 formed on 2D HfSe2) fabricated via plasma oxidation is reported, realizing an atomically sharp interface with a suppressed interface trap density (Dit ≈ 5 × 1010 cm-2 eV-1). The chemically converted HfO2 exhibits dielectric constant, κ ≈ 23, resulting in low gate leakage current (≈10-3 A cm-2) at equivalent oxide thickness ≈0.5 nm. Density functional calculations indicate that the atomistic mechanism for achieving a high-quality interface is the possibility of O atoms replacing the Se atoms of the interfacial HfSe2 layer without a substitution energy barrier, allowing layer-by-layer oxidation to proceed. The field-effect-transistor-fabricated HfO2/HfSe2 gate stack demonstrates an almost ideal subthreshold slope (SS) of ≈61 mV dec-1 (over four orders of IDS) at room temperature (300 K), along with a high Ion/Ioff ratio of ≈108 and a small hysteresis of ≈10 mV. Furthermore, by utilizing a device architecture with separately controlled HfO2/HfSe2 gate stack and channel structures, an impact ionization field-effect transistor is fabricated that exhibits n-type steep-switching characteristics with a SS value of 3.43 mV dec-1 at room temperature, overcoming the Boltzmann limit. These results provide a significant step toward the realization of post-Si semiconducting devices for future energy-efficient data-centric computing electronics.

BCl3/Cl2 plasma etching process to fabricate a ferroelectric gate structure for device integration

Despite the significant potential of ferroelectric devices in overcoming the challenges faced by conventional high-k-based CMOS devices owing to the scaling of CMOS processes, most ferroelectric devices are not implemented in practical circuits yet. For practical application, integrating them into a circuit is essential, and the development of a reliable etching process is crucial for the integration of individual devices into circuits. Therefore, this study proposes a process for etching hafnium zirconium oxide (HZO)-based gate stacks to fabricate a gate structure and integrate HZO-based devices into circuits. First, poly-Si/TiN/HZO/TiN/SiO2 was deposited on a Si substrate and etched via Cl2 and BCl3/Cl2 plasma etchings. Cl2 plasma etching was found to be less effective, whereas BCl3/Cl2 plasma etching exhibited a higher etching rate. The optimal etching time for the BCl3/Cl2 plasma at which the entire stack was successfully removed was 50 s. Furthermore, the optimal ratio of Ar:Cl2:BCl3 that resulted in minimal damage to the Si surface was determined to be 1:1:3. These results led to the successful formation of an HZO-based gate structure and provided the potential to integrate ferroelectric devices into the circuit, thereby enabling their practical utilization.

A High Channel Mobility and a Normally‐off Operation of a Vertical GaN Metal‐Oxide‐Semiconductor Field‐Effect Transistors using an AlSiO/AlN Gate Stack Structure on m‐plane Trench Sidewall

An AlSiO/AlN‐interlayer gate stack formed on c‐plane GaN metal‐oxide‐semiconductor (MOS) devices was previously developed to enhance the interface of the gate insulator. By utilizing this gate stack structure, a channel mobility of over 200 cm2 Vs−1 on c‐plane was obtained. However, the threshold voltage was negative because of the polarization charge at the AlN/GaN interface. This study extends the application of this gate stack structure to the nonpolar m‐plane, which is obtained from a trench sidewall. Both a high channel mobility of 150 cm2 Vs−1 and a threshold voltage of 1.3 V is successfully achieved, normally‐off operation. This achievement holds significant promise for the gate structure of a GaN trench‐gate MOS field‐effect transistor (MOSFET). The limiting factor of the channel mobility is Coulomb scattering in a low electric field, whereas surface roughness scattering is dominant in a higher field.

P‐7.18: Effect of gate materials and stack structure on threshold voltage of ADS Pro TFT

P‐7.18: Effect of gate materials and stack structure on threshold voltage of ADS Pro TFT