Gate Stack Layers Research Articles

Simulation Analysis of Noise Components in NCTFET with Ferroelectric Layer in Gate Stack

Tunnel FETs (TFETs) are a strong contender for replacing conventional MOSFETs in lower power applications due to their low off-state current and sub-threshold swing being much lower than 60 mV/decade. The major trade-off is the shortcomings of TFET, which are ambipolar behaviour, low on-state current and large miller capacitance. The various novel structures of TFETs have been proposed by researchers. This work presents one such structure of heterojunction negative capacitance TFET with raised source and gate material overlapping. With the intervention of the ferroelectric layer in the gate stack of TFET, the overall performance of the device has been improved. Further AC DC analysis and electrical noise analysis are carried out for the proposed device to see the impact of improvisations being done in the structure on the input–output characteristics of the device. Synopsys TCAD tool is used to carry out the simulations at low and high frequencies. As per the results obtained, the raised source device using Ge as source material exhibits a high ION of 4.295 × 10−5 A/μm, low IOFF of 6.01 × 10−15 A/μm and sub-threshold slope of 53.75 mV/decade. The proposed device structure is having least ambipolarity and can be used in ultra-low power circuits.

Evaluation of the effect of FinFET structure parameters on electrical characteristics using TCAD modeling tools

Using TCAD modeling, the effect of changing FinFET structure parameters, such as gate stack layer sizes, rib shape, or doping levels, on the electrical characteristics of the device is investigated.

A review on emerging negative capacitance field effect transistor for low power electronics

Power consumption is the major concern for conventional CMOS based integrated circuit and systems. Since there is a scope of lowering supply voltage with steep-subthreshold swing field effect transistor (FET) devices, it has been advocated as a suitable candidate for future highly energy-efficient circuits and systems. Among all the developed and proposed low power FET devices, that possess subthreshold swing (SS) lesser than 60 mV/decade, the negative-capacitance FETs (NCFETs) have gained the major attention of scientific and academic communities. The concept of negative capacitance (NC) in FET is basically belongs to the amplify the internal potential without modification of transport phenomena. With this capability, the NCFET have achieved similar switching at lower supply voltage, VDD as compared to conventional MOSFETs. Property of achieving similar on-current (ION) lower off-current (IOFF) at lower supply voltage indicates that NCFETs help to reduce the power consumption and switching voltage. This can be achieved by slight modification of conventional CMOS devices by adding thin layer of ferroelectric (FE) layer in gate stack. This slight modification in conventional MOSFET is for the NC, which is a special feature of FE materials. FE materials having nonlinear dielectric behavior. This material has preexisting, which is switched in reverse direction when an external electric field is applied. In this paper, a detailed review of NCFET device has discussed and also compared with the Tunnel FET (TFET) and conventional MOSFET.

Substrate Bias Enhanced Trap Effects on Time-Dependent Dielectric Breakdown of GaN MIS-HEMTs

In this work, we present the substrate bias enhanced trap effects on time-dependent dielectric breakdown (TDDB) in GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) by experiment. Under different substrate biases, the shape parameter β and scale factor η of the Weibull distribution are extracted from the experimental data. A monotonical decrease in β from intrinsic breakdown to extrinsic breakdown relating to the hole-emission from the acceptor-like buffer traps with increased negative substrate biases has been observed, while η is increased at large positive substrate biases. This unexpected increase in η suggests that the donor-like buffer traps play an important role with a longer lifetime. The trap mechanisms, relating to percolation path establishment, are analyzed based on progressive breakdown (PBD). The capacitance-voltage characteristics are measured during each stress cycle confirming the hole fluence and electron injection in the gate-stack layer with different trap distributions under various substrate biases. Finally, 2-D device simulations are carried out to probe for physical insight into the traps on TDDB failure mechanisms.

A Progressive Performance Boosting Strategy for 3-D Charge-Trap NAND Flash

The growing demands of large-capacity flash-based storages have facilitated the downscaling process of NAND flash memory. However, the downscaling of traditional planar floating-gate flash memory faces several challenges. Therefore, new NAND flash technologies have been explored to provide larger capacity with low cost. Among these new technologies, the 3-D charge-trap flash is regarded as one of the most promising candidates. The 3-D charge-trap flash is composed of several gate-stack layers and vertical cylindrical channels to provide high-density and low cell-to-cell interference. Owing to the cylindrical geometry of vertical channels, the access performance of each page in one block is distinctive, and this situation is exacerbated in the 3-D charge-trap flash with the fast-growing number of gate-stack layers. In this paper, a progressive performance boosting strategy is proposed to boost the performance of 3-D charge-trap flash by utilizing its asymmetric page access speed feature. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving the access performance of 3-D charge-trap flash.

Suppression of interfacial layer in high-K gate stack with crystalline high-K dielectric and AlN buffer layer structure

The gate stack composed of a crystalline ZrO2 high-K dielectric and an AlN buffer layer treated with the remote NH3 plasma was proposed and developed. The AlN buffer layer was introduced between the crystalline ZrO2 and the Si substrate to suppress the low-K silicate interfacial layer, leading to a reduction in CET. The Jg was also suppressed by the AlN buffer layer by three orders of magnitude. In addition, the decrease of Dit could be accomplished because of the hydrogen passivation from the remote NH3 plasma used for the AlN deposition. Moreover, the remote NH3 plasma treatment on the AlN buffer layer further reduces the CET, Dit, and Jg due to deactivation of the nitrogen vacancies. Accordingly, a low CET (in accumulation region) of 1.21 nm, Dit (at mid gap) of 5.32 × 1011 cm−2 eV−1, and Jg (at flatband voltage-1V) of 1.09 × 10−5 A/cm2 were achieved in the crystalline ZrO2/AlN buffer gate stack treated with the remote NH3 plasma. The result indicated that the crystalline high-K dielectrics/AlN buffer layer is a promising gate stack to improve the sub-nanometer CET scaling.

Low Temperature Effect on Strained and Relaxed Ge pFinFETs STI Last Processes

The lower effective mass of germanium compared to silicon makes its quite attractive for future high-performance applications, since high hole mobility material is required for p-type channel devices [1]. In combination with FinFET structures, which present a strong electrostatic coupling [2], it give rises to a promising future device, Ge pFinFET. This work analyses the influence of low temperature effects on static parameters such as threshold voltage (VT), transcondunctance (gm) and subthreshold swing (SS) of strained and relaxed Ge pFinFET devices. The gate stack layer is composed of a paritally oxidized Si passivation layer, hafnium oxide (HfO2) and TiN. The temperature impact is analyzed from 200 K down to 77 K. The devices used in this work have been fabricated on a p-type silicon substrate at Imec/Belgium. There are two diffent STI last processes under evaluation. The first one is the strained channel, whereby a thin Ge layer has been grown on top of a thicker layer of SiGe relaxed buffer (SRB) on a silicon wafer. The other is a relaxed channel, where a thicker Ge layer has been grown on top of the silicon substrate. The planar device dimensions are fin width (Wfin) of 20 nm and geometric channel length (LG) of 1 µm and 4 fins in parallel. All measurements were carried out in linear operation. As the temperature is varied from 200 K down to 77 K one clearly observes that the drain current (IDS) is increased and the curves shift to more negative values, as shown in Fig. 1. The temperature reduction causes the Ge intrinsic concentration to drop, which in turns results in a lower Fermi level value and consequently a threshold voltage (VT) value shift towards positive values [3]. On the other hand, as presented in Fig. 2 the temperature effect is not strong for both relaxed and strained devices, since the VT over temperature ratio values are quite low and similar, 3.25x10-4 V/K and 3.7x10-4 V/K, respectively. The IDS improvement is associated to the carrier mobility increase with the low temperature [4]. Furthermore, the difference between the IDS levels (ΔIDS) for a strained device and relaxed one (Fig. 1) is due to the impact of the strain that boosts the hole mobility and the effect remains for different temperatures. This means that the mobility scattering mechanism is the same, as confirmed in Fig. 3, since both devices present a similar slope. In contrast, the ΔIDS cannot be observed as the strained device presents a higher capacitance equivalent thickness. Moreover, while the IDS in the ON-region raises with the temperature fall, the leakage current reduces due to the thermal activation of the carrier generation in the subthreshold region, as depicted in Fig. 4. On the other hand, the slope for both strained and relaxed devices is different, pointing out that an additional effect also plays a role on the subthreshold swing.[1] S. Takagi et al., ECS Trans., 35(3), 279 (2011).[2] T. Chiarella et al., Solid-State Electron, 54, 855 (2010). [3] A. A. Osman at el, Proc. the 4th Int. High Temp. Electron. Conf., 1998 Fourth International, p. 301 (1998). [4] J. Mitard et al., Tech. Dig., IEEE VLSI (2009), p. 82. Figure 1

Non-Silicon microelectronics: Germanium and Germanium-Tin field-effect transistors

The background and motivation of the non-silicon microelectronics, in which the non-silicon channel materials are used to realize the CMOS integrated circuits, are introduced in this paper. As the typical non-silicon microeletronic devices, Germanium (Ge) and Germanium-Tin (GeSn) metal-oxide-semiconductor field-effect transistor (MOSFET) and tunneling field-effect transistor (TFET) are reviewed. Ge and GeSn are the promising candidate materials for the realization of high mobility channel CMOS devices owing to their high carrier mobilities and easy integration on Si platform. GeSn can transit from indirect to direct bandgap material by tunning Sn composition thus achieving the high band-to-band tunneling generation rate. Theory and experimental results proved that GeSn can be used to fabricate the high performance TFETs. A series of key problems including the growth of materials, surface passivation, gate-stack layer, source-drain engineering, strain engineering, and device reliability are discussed.

Memristive behavior in a junctionless flash memory cell

We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO2 as the tunnel dielectric, Al2O3 as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits the pinched hysteresis of a memristor and in the unoptimized device, Roff/Ron ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts Roff/Ron ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 106 s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.

Impact of Gate Stack Dielectric on Intrinsic Voltage Gain and Low Frequency Noise in Ge pMOSFETs

Concerning future high-performance applications, materials such as germanium (Ge) and III/V, have been extensively studied as alternative for the channel region instead of silicon. The high mobility makes Ge a promising channel material for both low power and high performance applications of advanced devices [1]. On the other hand, gate stack engineering is challenging in Ge devices, in view of the higher density of interface states typically observed [2]. This work analyses the influence of gate stack layers (GSL) on intrinsic voltage gain and low frequency noise in planar Ge pMOSFET devices. The GSL is composed of germanium oxide (GeOx), aluminum oxide (Al2O3) and hafnium oxide (HfO2), where both Al2O3 and HfO2film thicknesses were varied. There are also two different plasma powers under evaluation. Furthermore, the analog parameters were analyzed at high temperature, ranging from 25 to 150 °C. The devices used in this work have been fabricated on a p-type silicon substrate at Imec/Belgium. There are four wafers with different dielectric composition as shown in table 1. The planar device dimensions are channel width (W) of 10 µm and channel length (L) of 130, 250, 1 and 10 µm. The low frequency noise (LFN) was measured in linear operation showing no clear impact of the gate stack processing. From the normalized noise power spectral density versus drain current it is derived that the predominant flicker noise is due to trapping by border traps in the gate stack and more specifically in the GeOx layer. Representing the square root of the input-referred voltage noise spectral density (SVG 0.5) versus Id/gmyields the flat-band value (intercept) and the mobility scattering coefficient is obtained from the slope of a linear fit in Fig. 1. Among the studied wafers (figure 2), D20 (which has the thinnest Al2O3 thickness) presents the lowest value of the intrinsic voltage gain (AV) for the channel length range studied due to the degradation of the Early voltage (VEA). Furthermore, for the other wafers no significant AV variation betweem the wafers was observed. It suggests that neither the HfO2 thickness nor the plasma power presented a relevant influence on the AVvalue. Considering that the AV for all studied wafers, except D20, present the same trend at room temperature (figure 2), wafer D18 was chosen to investigate the analog basic parameter performances from 25 to 150 °C. In figure 3 is can be seen that the transconductance (gm) is strongly degraded as the temperature increases due to mobility degradation. On the other hand, the output conductance (gD) presented almost no difference with the temperature rise. Figure 4 focuses on the AV as a function of temperature. It can be seen that AVdecreases 5 dB as the temperature increases from 25 to 150 °C, due to the influence of the gm reduction. [1] J.-H. Han et al., Microelectronic Engineering, v.109, p. 266–269, 2013. [2] V.P.-H Hu et al.,TED, v.60, I. 10, p. 3596 – 3600, October, 2013. [3] S. Takagi et al., Microelectronic Engineering, v.109, p. 389–395, 2013. Figure 1

Impact of Gate Stack Dielectric on Intrinsic Voltage Gain and Low Frequency Noise in Ge pMOSFETs

This paper presents an experimental analysis of the gate stack dielectric influence on low frequency noise and intrinsic voltage gain (AV) in planar germanium pMOSFETs with a HfO2/Al2O3 gate stack. The Av is studied not only at room temperature, but also from 25 to 150 °C. It is observed that neither the HfO2 - thickness nor the plasma oxidation power have a significant impact on the noise power spectral density and intrinsic voltage gain (AV). In contrast, the thinner Al2O3 - layer is more susceptible to any damage during the fabrication processes, which increases the interface state density (NIT) between the Ge surface and gate stack layer, resulting in a device performance degradation. Furthermore, from high temperature point of view, the AV is predominantly dominated by the carrier mobility degradation, which reduces the transconductance.

Bound states within the notch of the HfO2/GeO2/Ge stack

A model is presented to allow calculation of the bound states in the conduction band notch at the interface between the interfacial native GeO2 and high-κ dielectric layer in a Ge MOSFET gate stack. The notch represents a potential charge trapping site, which can induce threshold voltage instability. The model is applied to a three-dimensional structure, and the number of electrons or average occupancy of confined electrons in the notch is calculated. The effect of device physical and electrical parameters on the number of bound states and average occupancy of states in the notch is discussed. The significance of the confined charge in the notch and its effect on the threshold voltage shift in an 8-nm node Ge MOSFET is investigated. The main conclusion is that charge storage in this notch is insignificant at the relevant technology node.

Evaluation and modeling of lanthanum diffusion in TiN/La2O3/HfSiON/SiO2/Si high-k stacks

In this study, TiN/La2O3/HfSiON/SiO2/Si gate stacks with thick high-k (HK) and thick pedestal oxide were used. Samples were annealed at different temperatures and times in order to characterize in detail the interaction mechanisms between La and the gate stack layers. Time-of-flight secondary ion mass spectrometry (ToF-SIMS) measurements performed on these samples show a time diffusion saturation of La in the high-k insulator, indicating an La front immobilization due to LaSiO formation at the high-k/interfacial layer. Based on the SIMS data, a technology computer aided design (TCAD) diffusion model including La time diffusion saturation effect was developed.

The Improvement of High-$k$/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure

The impact of the Si cap/SiGe layer on the Hf-based high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> /metal gate SiGe channel pMOSFET performance and reliability has been investigated. We proposed an optimized strain SiGe channel with a Si cap layer to overcome the Ge diffusion and confine the channel carriers in the strained SiGe layer without the formation of a significant parasitic channel at the interface. With this optimized Si/SiGe stack channel, a high-performance Hf-based high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> /metal gate SiGe pMOSFET can be obtained with an appropriate <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> (~0.3 V), low <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> hysteresis ( <; 5 mV), and better I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> - I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> rolloff, and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> stability. By the way, the related interface trap density in the high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> gate stack layer can also be reduced, thus improving the device's NBTI and HCI stressing-induced reliability.

Investigation of 3-D stacked NAND flash memory cell string having 4F 2 cell size and shield layer for suppressing cross-talk

A new 3-D stacked NAND flash memory was proposed and key characteristics of the memory were investigated using extensive device simulation. To simplify gate stack etch process, Si/SiGe selective etch process was adopted. By applying silicon trench etch process, threshold voltage ( V TH) variation in a bit-line can be reduced and the number of vertical control-gate (CG) stacks can be increased as a result. In the trench between CG stacks, gate stack, poly-Si bodies, back-side oxide (BOX) and shield layer are formed. The 3-D stacked NAND flash memory structure without shield layer showed significant cross-talk between adjacent bodies. By adopting shield layers in the trenches, the cross-talks were completely removed. We designed BOX thickness which guarantees reasonable DIBL (Drain-Induced-Barrier-Lowering) and SS (Sub-threshold Swing). The V TH shift of ∼1.8 V was observed with the Q nit of 6 × 10 12 cm −2.

Modelling of Layers and Traps in High-Κ Gate Stacks and Energy Band and Equivalent Circuit Representations

Five layers - two bulk and three chemically graded layers - have been identified to constitute the high-K gate stack; the bulk layers being the intermediate oxide and the high-K layers; the three chemically graded layers being the silicon/intermediate-oxide, the intermediate-oxide/high-K, and the high-K/metal-oxide interfacial layers. Energy band diagrams across the silicon space-charge, the five gate stack, and the metal layers, have been modeled, in which graded band-gap in the chemically graded layer, and the effects of the electric fields and image force barrier lowering have been considered. Response of traps in all the five layers of the gate stack to an applied small signal has been modeled, including the profile of the quasi-Fermi function in the gate stack. Relations for the potentials across the five gate stack layers have been formulated. Finally, small-signal equivalent circuit representations have been developed for the entire gate stack and the silicon space-charge layer.

Gate Oxide Reliability Characterization of Tungsten Polymetal Gate with Low-Contact-Resistive WSix/WN Diffusion Barrier in Memory Devices

Gate oxide reliability characteristics using different diffusion barrier metals for a tungsten polycrystalline silicon (poly-Si) gate stack were investigated in detail. The insertion of a thin WSix layer in a tungsten poly gate stack could effectively relieve the mechanical stress of a gate hardmask nitride film during a post thermal process, which contributes to better gate oxide reliability and the stress-immunity of the transistor. This insertion could also prevent the formation of a Si–N inter-dielectric layer, which could lower the contact resistance between poly and tungsten effectively. A W/WN/WSix/poly gate stack could be a promising candidate for a future W poly gate that shows reliable high-speed characteristics in dynamic random access memory applications.

Understanding of the thermal stability of the hafnium oxide/TiN stack via 2 “high k” and 2 metal deposition techniques

In this work we evaluate the impact of the gate stack layers deposition technologies and their combination on the thermal stability of the stack with respect to EOT vs leakage figure of merit. Two HfO 2 deposition technologies have been used: ALCVD and AVD (for Atomic Vapor Deposition); and two TiN deposition technologies have been evaluated: CVD and PVD. As a result, it appears that stack stability after a 1050 °C spike anneal can be achieved by combination of AVD HfO 2 and PVD TiN. Anyway a trade-off in terms of mobility degradation using this metallic layer deposition technique is still present.

Formation of Germanium Nanocrystals Embedded in a Silicon-Oxygen-Nitride Layer

The formation of germanium nanocrystals embedded in silicon-oxygen-nitride with distributed charge storage elements is proposed. A large memory window was observed due to isolated Ge nanocrystals in the gate stack layer. The Ge nanocrystals were nucleated after a high-temperature oxidized layer. The Ge nanocrystals embedded in the stack layer exhibited nonvolatile memory characteristics with the obvious threshold voltage shift under a bidirectional voltage sweep. Also, the manufacturing technology using the sequent high-temperature oxidation of the a-Si layer and the direct oxidation of the layer is proposed, respectively, for the formation of a blocking oxide layer to enhance the performance of nonvolatile memory devices. The reliability characteristics, including retention time and endurance, are also advisable for the application of nonvolatile memory device.

Formation of germanium nanocrystals embedded in silicon-oxygen-nitride layer

The formation of germanium nanocrystals embedded in silicon-oxygen nitride with distributed charge storage elements is proposed in this work. A large memory window is observed due to isolated Ge nanocrystals in the SiON gate stack layer. The Ge nanocrystals were nucleated after high temperature oxidized SiGeN layer. The nonvolatile memory with the Ge nanocrystals embedded in SiON stack layer exhibits 4V threshold voltage shift under 10V write operation. Also, the manufacture technology using the sequent high-temperature oxidation of the a-Si layer acting as the blocking oxide is proposed to enhance the performance of nonvolatile memory devices.