Suppression of interfacial layer in high-K gate stack with crystalline high-K dielectric and AlN buffer layer structure

Abstract

The gate stack composed of a crystalline ZrO2 high-K dielectric and an AlN buffer layer treated with the remote NH3 plasma was proposed and developed. The AlN buffer layer was introduced between the crystalline ZrO2 and the Si substrate to suppress the low-K silicate interfacial layer, leading to a reduction in CET. The Jg was also suppressed by the AlN buffer layer by three orders of magnitude. In addition, the decrease of Dit could be accomplished because of the hydrogen passivation from the remote NH3 plasma used for the AlN deposition. Moreover, the remote NH3 plasma treatment on the AlN buffer layer further reduces the CET, Dit, and Jg due to deactivation of the nitrogen vacancies. Accordingly, a low CET (in accumulation region) of 1.21 nm, Dit (at mid gap) of 5.32 × 1011 cm−2 eV−1, and Jg (at flatband voltage-1V) of 1.09 × 10−5 A/cm2 were achieved in the crystalline ZrO2/AlN buffer gate stack treated with the remote NH3 plasma. The result indicated that the crystalline high-K dielectrics/AlN buffer layer is a promising gate stack to improve the sub-nanometer CET scaling.