Gate-source Capacitance Research Articles

Analysis of source second-harmonic-controlled wideband extended series of continuous modes power amplifiers

In this article, an in-depth analysis is presented for the first time by considering the impact of the input nonlinearity caused by gate-source capacitance (Cgs) on the performance and broadband design of extended series of continuous modes (ESCMs) power amplifiers (PAs). The conclusion of the analysis shows that the drain current waveforms of ESCMs will be altered, resulting in the overlapping region with the voltage waveform and theoretical efficiency becoming a function of the nonlinear factor γ under the influence of input nonlinearity. As a result, compared to the traditional ESCMs PAs, the introduction of nonlinear factor γ has given rise to a wider load design space and source second-harmonic manipulation space, which can achieve bandwidth expansion while reducing the design complexity of input and output matching networks. Subsequently, this conclusion was verified by using a commercially available 10W gallium nitride (GaN) device from Cree to design wideband high-efficiency PAs. The measured results show that in the target frequency band from 0.55 to 3.55 GHz, a drain efficiency of 60.5%–71.5 % and a gain of 9–12 dB can be obtained at a saturated output power of 39–42 dBm.

Thermal management and switching performance of β-Ga2O3 vertical FinFET with diamond-gate structure

In this paper, a beta-phase gallium oxide (β-Ga2O3) vertical FinFET with diamond-gate has been studied by Silvaco-ATLAS simulation. The diamond-gate structure achieves adjustable pin (p-insulator-n) junction owing to the diamond-SiO2-Ga2O3 heterostructure. This design also enhances heat dissipation by virtue of the high thermal conductivity of the diamond. Compared to conventional FinFETs, the diamond-gate FinFET (DG-FinFET) reduces the static operating temperature rise by around 17.30%. Additionally, due to its greater heat dissipation capacity, DG-FinFETs provide a 5.84% increase in current density at 1 kA cm−2 current density level. The structural changes in the diamond-gate also result in a significant reduction in the gate-source capacitance (C GS). At 1 MHz operating frequency and the same gate voltage, DG-FinFETs have 69.29% less gate-source charge (Q GS), 70.80% less charge/discharge delay time, 73.70% less switching loss, and 57.15% less conduction loss. Overall, the simulation and analysis presented in this work indicate a promising advancement of the DG-FinFET structure in high-power and rapid switching applications.

TCAD Simulation of Novel Recess Gate Common Drain Dual Channel AlGaN/GaN HEMT for Small Signal Performance

In this paper, DC and RF characteristics of Recess Gate Common Drain Dual Channel (CDDC) AlGaN/GaN HEMT have been investigated. The performance of the device in terms of the various figures of merits including gate-source capacitance, drain current, transconductance, and channel conductance has been studied for different recess depths. The threshold voltage is found to decrease by shifting right with increasing recess depth, even though with deeper recess, transconductance increases. It has also been observed that the device operates in enhancement mode with a minimum gate recess depth of 15 nm or more. With increasing recess depth, the drain current starts decreasing due to an increase in channel resistance. Use of recess technology with Al graded barrier layer enhances the performance in terms of gm, ft, and fmax which are 0.003 S, 23, and 46 GHz, respectively, but utilizing gate recess technology alone in CDDC HEMT further enhances device performance and the maximum gm, ft, and fmax are 0.0442 S, 28.43, and 59.21 GHz. The CDDC HEMT retain its advantage for specific applications including PA, LNA, and RF switch with optimized gate recess and graded barrier layer parameters.

Polarized Coulomb field scattering in LaAlO3/SrTiO3 heterojunction field-effect transistors

LaAlO3/SrTiO3 heterojunction field-effect transistors (HFETs) were fabricated. Using a combination of measured current–voltage (I–V) output curves and gate-source capacitance–voltage (C–V) characteristic curves for the fabricated LaAlO3/SrTiO3 HFETs, and considering scattering mechanisms for longitudinal optical phonon, interface rough, electron-electron (E-E), acoustic phonon, and polarized Coulomb field (PCF), the channel electron mobility of LaAlO3/SrTiO3 HFETs has been calculated and analyzed. The results showed that PCF scattering is a significant carrier scattering mechanism in LaAlO3/SrTiO3 HFETs. The heterostructure of the LaAlO3/SrTiO3 system has strong polarization characteristics. This paper is the first to demonstrate that PCF scattering is a significant carrier scattering mechanism in LaAlO3/SrTiO3 HFETs, following GaN HFETs, thus demonstrating that LaAlO3/SrTiO3 HFETs also have PCF scattering effect.

Investigation of junction capacitance in Zener tunnelling tunnel diode partially depleted silicon on insulator

Junction capacitance variation in Zener Tunnelling Tunnel Diode Partially Depleted Silicon On Insulator (ZT-TDPDSOI), due to the geometry effects of source and drain are discussed in this paper. Electric field profile and a capacitance equivalent circuit are used to reveal the gate-source capacitance dependence on the P+ region in ZT-TDPDSOI. It is demonstrated how the inclusion of a P+ region below the source/drain region impacts the gate substrate capacitance using the hole concentration and valence band energy at the source channel junction. A decrease of 42 % was noted in gate-substrate capacitance for a P+ doping of 2*1020/cm3 and thickness of 0.05 μm under fixed biased condition. The use of the trapezoidal approximation is also suggested as an extraction technique for the depletion width.

Impact of Gaussian Traps on the Characteristics of L-shaped Tunnel Field-effect Transistor

Background: Internet of Things (IoT) applications require high-performance TFET devices that can be efficiently integrated with the cyber world and physical world. Objectives: The impact of introducing Gaussian traps in hetero-junction tunneling-field-effecttransistors (TFET) with an L-shaped gate is presented. Methods: The 2-D TCAD study of different characteristics, like input, output characteristics, and noise spectral density with trap and without trap, has been performed. Results: The simulation results showed that in L-shaped TFET (L_TFET), the high on-current of 1.93×10-5 A/μm, low off-current/leakage current of 1.09×10-13 A/μm, and steep sub-threshold slope (SS) of 24 mV/dec without traps and on-current of 8.46×10-6 A/μm, off-current of 2.86×10- 11 A/μm, and degraded SS with traps are observed. They also indicated that the presence of traps reduces gate-drain capacitance (Cgd), while gate-source capacitance (Cgs) remains unaffected. In addition, in L_TFET, the drain current noise spectral density (SID) of 7.63 E-21 (A2/Hz) at LF and 2.69 E-26 (A2/Hz) at HF while the noise voltage spectral density (SVG) of 7.33 E-4 (V2/Hz) at LF and 2.59 E-15 (V2/Hz) at HF without traps have been investigated in this study. The inverse dependence of drain current noise spectral density on frequency has been observed to lower the effect of noise at HF. Conclusion: It can be concluded that the proposed L_TFET device is free from ambipolarity conduction and can be well-suited for low-power applications.

Design and Analysis of a Wideband K/Ka-Band CMOS LNA Using Coupled-TL Feedback

We demonstrate a low power (PD) 22-33 GHz CMOS low-noise amplifier (LNA) with low noise-figure (NF) and small group-delay (GD) variation for 28 GHz 5G system. Body-selfforward-bias (BSFB) technique, i.e., connection of transistor’s body to drain via body resistance, is used for threshold and supply voltage reduction, and substrate leakage suppression. Gain and NF enhancement at the same PD is achieved because lower VDD and higher transconductance (due to larger bias current) are used. Current-reused topology is used for low PD. Coupled transmission -line (TL) feedback neutralization technique is proposed for further gain and NF enhancement. The feedback from output (drain) to input (gate) via gate-drain capacitance (Cgd) can be cancelled by the feedback from drain (through source) to gate via the coupled TL and gate-source capacitance (Cgs). The LNA consumes 12.2 mW and achieves S21 of 16 dB, 3 dB bandwidth (f3dB) of 11 GHz (22-33 GHz), minimum NF (NFmin) of 2.5 dB, average NF (NFavg) of 3.1 dB, and GD variation of ±6 ps for 22-33 GHz, and figure-of-merit (FOM) of 91.7 GHz. Moreover, the LNA achieves input third-order intercept point (IIP3) of -3 dBm. The NF and FOM are one of the best results ever reported for LNAs with f3dB greater than 7 GHz and PD lower than 15 mW.

Design of a Nonlinear Model of a Pseudomorphic 0.15 μm рHEMT AlGaAs/InGaAs/GaAs Transistor

This paper studies the design of a nonlinear model of AlGaAs/InGaAs/GaAs рHEMT microwave-frequency range transistors with a gate length of 0.15 µm using parametric analysis methods. In the calculations, not only nonlinear current sources but also the dependences of the nonlinear gate-source and gate-drain capacitances on voltages are studied. It is shown that the proposed model makes it possible to describe the IV characteristics of the studied device adequately in the range of drain currents from 0 to 100 mA and the frequency range from 5 to 45 GHz. The error of the model does not exceed 3%.

A New Analytical Large-Signal Model for Quasi-Ballistic Transport in InGaAs HEMTs Accommodating Dislocation Scattering

A surface-potential-based analytical large-signal model, which is applicable to both ballistic and quasi-ballistic transport in InGaAs high electron mobility transistors, is developed. Based on the one-flux method and a new transmission coefficient, a new two-dimensional electron gas charge density is derived, while the dislocation scattering is novelly taken into account. Then, a unified expression for Ef valid in all the regions of gate voltages is determined, which is utilized to directly calculate the surface potential. The flux is used to derive the drain current model incorporating important physical effects. Moreover, the gate-source capacitance Cgs and gate-drain capacitance Cgd are obtained analytically. The model is extensively validated with the numerical simulations and measured data of the InGaAs HEMT device with the gate length of 100 nm. The model is in excellent agreement with the measurements under I-V, C-V, small-signal conditions, and large-signal conditions.

Design of a Nonlinear Model of a Pseudomorphic 0.15 μm рHEMT AlGaAs/InGaAs/GaAs Transistor

This paper studies the design of a nonlinear model of AlGaAs/InGaAs/GaAs рHEMT micro-wave-frequency range transistors with a gate length of 0.15 μm using parametric analysis methods. In the cal-culations, not only nonlinear current sources but also the dependences of the nonlinear gate-source and gate-drain capacitances on voltages are studied. It is shown that the proposed model makes it possible to describe the IV characteristics of the studied device adequately in the range of drain currents from 0 to 100 mA and the frequency range from 5 to 45 GHz. The error of the model does not exceed 3%

Optimization of Channel Structures in InP HEMT Technology for Cryogenic Low-Noise and Low-Power Operation

We report the impact from channel composition on the cryogenic low-noise performance at low dc power for a 100-nm gate-length InGaAs-InAlAs-InP high-electron mobility transistor (HEMT). Two indium (In) channel compositions, 65% and 80%, were studied by dc and RF characterization at 300 and 5 K. For the cryogenic low-noise optimization, it was important to increase the transconductance to gate–source capacitance ratio in the weak inversion region implying that a higher maximum cutoff frequency in the HEMT does not guarantee lower noise. The HEMT noise performance was obtained from noise measurements in a hybrid three-stage 4–8-GHz ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{C}$</tex-math> </inline-formula> -band) low-noise amplifier (LNA) down to 300- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W dc power dissipation. While the HEMT LNA noise performance for both the channel compositions at 300 K was found to be comparable, the HEMT LNA at 5 K with 65% In channel showed a minimum noise temperature of 1.4 K, whereas the noise temperature in the HEMT LNA with 80% In channel HEMTs increased to 2.4 K. The difference in the noise became more pronounced at reduced dc power dissipation. The ultralow dc power of 300 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W demonstrated for a cryogenic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{C}$</tex-math> </inline-formula> -band LNA with an average noise temperature of 2.9 K and 24-dB gain is of interest for future qubit read-out electronics at 4 K.

Improved Current-Sharing Imbalance Control Model Based on Magnetic Ferrite Inductance and a Gate Drive Circuit

The dynamic and static imbalance of parallel current sharing has held the concern of researchers in view of the variation in multiple parasitic parameters on high-frequency parallel switching mode power supply (SMPS). The joint simulations and suppression experiments on the parallel current-sharing imbalance of various parasitic parameters are investigated on the improved dual-pulse detection circuit platform to determine the method of detecting the parallel current-sharing imbalance ratio using the sum of the differential magnetic flux. An improved model of current-sharing imbalance control is presented consisting of magnetic ferrite inductance and a gate drive circuit. The main concerns are the suppression performance of drain, gate, and source parasitic inductance, gate–source capacitance, driving time and voltage, gate resistance, and delayed forward/reverse driving signals on the ratio of parallel current-sharing imbalance, respectively. The improved model effectively reduces the parallel current-sharing imbalance ratio by more than 5% and 2–4.2%, compared with using a gate drive circuit alone and using magnetic ferrite inductance solely.

Влияние ёмкости посадочного места транзистора на его устойчивость к воздействию электростатического разряда

The paper presents an assessment of the resistance of field-effect transistors to the effects of an electrostatic discharge. It is made for two field-effect transistors of different types of conductivity, IRFZ46N and IRF4905 SPbF, in different TO-220 and TO-263 packages, with and without taking into account the seat capacitance. Analytical and quasi-static models of transistor package seats are presented, and with their help, an analysis of intrinsic and mutual capacitances is carried out with and without allowance for the solder layer. The analysis showed that the solder layer on the transistor electrodes increases the gate-source and drain-source capacitance by 1.7 times for the IRFZ46N transistor and by 2.2 times for the IRF4905 SPbF transistor. Based on the calculated capacitances, a circuit model of the transistor was created, taking into account the packages and seat with a solder layer. A circuit and a model are presented for assessing the resistance of transistors to the effects of an electrostatic discharge in a circuit simulator. An analysis of the results of simulating and experiments showed that the seat capacitance, taking into account the solder layer, has a significant effect on the breakdown voltage of the gate dielectric of the transistor when exposed to an electrostatic discharge. It is shown that the critical amplitudes of the electrostatic discharge voltage for the performance of the IRFZ46N transistors in the TO-220 package and IRF4905 SPbF in the TO-263 package, taking into account the capacitance of the seat, are 3.05 and 4.75 kV, and without taking into account these values are higher by 0.2-0.25 kV. A comparison of the simulation and experimental results showed a difference of no more than 2%.

Analytically modeling electric field of shielded gate trench metal-oxide-semiconductor field effect transistor

Shielded gate trench metal-oxide-semiconductor field effect transistor (SGT-MOSFET) introduces a longitudinal shielding gate connected to the source inside the body, which can assist in depleting the drift region. Its principle of withstanding voltage is different from that of the vertical U-groove MOSFET (VUMOSFET). The SGT-MOSFET will generate two electric field peaks inside the body, which will further optimize the electric field strength distribution of the device and increase the breakdown voltage of the device. Therefore, SGT-MOSFET has not only the advantages of low conduction loss of CCMOSFET, but also lower switching loss. The effects of structural parameters such as the width of the mesa, the thickness of the field oxygen, the depth of the trench and the doping concentration on the electric field strength distribution of SGT-MOSFET are not independent of each other. The more the parameters, the more complex the correlation of their effects on the electric field strength distribution is. In this paper, we take 110V SGT-MOSFET as a research object. Through numerical simulation, theoretical analysis and analytical modeling, the principle of withstanding voltage for different structures and the correlation between structural parameters and electric field strength distribution are studied. The analytical model of the electric field related to various structural parameters of the device is established, which provides a theoretical basis for the design of the device structure. The analytical model of electric field under low current is modified by introducing avalanche carriers, so that the modified analytical results can better match the simulation results. Through the modified electric field analysis model, the field oxygen thicknessin an optimal electric field is 0.68 µm . Comparing with the product of SGTMOSFET with 0.58 µm field oxygen thickness, at the optimal field oxygen thickness of 0.68 µm, the on-resistance of the device is reduced because the on-area of the device is increased; the electric field distribution is more uniform, so the device breakdown voltage increases; the gate-source capacitance decreases and the gate-drain capacitance is almost no change, so the gate-source charge decreases and the gate-drain charge is almost no change, while the total gate charge decreases. As a result, the optimal value parameter FOM&lt;sub&gt;1&lt;/sub&gt; of the device is increased by 18.9%, and the optimal value parameter FOM&lt;sub&gt;2&lt;/sub&gt; is reduced by 8.5%. Therefore, the static and dynamic characteristics of the device are significantly promoted, and the performance of the corresponding products is greatly improved.

Diminish Short Channel Effects on Cylindrical GAA Hetero-gate Dielectric TFET using High-Density Delta

The examined work elucidates a novel concept on Gate All Around (GAA) hetero dielectric gate-cylindrical tunnel field-effect transistor (TFET) to reduce SCEs. In this paper, a hetero dielectric gate (HeG) integrated with Silicon-Germanium (Si-Ge) substrate material is proposed along with a novel placement of a high-density delta (HDD) layer across the source–channel junction to achieve high ION of 1.12 × 10−4 A/µm and robust IOFF of 9.7 × 10−17 A/µm at Vgs = 1.2 V with steepest subthreshold swing (SS) of 55 mV/decade. Designing and computation of the proffered structure have been done with the computer-aided design (TCAD) 3D device computation software. The systematic investigation in terms of AC and DC parameters, such as ON-current, OFF-current, Miller Capacitances (Gate-Drain Capacitance (Cgd)) and Gate-Source Capacitance (Cgs), are examined. Hetero-gate dielectric Cyl-TFET with high-density delta (HDD) is superior to other conventional structures. The result outcomes included a trap analysis while incorporating the hot charge carriers inside the oxide for improved device reliability. Furthermore, a low Cgd of 58fF and high Cgs of 6.6fF at Vds = 0.3 V have been achieved.

Improved 4H–SiC MESFET with bulgy channel

This paper proposes an improved 4H–SiC metal semiconductor field effect transistor with a bulgy channel (BC-MESFET) whose gate-source and gate-drain drift regions are shifted downward 0.1 μm relative to the channel below the gate. By introducing recesses at both ends of the metal gate, both the DC and AC characteristics of the structure have been greatly improved. The simulation results show that the saturation current of BC-MESFET is 30% higher than that of DR-MESFET, and the breakdown voltage is 78% higher. Therefore, the maximum output power density has a significant increase of 137%. In terms of RF, since the gate-source capacitance of the BC-MESFET structure is 31% lower than that of the DR-MESFET, its characteristic frequency is also improved by 18%. In this paper, aiming at high power added efficiency (PAE), the bump height H of the buffer layer under the lower gate is optimized, and a structure with 25% higher PAE than DR-MESFET is obtained.

The Second Source Harmonic Optimization in Continuous Class-GF Power Amplifiers

In this letter, the second source harmonic in continuous-mode class GF (CCGF) is optimized to flatten the power amplifier’s (PA) frequency response over a wideband. A new design space is explored by considering the effects of controlling the input nonlinearity of the gate–source capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {gs}}$ </tex-math></inline-formula> ) on the drain current waveforms under continuous-mode drain voltage waveforms. A wideband CCGF PA is designed and fabricated using a commercial 10-W gallium nitride (GaN) device and low-temperature co-fired ceramic (LTCC) technology. Results of the measurement show a flat frequency response from 3.3 to 4.3 GHz with variations less than ±0.4 dB for 40 dBm output power, and 17 dB large signal gain at 3-dB compression point. A drain efficiency of 66 ± 2% is achieved over the entire bandwidth.

Применение нейронных сетей при построении нелинейных моделей полевых транзисторов

The nonlinear model of a field-effect transistor based on the mathematical apparatus of the theory of artificial neural networks was developed. The main feature of this model is the possibility of training neural networks used to approximate the current-voltage characteristic and the gate-drain and gate-source capacitances of a nonlinear transistor model by using optimization algorithms built into popular microwave CAD systems. This makes it possible to use the well-known advantages of neural networks in the problems of function approximation to increase the reliability of the results of non-linear modeling of microwave devices based on field-effect transistors.

The effect of nonideal boundary condition on instability of THz plasma waves in quantum field-effect transistors

The instability of THz plasma waves propagating along a channel of field-effect transistors opens up a new mechanism of emission of THz waves. In this work, we investigate the instability of THz plasma waves in field-effect transistors in the presence of quantum effects and nonideal boundary condition at the source and the drain by using the quantum hydrodynamic model. The results show that the THz plasma waves will be unstable when the gate–source capacitances are larger than gate–drain capacitances and the instability increment can be increased by increasing gate–source capacitances or decreasing gate–drain capacitances. The results of this work give nano-field-effect transistors an advantage in achieving real THz oscillations.

A novel 4H–SiC MESFET with P-type doping zone and recessed buffer layer

Based on the double recessed 4H–SiC metal semiconductor field effect transistor (DR-MESFET) structure, a new 4H–SiC MESFET with p-type doping zone in drain drift region and recessed buffer layer under the source drift region (PDRB-MESFET) is proposed in this paper. The simulation results show that the breakdown voltage of this novel structure is improved by 63.76% compared with that of DR-MESFET. Thus, the maximum output power density of the device is increased by 72.85%. As for RF, the cutoff frequency decreases by 4.42% due to the increase of gate source capacitance, and RF performance deteriorates slightly. But in general, it is meaningful to exchange a slight decline in RF performance for a significant improvement in DC performance. The length and width of the p-type doping region are optimized and the optimal size of the p-type doping region is obtained.