Investigation of junction capacitance in Zener tunnelling tunnel diode partially depleted silicon on insulator

Abstract

Junction capacitance variation in Zener Tunnelling Tunnel Diode Partially Depleted Silicon On Insulator (ZT-TDPDSOI), due to the geometry effects of source and drain are discussed in this paper. Electric field profile and a capacitance equivalent circuit are used to reveal the gate-source capacitance dependence on the P+ region in ZT-TDPDSOI. It is demonstrated how the inclusion of a P+ region below the source/drain region impacts the gate substrate capacitance using the hole concentration and valence band energy at the source channel junction. A decrease of 42 % was noted in gate-substrate capacitance for a P+ doping of 2*1020/cm3 and thickness of 0.05 μm under fixed biased condition. The use of the trapezoidal approximation is also suggested as an extraction technique for the depletion width.