Gate Series Resistance Research Articles

A study on GaN-based high-efficiency class E power amplifier circuits at medium-low frequencies

Abstract In this paper, a high-power amplifier is designed to address the challenges of low transmission power and poor efficiency in wireless energy transmission technology at low frequencies. The design is based on a class E power amplifier circuit. The theoretical analysis is conducted to determine transistor selection and the static DC operating point. Load traction technology is employed to match the load impedance of the power amplifier, ensuring highly efficient and unified power additional efficiency, and output power. To enhance system stability and feedback compensation, gate series resistance and parallel capacitors are incorporated. Simulation results demonstrate that the designed power amplifier achieves an output power of 48 dBm with a power additive efficiency (PAE) of 85%. Furthermore, the third-order intermodulation component reaches 70 dBm, indicating concentrated output energy and high linearity in the amplifier system. Experimental results validate the consistency between theoretical analysis and model simulation, confirming the stability of the designed power amplifier circuit, and successfully achieving energy-efficient, high-power transmission.

Low-resistive gate module for RF GaN-HFETs by electroplating

This paper presents a novel approach for reducing the gate resistance (R g) of K and Ka-band GaN HFETs with 150 nm gate length through a new gate metallization technique. The method involves increasing the gate cross-section via galvanic metallization using FBH’s Ir-sputter gate technology, which allows an increase in gate metal thickness from the current 0.4 μm to approximately 1.0 μm for the transistors under investigation. This optimization leads to a substantial 50% reduction in gate series resistance, resulting in significant improvements in the RF performance. Specifically, the devices achieve 20% higher output power density and 10% better power-added efficiency at 20 GHz and V ds = 20 V. The decreased gate resistance enables new degrees of freedom in design, such as longer gate fingers and/or shorter gate lengths, for more efficient power cells operating in this frequency range.

Estimation of doping in junctionless transistors through dc characteristics

In this work, a new technique has been developed to extract the doping (Nd) of a junctionless (JL) transistor using dc analysis i.e. transfer characteristics. The proposed method utilises the evaluation of bulk mobility (μbulk) by averaging the values of transconductance (gm) between the limits of threshold (Vth) and flatband (Vfb) voltages of a junctionless device to account for bulk conduction, which can be subsequently used to extract the doping from the volume current. Results show that the extracted doping values are very close to the doping used in the simulations. The methodology is applied to planar (single gate and double gate) as well as non-planar i.e. triple gate and cylindrical nanowire devices. Impact of gate length downscaling and series resistance is also investigated. The validity of the developed approach to predict the doping is also verified through the experimental data published in the literature. The work showcases the potential of a new and relatively simpler approach to estimate the doping of a junctionless transistor by utilising dc characteristics and avoiding the capacitance measurements that often require careful de-embedding techniques.

Short channel effects in graphene-based field effect transistors targeting radio-frequency applications

Channel length scaling in graphene field effect transistors (GFETs) is key in the pursuit of higher performance in radio frequency electronics for both rigid and flexible substrates. Although two-dimensional (2D) materials provide a superior immunity to short channel effects (SCEs) than bulk materials, they could dominate in scaled GFETs. In this work, we have developed a model that calculates electron and hole transport along the graphene channel in a drift-diffusion basis, while considering the 2D electrostatics. Our model obtains the self-consistent solution of the 2D Poisson’s equation coupled to the current continuity equation, the latter embedding an appropriate model for drift velocity saturation. We have studied the role played by the electrostatics and the velocity saturation in GFETs with short channel lengths Severe scaling results in a high degradation of GFET output conductance. The extrinsic cutoff frequency follows a scaling trend, where the index fulfills The case corresponds to long-channel GFETs with low source/drain series resistance, that is, devices where the channel resistance is controlling the drain current. For high series resistance, decreases down to and it degrades to values of because of the SCEs, especially at high drain bias. The model predicts high maximum oscillation frequencies above 1 THz for channel lengths below 100 nm, but, in order to obtain these frequencies, it is very important to minimize the gate series resistance. The model shows very good agreement with experimental current voltage curves obtained from short channel GFETs and also reproduces negative differential resistance, which is due to a reduction of diffusion current.

Ultra-Thin, High Quality HfO2 on Strained-Ge MOS Capacitors with Low Leakage Current

Strained-Ge is a promising channel material for future CMOS nodes due to its very high hole mobility [1] and compatibility with existing processes. In comparison to Si, high quality dielectric interfaces for Ge are challenging due to the lack of an ideal native oxide. In this work, for the first time, we show an extremely-scaled (EOT < 5 Å), high quality dielectric on s-Ge. CV measurements of a MOS capacitor structure show areal capacitance scaling, little hysteresis, and low gate leakage current (< 0.2 A/cm2).The epitaxial structure (shown in Fig. 1(a)) was grown by low-pressure CVD, and the s-Ge layer is compressively strained (2.3% biaxial) due to the lattice mismatch with the relaxed Si0.55Ge0.45 virtual substrate. The epitaxial wafer was cleaved into pieces, and a 5-minute 1:10 (HCl:H2O) clean was performed prior to atomic layer deposition (ALD) of 1 minute O3/~3 nm HfO2 (both at 250 °C), followed by ~10 nm of TiN at 300 °C. After ALD, Al contacts were sputtered and patterned followed by a 30-minute forming gas anneal at 450 °C. The final MOS capacitor structure (Fig. 1(a)) reflects the loss in the s-Ge due to the HCl clean and O3 oxidation.CV measurements of a 100×100 µm MOS capacitor show a CET of 8.6 Å (Fig. 2). Large frequency dispersion exists for frequencies > 50 kHz due to large series resistance likely caused by a 500 meV valence band offset [2] between s-Ge and Si0.55Ge0.45 (Fig. 1(b)). The IV measurements (Fig. 3) show small gate leakage current (< 0.2 A/cm2), which translates to IG < 20 pA/µm for LG = 10 nm, well below ITRS requirements [3].Quasistatic one-dimensional self-consistent coupled Poisson-Schrödinger electrostatic simulations were performed in order to extract EOT. A strain-dependent 6×6 k∙p Hamiltonian (with deformation potentials from [2]) was used to calculate hole quantization in the s-Ge layer. In accordance with [4], a 2.1 eV valence band offset between Ge and GeOx was used in the simulations (Fig. 1(b)). The 500 meV valence band offset between between s-Ge and Si0.55Ge0.45creates a deep quantum well confining most of the holes in the s-Ge layer.Fig. 5 shows the 10 kHz experimental CV in addition to simulated quasistatic CV curves for structures with varying EOT. The mismatch of the simulated and experimental curves in strong hole accumulation is due to both a large series resistance (Rs ~ 0.1 Ω∙cm2) and gate leakage, which causes a sizable error when transforming the measured impedance to a two-element parallel capacitance CP , parallel conductance GP circuit model [5]. A circuit model (inset Fig. 6) incorporating parasitic gate tunneling conductance Gt and series resistance Rs is applied to an ideal simulated CV in order to recover the measured CV result, yielding an extracted EOT of 4.9 Å (Fig. 6). This is the smallest known EOT for a high quality dielectric on s-Ge published to date. Other recent results include a 7-Å EOT on s-Ge [6], and an 8-Å CET on unstrained Ge [7].

Impacts of gate-oxide breakdown on power-gated SRAM

This paper presents a detailed analysis on the impacts of various gate-oxide breakdown (BD) paths in column-based header- and footer-gated SRAMs. It is shown that with gate-oxide BD, the read static noise margin (RSNM) and write margin (WM) degrade in general. Pass-transistor gate-oxide BD between WL and BL is shown to degrade read/write margin and performance, and to affect other healthy cells along the same column as well. The effects of gate-to-source BD of cell transistors are shown to confine to the individual cells, while multiple cells suffering cell transistor drain-to-drain BD in a column could cumulatively affect VVDD (header structure) or VVSS (footer structure), thus influencing other cells in the same column. In particular, we show that the gate-oxide BD of the power-switches has severe and even detrimental effects on the margin, stability, and performance of the SRAM array. Several techniques to mitigate the power-switch gate-oxide BD have been evaluated, including adding a gate series resistance to the power-switch, dual threshold voltage power-switch, thick gate-oxide power-switch, and dual gate-oxide thickness (dual-TOX) power-switch. It is shown that the dual-TOX power-switch improves the time-to-dielectric-breakdown (TBD) of the power-switch while maintaining the performance without side effect.

Degradation of AlGaN/GaN High Electron Mobility Transistors with Different AlGaN Layer Thicknesses under Strong Electric Field

The degradation of AlGaN/GaN high electron mobility transistors (HEMTs) has a close relationship with a model of traps in AlGaN barriers as a result of high electric field. We mainly discuss the impacts of strong electrical field on the AlGaN barrier thickness of AlGaN/GaN HEMTs. It is found that the device with a thin AlGaN barrier layer is more easily degraded. We study the degradation of four parameters, i.e. the gate series resistance RGate, channel resistance Rchannel, gate current IG,off at VGS = −5 and VDS = 0.1 V, and drain current ID,max at VGS = 2 and VDS = 5 V. In addition, the degradation mechanisms of the device electrical parameters are also investigated in detail.

Photo-sensitive characteristics of negative resistance turn-around occurring in SIPTH

Influences of light irradiation on the negative resistance turn-around characteristics of static induction photosensitive thyristor (SIPTH) have been experimentally and theoretically studied. As the gate current of SIPTH is increased by the light irradiation, the potential barrier in the channel is reduced due to the increase in voltage drop across the gate series resistance. Therefore, SIPTH can be quickly switched from the blocking state to the conducting state by relatively low anode voltage. The optimal matching relation for controlling anode conducting voltage of SIPTH by light irradiation has also been represented.

Multichannel Field-Effect Transistor (MCFET)—Part II: Analysis of Gate Stack and Series Resistance Influence on the MCFET Performance

Three-dimensional multi-channel field-effect transistor (MCFET) gate stack and series resistance are investigated and optimized by specifically developed integration processes, characterization methods, and numerical simulations. First, the impact of a TiN/HfO2 gate stack on embedded-gate MCFET structure performance is studied. Both TiN/SiO2 and N+poly-Si/SiO2 gate stacks were introduced in the MCFET to compare the carrier mobility behavior (300 K down to 20 K), the gate leakage current, and the negative bias temperature instability. The obtained electrical data are then compared with a planar FD-SOI reference, highlighting some specific challenges linked to the introduction of a high- kappa/metal gate stack in embedded cavities. On the other hand, it is shown how the series resistance is intrinsically increased by the 3-D configuration. We also show how this increase can be attenuated significantly by optimizing the source/drain (S/D) shape, the implantation conditions, and the S/D silicide position.

A design of 0.25μm CMOS switch

Single-Pole Double-Throw (SPDT) broadband switch has been designed in a 0.25µm Complementary Metal Oxide Semiconductor (CMOS) process. To optimize the performance of isolation and insertion loss, based on normal design, the effects of Gate Series Resistances (GSR) on insertion loss and switching time are analyzed for the first time. The compatible GSRs are chosen by the analyses. The fabricated chips were tested and the results show the switch isolation from DC (Direct Current) to 1GHz exhibits 55dB and insertion loss lower than 2.1dB.

Modeling and optimization of series resistance of planar MIM capacitors

Integrated circuits for analog and telecom applications require metal insulator metal (MIM) capacitors with not only a high capacitance value (typically 5nF/mm2), but also a low series resistance Rs. The optimization of this latter parameter is investigated in this paper, by means of a simple analytical model, taking into account both the impact of material parameters and device architectures, suggesting possible strategies for Rs minimization. Such a model is also suitable for MIM circuit simulation, and can be also extended to other devices, such as to the gate series resistance modeling of RF MOSFET. Results are in good agreement with numerical simulations and HF measurements, performed on state of the art planar MIM devices. Moreover, discussion on via placement to access the top electrode has been held, in order to optimize the series resistance of the capacitor.

Structural Optimization of SUTBDG Devices for Low-Power Applications

In this paper, we investigate the impact of physical structure on the performance of symmetric ultrathin body double-gate devices for low-operating-power (LOP) applications. Devices with regular raised source/drain (S/D) structures have optimal spacer thicknesses governed by a tradeoff between fringing capacitance and series resistance. Expanded S/D structures improve on regular raised S/D structures by slowing down the increases in both fringing capacitance with gate height and series resistance with spacer thickness. The cost is more chip area and process complexity. Pure high-/spl kappa/ gate dielectrics raise the off-state current (I/sub OFF/) due to the fringing field-induced barrier lowering effect. Suppressing the I/sub OFF/ increase requires either a significant reduction in equivalent oxide thickness or a significant shift in gate work function. If the gate work function is tuned to maintain a fixed I/sub OFF/, devices with less abrupt S/D-channel junctions suffer a drive current (I/sub ON/) degradation, and devices with weakly coupling S/D and relatively thick bodies gain improvements in I/sub ON/. The I/sub ON/ of a device with metal S/D is significantly lower than required for LOP applications, if the S/D Schottky barrier height (SBH) is over 200 meV. We also briefly discuss the impact of mobility degradation on this structural optimization.

A New Method to Extract EOT of Ultrathin Gate Dielectric With High Leakage Current

The standard capacitance-voltage (C-V ) technique can no longer determine accurately the equivalent oxide thickness (EOT) for an advanced CMOS transistor with ultrathin gate dielectric where there is high gate leakage current, as well as series resistance; this situation will get worse as the CMOS transistor's scaling trend continues. This paper describes a simple methodology based on dual-frequency C-V measurement and four-element circuit model to extract accurately the EOT in the presence of gate leakage current and series resistance. This method can be effective with a current density of 1000 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for a 10 μm ×10 μm capacitor. Such a high current density will satisfy the projected gate leakage current requirements for many generations of CMOS technologies, as specified in the 2003 International Technology Roadmap for Semiconductors.

High-Frequency Limits of Heterostructure Field-Effect Transistors (HFETs)

This paper present a simplified theoretical basis for an understanding of the high frequency limits of the HFETs, and compares the performance of InP based short gate-length devices reported by various groups. For this comparison, the average velocity (Vav) in each device is extracted using the effective gate-length that includes the laterally extended gate-to-drain depletion length. The results indicate that Vav increases approximately from 2.46 x 107 to 3.0 x 107 cm/sec when the gate-length is reduced from 0.15 μm to 0.05 μm. This comparison clearly suggests that although reduction of the gate-length can increase the unity current-gain frequency (fτ), it does not necessarily lead to a high unity power-gain frequency (fmax). The latter requires a low gate series resistance (rgg'), a low source series resistance (rss'), and a very low drain-to-gate feedback capacitance cdg. Since all these parameters are adversely affected by the reduction of the gate-length, the challenge of realizing practical HFETs with useful power gain of 4dB at and beyond 300 GHz, appears to be a formidable one.

A new DC Drain-Current-Conductance method (DCCM) for the characterization of effective mobility (μ/sub eff/) and series resistances (R/sub s/, R/sub d/) of fresh and hot-carrier stressed graded junction MOSFETs

A simple new DC technique is developed to extract the gate bias dependent effective channel mobility (u/sub eff/) and series resistances (R/sub s/ and R/sub d/) of graded junction n- and p-channel MOSFETs. This technique is found to be accurate and effective for devices with differing channel lengths and also for devices after nonuniform hot-carrier degradation. The parameter values extracted provide further insight into the damage mechanisms of hot-carrier stressed graded junction nMOSFETs and are usable in circuit and reliability simulation. This technique is especially useful for the optimization of hot-carrier resistant structures of submicrometer MOSFETs.

Spreading resistance measurements in p-n junctions — a simple technique

A simple technique to extract the location and value of parasitic series resistance in junction devices is discussed and an instrument which performs these measurements is described. Measurements of gate series resistance on several high figure of merit junction field-effect transistors are presented. The limitations in noise behavior due to this resistance are discussed.

Influence of series resistances and interface coupling on the transconductance of fully-depleted silicon-on-insulator MOSFETs

A model is proposed to describe the variation of the transaconductance in fully-depleted silicon on insulator MOSFETs as a function of the front/back gate biases, channel length and series resistances. The influence of series resistances on the static characteristics of short-channel transistors depends on the region of operation, via the front and back gate voltages, and is a maximum when both interfaces are inverted. Simple analytical expressions explain the gradual deformation of the transconductance curve and the lowering of the transconductance peak with increasing series resistances. The model is experimentally verified by associating external resistors to the transistor. It is shown that a major consequence of X-ray irradiations in short-channel SIMOX MOSFETs is the trapping of positive charges in the buried oxide, which causes activation of interface coupling effects and enhanced influence of series resistances.

Millimeter-wave performance of ultrasubmicrometer-gate field-effect transistors: A comparison of MODFET, MESFET, and PBT structures

Device structures for the modulation-doped high-electron-mobility transistor (MODFET or HEMT), the metal Schottky-barrier gate transistor (MESFET), and the permeable-base transistor (PBT) With 0.1- to 0.25-µm gate lengths have been examined for their millimeter-wave performance. In particular, their unity-current-gain frequency (f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> ), maximum oscillation frequency (f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> ), and the stability of power gains are Compared. It is shown that in field-effect transistors with gate lengths below 0.25 µm, the high aspect ratio design approach, involving the ratio of the gate length to its associated depletion depth, needs to be extended to include the gate-to-drain separation in an effective gate-length concept. Using the charge-control approach in conjunction with the carrier velocity saturation effect, it is shown that the overall transit time delay across the total effective gate length results in an effective gate capacitance that is significantly larger than that due to the physical size of the gate itself. It is shown with specific examples that a successful design of these ultrasubmicrometer gate structures depends on the choice of the gate-to-drain separation (L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</inf> ) and the separation (d <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</inf> ) between the gate and the channel sheet Charge, with an appropriate choice of doping concentration consistent with the desired drain voltage operation. The designs have been based on practically obtainable values of the gate and source series resistances. When the actual gate length is much smaller than L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</inf> , as in the case of PBT's, it is shown that the stable power gain margin in these devices is determined by the square of the aspect ratio (L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</inf> /d <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</inf> ). The results show that an f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> of approximately 350 GHz can be achieved from a MODFET structure with an effective gate length of 0.14 µm. In a PBT structure an f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> exceeding 500 GHz can be achieved with an effective gate length of 0.15 µm, and in a similar MESFET structure an f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> of approximately 450 GHz can be achieved. The device design approach presented clearly indicates the possibility of achieving FET'S operating beyond 200 GHz with useful power gains.

Corrections to "Source, drain, and gate series resistances and electron saturation velocity in ion-implanted GaAs FET's"

Corrections to "Source, drain, and gate series resistances and electron saturation velocity in ion-implanted GaAs FET's"

Source, drain, and gate series resistances and electron saturation velocity in ion-implanted GaAs FET's

Techniques which allow us to determine the series source, drain, and gate resistances and the electron saturation velocity of ion-implanted GaAs FET's are described. These techniques are based on the resistance measurements. The theory of this method is developed and used for a new interpretation of the resistance measurements. The values of the series resistances determined by this technique are shown to be in an excellent agreement with those obtained by the modified Fukui method. The values of the electron saturation velocity varying from 1.0 × 105m/s to 1.3 × 105m/s are obtained using the end resistance method. The proposed set of measurements is simple and accurate enough to be used as a routine characterization technique for GaAs FET's.