Gate Oxide Lifetime Research Articles

Boron penetration effect on gate oxide reliability of 50 Å PMOS devices

Modern CMOS technology widely utilizes dual poly gate technology to create surface channel PMOS devices with a low threshold voltage. This article presents the analysis of degradation and gate oxide reliability in 50 Å oxide p+-poly PMOS transistors. The post-boron implant anneal temperature is used to vary the amount of boron penetration into the oxide. Results indicate the significant role of boron in the reduction of the gate oxide lifetime of PMOS devices and enhanced electron trapping in the oxide. This degradation correlates with the threshold voltage variation due to channel doping change. The stress-induced leakage current does not seem to be affected by the boron penetration effect.

Improvement of sheet resistance and gate oxide integrity using phosphorus ion implantation in tungsten polycide gate

An implantation of phosphorus is used in tungsten polycide gate process, and the effects of implantation on the reduction of resistance and characteristics of GOI (Gate Oxide Integrity) were investigated. The sheet resistance of gate electrode decreases with increase of phosphorus implant dose and energy as increase of grain size. The depletion effects of gate polysilicon at reverse biases were found in unimplanted tungsten polycide gate due to the out-diffusion of dopant atoms in buffer polysilicon layers during activation anneals. However, the depletion effects of gate polysilicon were effectively suppressed by the implantation of phosphorus. The lifetime of gate oxide was degraded several orders of magnitude for the high-energy implanted samples. Therefore, there is optimum energy for phosphorus implantation into gate electrode to improve the resistance of tungsten polycide gate electrode and the depletion effects of gate polysilicon.

New rapid method for lifetime determination of gate oxide validated with bipolar/CMOS/DMOS technology

Abstract We have established a new control method in order to decrease drastically the evaluation time of the gate oxide lifetime in bipolar/CMOS/DMOS technology. This technique is based on the measurement of the Fowler Nordheim (FN) current and on the use of a new equation established between the time to breakdown ( 1 E model) and the FN current. This technique applied to a test cell (THFE), thanks to direct probing on wafers, reduces the experimental capacitance measurement time down to four hours instead of several weeks.

Correlation between lifetime, temperature, and electrical stress for gate oxide lifetime testing

A relationship between the gate oxide lifetime (t/sub bd/), temperature (T), and the electrical stress for the reliability testing is investigated. Based on the various lifetime testing results reported by previous investigators, a new parameter for the oxide lifetime prediction is introduced. The parameter T[log(t/sub bd/)+C], where C is a constant, has a linear relationship with respect to the electrical stress field in the oxide. By using the above parameter, it becomes easy to describe and compare the characteristics of oxide reliability on one graph.

Sheet resistance and layout effects in accelerated tests for dielectric reliability evaluation

Different extrapolation algorithms can be used to calculate gate oxide lifetime from accelerated reliability tests. The measurement is often carried out on large area capacitors in order to be statistically meaningful with respect to the active oxide area of the devices. This also allows a reduction of test time and therefore of cost. However, both the capacitor layout and the sheet resistance either of gate or of substrate or of interconnections can have a huge impact on the correctness of the experimental data. In this work it will be shown that lifetime forecast can be largely over-estimated due to series resistance. Moreover, a non-optimized layout of the capacitor can induce a non-uniform stress on the oxide due to sheet resistance effects. The validity of the accelerated test is also questionable in this case. Some guidelines to avoid errors in the collection of raw data will also be given.

Correlating Charge-to-Breakdown with Constant-Current Injection to Gate Oxide Lifetime under Constant-Voltage Stress

In this paper we describe the Cumulative Damage Law which clarifies the relationship between the charge-to-breakdown with constant-current injection (Q bd) and the time-to-breakdown with constant-voltage stress (t bd). The oxide lifetime (t bd) can be predicted from Q bd by evaluating the time dependence of the gate current density J(t) under constant-voltage stress. The applicability of this relationship is verified for oxide thickness greater than 6 nm and various substrate temperatures in the range from 35°C to 150°C. It is found that the temperature dependence of the gate current density is responsible for the difference in the temperature-accelerating factors obtained using Q bd and t bd measurement methods, respectively.

Gate-oxide breakdown accelerated by large drain current in n-channel MOSFET's

A study of the time-dependent dielectric breakdown (TDDB) of thin gate oxides in small n-channel MOSFETs operated beyond punchthrough is discussed. Catastrophic gate-oxide breakdown is accelerated when holes generated by the large drain current are injected into the gate oxide. More specifically, the gate-oxide breakdown in a MOSFET (gate length=1.0 mu m, gate width-15 mu m) occurs in approximately 100 s at an applied gate oxide field of approximately 5.2 MV/cm during the high drain current stress, while it occurs in approximately 100 s at an applied gate oxide field of approximately 10.7 MV/cm during a conventional time-dependent dielectric breakdown (TDDB) test. The results indicate that the gate oxide lifetime is much shorter in MOSFETs when there is hot-hole injection than that expected using the conventional TDDB method. >

Breakdown Yield and Lifetime of Thin Gate Oxides in CMOS Processing

The processing effects on thin gate oxide yield and lifetime were studied by using ramp voltage and time‐dependent dielectric breakdown (TDDB) measurements on minimally processed MOS capacitors and fully processed devices in a CMOS technology. Gate oxides grown in a wet ambient are considerably superior to those grown in a dry ambient interms of breakdown distribution, yield, and lifetime. In addition, the correlation between lifetime and applied electric field also suggests an advantage for using wet oxides rather than dry oxides for scaling down the thickness. Several processing modules in a CMOS technology on the gate oxide breakdown characteristics are examined. High temperature oxidation and drive or back‐side gettering processing prior to the gate oxidation steps improve the oxide yield. Reactive ion or plasma etching for the gate electrode definition reduces lifetime of approximately 10% of the devices compared to the wet‐etched control. However, the most significant influence on the gate oxide yield and lifetime occurs during the oxidation and polysilicon gate deposition processing steps. Fully processed CMOS devices show a large reduction in gate oxide yield and lifetime as compared to minimally processed capacitors. Additional processing for double level metallization further degrades the gate oxide. This result indicates the cumulative nature of processing induced damage. Breakdown characteristics are significantly degraded when electrons are injected from the polysilicon gate as opposed to injection from the silicon substrate for the fully processed devices. This polarity dependence can be explained by plasma processing induced trapped holes near the interface which also cause anomalous leakage currents with a negative gate bias.