Abstract
Different extrapolation algorithms can be used to calculate gate oxide lifetime from accelerated reliability tests. The measurement is often carried out on large area capacitors in order to be statistically meaningful with respect to the active oxide area of the devices. This also allows a reduction of test time and therefore of cost. However, both the capacitor layout and the sheet resistance either of gate or of substrate or of interconnections can have a huge impact on the correctness of the experimental data. In this work it will be shown that lifetime forecast can be largely over-estimated due to series resistance. Moreover, a non-optimized layout of the capacitor can induce a non-uniform stress on the oxide due to sheet resistance effects. The validity of the accelerated test is also questionable in this case. Some guidelines to avoid errors in the collection of raw data will also be given.
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