Gate HEMT Research Articles

Gate Leakage Suppression and Breakdown Voltage Enhancement in p-GaN HEMTs Using Metal/Graphene Gates

In this work, single-layer intrinsic and fluorinated graphene were investigated as gate insertion layers in normally-OFF p-GaN gate HEMTs, which wraps around the bottom of the gate forming Ti/graphene/p-GaN at the bottom and Ti/graphene/ SiNx on the two sides. Compared to the Au/Ti/p-GaN HEMTs without graphene, the insertion of graphene can increase the ION/IOFF ratios by a factor of 50, increase the VTH by 0.30 V and reduce the off-state gate leakage by 50 times. Additionally, this novel gate structure has better thermal stability. After thermal annealing at 350 {\deg}C, gate breakdown voltage holds at 12.1 V, which is first reported for Schottky gate p-GaN HEMTs. This is considered to be a result of the 0.24 eV increase in Schottky barrier height and the better quality of the Ti/graphene/p-GaN and Ti/graphene/SiNx interfaces. This approach is very effective in improving the Ion/Iff ratio and gate BV of normally-OFF GaN HEMTs.

Asymmetric Bipolar Injection in a Schottky-Metal/${p}$ -GaN/AlGaN/GaN Device Under Forward Bias

In this letter, we investigated the electroluminescence (EL) spectra and photovoltage spectrum of a Schottky-metal/p-GaN/AlGaN/GaN diode with a semitransparent anode electrode. By analyzing the bias-dependence of the EL spectra of the diode as well as the gate stress bias-/time-dependences of the threshold voltage shift of a p-GaN gate HEMT, the electron/hole injection sequence, electron trapping, hole-assisted de-trapping, and optical pumping processes in the p-GaN gate region are identified. The band diagrams of the Schottky-metal/p-GaN/AlGaN/GaN heterostructure under different forward bias voltages are proposed.

Frequency- and Temperature-Dependent Gate Reliability of Schottky-Type ${p}$ -GaN Gate HEMTs

In this paper, we carried out a systematic investigation on gate degradation and the physical mechanism of the Schottky-type ${p}$ -GaN gate HEMTs under positive gate voltage stress. The frequency- and temperature-dependent measurements have been conducted. It is found that the time-dependent gate degradation exhibits weak relevance with frequencies ranging from 10 to 100 kHz under dynamic gate stress and is similar to that in static gate stress. Both the gate breakdown voltage (BV) and mean-time-to-failure (MTTF) show positive temperature dependence. Moreover, the current–voltage ( I–V ) characteristics and threshold voltage ( ${V}_{\text {TH}}$ ) instability of ${p}$ -GaN devices before/after gate degradation are compared and analyzed. The degraded Schottky junction exhibits an ohmic-like gate behavior. It is revealed that under a large gate bias stress, high-energy electrons accelerated in the depletion region of the ${p}$ -GaN layer would promote the formation of defect levels near the metal/ ${p}$ -GaN interface, leading to the initial ${p}$ -GaN layer degradation. The subsequent high gate leakage density could cause the final degradation of the AlGaN barrier.

(Invited) GaN-Based Multiple 2DEG Channel BRIDGE (Buried Dual Gate) HEMT Technology for High Power and Linearity

We report on a GaN-based field effect transistor with laterally-gated multiple 2DEG channels, called BRIDGE (buried dual gate) HEMT. Unique operation principle of the transistor enables unprecedented device characteristics suitable for efficient and linear millimeter-wave power amplifier applications. The lateral gate simultaneously modulate multiple 2DEG channels formed in an Al(Ga)N/GaN hetero-structure. A higher electron saturation velocity measured for a lower 2DEG density suggests that the multiple 2DEG channel structure is ideal for obtaining a high current density, and simultaneously enhancing high frequency performance of the transistor. The BRIDGE HEMTs built on a 16-channel HEMT epitaxial structure with a net 2DEG density of 3.3×1013 cm-2 exhibited a record high knee current density of 3.7 A/mm. The absence of the top contact gate results in negligible current collapse by eliminating a high electric field region at the drain end of the gate – another key feature of the BRIDGE HEMT.

Charge Storage Mechanism of Drain Induced Dynamic Threshold Voltage Shift in ${p}$ -GaN Gate HEMTs

The drain induced dynamic threshold voltage ( ${V}_{\textrm {th}}$ ) shift of a ${p}$ -GaN gate HEMT with a Schottky gate contact is investigated, and the underlying mechanisms are explained with a charge storage model. When the device experiences a high drain bias ${V}_{\textrm {DSQ}}$ , the gate-to-drain capacitance ( ${C}_{\textrm {GD}}$ ) is charged to ${Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSQ}}$ ). As the drain voltage drops to ${V}_{\textrm {DSM}}$ where ${V}_{\textrm {th}}$ is measured, ${C}_{\textrm {GD}}$ is expected to be discharged to ${Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSM}}$ ). However, the metal/ ${p}$ -GaN Schottky junction could block the discharging current, resulting in storage of negative charges in the ${p}$ -GaN layer. For the device to turn on, additional gate voltage is required to counteract the stored negative charges, resulting in a positive shift of ${V}_{\textrm {th}}$ . The dynamic ${V}_{\textrm {th}}$ shift is an intrinsic and predictable characteristic of the ${p}$ -GaN gate HEMT which is linearly correlated with $\Delta \!{Q}_{\textrm {GD}}={Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSQ}}$ ) $- {Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSM}}$ ). The ${V}_{\textrm {th}}$ shift is dependent on ${V}_{\textrm {DSQ}}$ as well as ${V}_{\textrm {DSM}}$ , indicating that the ${V}_{\textrm {th}}$ shift is varying along the load line during a switching operation.

Nanoscale T-shaped AlGaN/GaN HEMT with improved DC and RF performance

AlGaN/GaN-based HEMT with different gate structure are designed i.e., 150 nm rectangular shaped HEMT and 90 nm T-shaped HEMT. It is shown that the DC parameters like drain current, transconductance are improved for T-shaped HEMT as compared to normal gate HEMT. The maximum cut-off frequency for normal gate HEMT is 24 GHz at drain voltage of 20 V and gate voltage of 2 V whereas it is 47 GHz for the T-shaped HEMT. Maximum frequency of oscillation for normal gate HEMT is 95 GHz and for T-shaped HEMT, it is 115 GHz. At the frequency of 5 GHz, the minimum noise figure of the normal gate HEMT is 0.13 dB and for T-shaped HEMT, it is 0.05 dB. Intrinsic time delay of normal gate HEMT is 22 ps whereas the intrinsic time delay for T-gate HEMT is 12 ps. These results prove that the T-shaped HEMT is more preferable for high frequency operations like radar communication, satellite communication, wireless communication, etc.

Nanoscale T-shaped AlGaN/GaN HEMT with improved DC and RF performance

AlGaN/GaN-based HEMT with different gate structure are designed i.e., 150 nm rectangular shaped HEMT and 90 nm T-shaped HEMT. It is shown that the DC parameters like drain current, transconductance are improved for T-shaped HEMT as compared to normal gate HEMT. The maximum cut-off frequency for normal gate HEMT is 24 GHz at drain voltage of 20 V and gate voltage of 2 V whereas it is 47 GHz for the T-shaped HEMT. Maximum frequency of oscillation for normal gate HEMT is 95 GHz and for T-shaped HEMT, it is 115 GHz. At the frequency of 5 GHz, the minimum noise figure of the normal gate HEMT is 0.13 dB and for T-shaped HEMT, it is 0.05 dB. Intrinsic time delay of normal gate HEMT is 22 ps whereas the intrinsic time delay for T-gate HEMT is 12 ps. These results prove that the T-shaped HEMT is more preferable for high frequency operations like radar communication, satellite communication, wireless communication, etc.

High Uniformity Normally-OFF p-GaN Gate HEMT Using Self-Terminated Digital Etching Technique

A normally-OFF p-GaN gate AlGaN/GaN high-electron-mobility transistor with high ON-state resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) uniformity was realized using a self-terminated digital etching technique. ${R}_{ \mathrm{\scriptscriptstyle ON}}$ uniformity control was improved by simultaneously using an AlN etching stop layer in an epitaxial design and a novel digital etching procedure. Digital etching includes the multiple-cycle oxidation and the wet etching of p-GaN layers and provides easy control of p-GaN removal depth and surface damage reduction at the gate-to-drain and gate-to-source spacing areas. Low-frequency noise and pulse measurements indicated that device surface traps and current collapse phenomena were suppressed.

Efficient 3D-TLM Modeling and Simulation for the Thermal Management of Microwave AlGaN/GaN HEMT Used in High Power Amplifiers SSPA

A three-dimensional thermal simulation investigation for the thermal management of GaN-on-SiC monolithic microwave integrated circuits (MMICs) of consisting multi-fingers (HEMTs) is presented. The purpose of this work is to demonstrate the utility and efficiency of the three-dimensional Transmission Line Matrix method (3D-TLM) in a thermal analysis of high power AlGaN/GaN heterostructures single gate and multi-fingers HEMT SSPA (solid state power amplifiers). The self-heating effects induce thermal cross-talk between individual fingers in multi-finger AlGaN/GaN that affect device performance and reliability. Gate-finger temperature differences only arise after a transient state, due to the beginning of thermal crosstalk which is attributed to the finite rate of heat diffusion between gate fingers. The TLM method accounts for the real geometrical structure and the non-linear thermal conductivities of GaN and SiC in order to improve the realistic calculations accuracy heat dissipation and thermal behavior of the device. In addition, two types of heat sources located on the top of GaN layer are considered in thermal simulations: Nano-scale hotspot as a pulsed wave heat source under gate and micro-scale hotspot as a continuous wave heat source, between gate and drain. Heat diffusion however, occurs not only between individual gate fingers (inter-finger) in a multi-finger HEMT, but also within each gate finger (intra-finger). To compare results, a Micro-Raman Spectroscopy experience is conducted to obtain a detailed and accurate temperature distribution. Good agreement between the microscopic spectral measurement and TLM simulation results is observed by accepting an error less than 2.2% relative to a maximum temperature. Results show that the 3D-TLM method is suitable for understanding heat management in particular for microwave devices AlGaN/GaN HEMTs SSPA amplifier. TLM method helps to select and locates the expected hot spots and to highlight the need of thermal study pre-design in order to minimize the system-level thermal dissipation and lead therefore to higher reliability.

Unstable behaviour of normally-off GaN E-HEMT under short-circuit

The short-circuit capability of power switching devices plays an important role in fault detection and the protection of power circuits. In this work, an experimental study on the short-circuit (SC) capability of commercial 600 V Gallium Nitride enhancement-mode high-electron-mobility transistors (E-HEMT) is presented. A different failure mechanism has been identified for commercial p-doped GaN gate (p-GaN) HEMT and metal-insulator-semiconductor (MIS) HEMT. In addition to the well known thermal breakdown, a premature breakdown is shown on both GaN HEMTs, triggered by hot electron trapping at the surface, which demonstrates that current commercial GaN HEMTs has requirements for improving their SC ruggedness.

Relationship between effective mobility and border traps associated with charge trapping in In0.7Ga0.3As MOSFETs with various high-κ stacks

The effective mobility and reliability characteristics of In0.7Ga0.3As quantum-well (QW) MOSFETs with various high-κ gate stacks and HEMTs with a Schottky gate under bias temperature instability (BTI) stress were investigated. The effective mobilities (μeff) of HEMTs, single-layer Al2O3, bilayer Al2O3 (0.6 nm)/HfO2 (2.0 nm), and Al2O3 (0.6 nm)/HfO2 (3.0 nm) were ∼9000, ∼6158, ∼4789, and ∼4447 cm2 V−1 s−1 at Ninv = 1.5 × 1012/cm2, respectively. The maximum effective mobility of In0.7Ga0.3As channel MOSFETs was compared with that of In0.7Ga0.3As/In0.48Al0.52As HEMTs, which are interface and border trap-free FETs. The results showed that the effective channel mobility was sensitive to traps in high-κ dielectrics related to interface trap density and border traps in the oxide. The ΔVT degradation of the bilayer Al2O3/HfO2 under BTI stress was greater than that of a single Al2O3 layer because the HfO2 layer had a high density of oxygen vacancies which were related to border traps.

The Recessed Trapezoidal Groove Dual‐Gate AlGaN/GaN E‐Mode Transistor by Using Depletion Enhancement Effect

The recessed trapezoidal groove dual‐gate profile is achieved by the low power CF4 plasma etching based on the principle of ion‐scattering. The recessed trapezoidal groove dual‐gate architecture can increase the lateral broadening of depletion width, yielding the Enhancement‐mode operation. This device demonstrates a threshold voltage of 0.43 V, a maximum drain current of 480 mA mm−1 and a trans‐conductance of 308 mS mm−1. The device exhibits a low off‐state leakage current of ≈10−10 A mm−1 and gate induced drain leakage is effectively improved. An extrinsic current gain cut off frequency of 32 GHz and a maximum oscillation frequency of 65 GHz are deduced. The threshold voltage (Vth) stability of the Schottky gate HEMT is investigated. The recessed trapezoidal groove dual‐gate exhibits a small shift of Vth, which is attributed to the lateral extension of depletion region in the trapezoidal groove dual‐gate structure.

VTH Instability of p-GaN Gate HEMTs under Static and Dynamic Gate Stress

The impacts of static and dynamic gate stress on the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> ) instability in Schottky-type <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -GaN gate AlGaN/GaN heterojunction field-effect transistors are experimentally investigated. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shifts negatively under large positive bias static stress ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}\_ {\text {stress}} &gt; 5$ </tex-math></inline-formula> V) by adopting conventional quasi-static characterization techniques. In contrast, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> under fast-dynamic-stress exhibits positive shift, and a positive frequency dependence occurs within a wide range of frequency from 10 Hz to 1 MHz. The different <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> instability behavior under static and dynamic stress mainly originates from the time-dependent charges (electrons and holes) storage/release mechanisms in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -GaN layer, which is floating in the Schottky-type <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -GaN gate HEMT.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance–voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of −20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10−7 mA mm−1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

Short-Circuit Study in Medium-Voltage GaN Cascodes, p-GaN HEMTs, and GaN MISHEMTs

This paper studies by experimentation and physics-based simulation the Short-Circuit (SC) capability of several normally-off 600–650 V Gallium Nitride High-Electron-Mobility Transistors (GaN HEMTs): cascodes, p-GaN, and GaN Metal–Insulator–Semiconductor HEMTs (MISHEMTs). As a result, cascodes present the worst SC ruggedness. By contrast, p-GaN gate HEMTs and MISHEMTs provide a higher SC capability thanks to their strong drain current reduction. In addition, a valuable state-of-the-art about all commercially available technologies is also provided, which demonstrates that current GaN devices do not allow SC capability.

Second Breakdown and Robustness of Vertical and Lateral GaN Power Field‐Effect Transistors

Robustness of GaN power field‐effect transistors, including the vertical UMOSFET, vertical DMOSFET, and lateral p‐AlGaN gate HEMT is studied by analyzing their safe operating areas (SOA) using finite‐element‐analysis device simulation. At off‐state gate voltages, the devices are forced into high‐voltage, high‐current avalanche breakdown. Assuming isothermal conditions at 300 K, the simulated DMOSFET SOA exhibits high robustness, while the UMOSFET and the p‐AlGaN gate HEMT experiences current snapback. The simulated robustness of both the DMOSFET and the UMOSFET degrades when realistic temperature dependence is included in the non‐isothermal case, with current filamentation in high dissipation areas, leading to a more pronounced current snapback.

Lossless turn-off switching projection of lateral and vertical GaN power field-effect transistors

New physical insights into switching loss evaluation are applied to GaN power field-effect transistors, including p-AlGaN gate HEMTs, MOS channel HEMTs, and vertical UMOSFETs. Internal channel current is used to calculate true switching loss values for both turn-on and -off. In contrast to conventional terminal current-based loss calculations, energy stored in device output capacitances during turn-off and dissipated during turn-on is counted as turn-on loss rather than turn-off loss. At appropriate RG and off-state VG values, lossless turn-off can be achieved for MOS channel HEMTs and UMOSFETs, but not for p-AlGaN gate HEMTs. In appropriate circuit applications, near zero total switching loss can be realized by combining lossless turn-off and zero-voltage turn-on.

Three-Level Gate Drivers for eGaN HEMTs in Resonant Converters

Commercial eGaN HEMT gate drivers focus on high reliability to the strict gate driving voltage against parasitic components. However, they do not consider the high reverse conduction voltage due to the reverse conduction mechanism under ZVS condition. A three-level gate driver is proposed for eGaN control HEMTs. The midlevel voltage reduces the reverse conduction voltage since that the reverse conduction voltage decreases when gate voltage increases. The proposed driver is applied to a 7-MHz isolated resonant SEPIC converter. The efficiency was improved from 72.7% using conventional driver to 73.4% (an improvement of 0.7%) with 24-V input and 5-V/10-W output. An eGaN SR gate driver is proposed to minimize the reverse conduction time. The driver uses a wave-shape circuit, designed by the HEMT rectifier mathematic model built with the MATLAB script, to compensate the driving IC propagation delay and obtain desired driving signal timing. The proposed SR driver improves the efficiency from 79.9% without considering the driving IC delay to 84.7% (an improvement of 4.8%) with 18-V input and 5-V/10-W output.

P-GaN HEMTs Drain and Gate Current Analysis Under Short-Circuit

Gallium Nitride High-Electron-Mobility Transistors (GaN HEMTs) are promising devices for high-frequency and high-power density converters, but some of their applications (e.g., motor drives) require high robustness levels. In this scenario, 600 V normally-off p-GaN gate HEMTs are studied under Short-Circuit (SC) by experiment and physics-based simulations (drift-diffusion and thermodynamic models). A strong drain current reduction (>70% after saturation peak) and high gate leakage current (tens of mA) are observed. All studied devices withstand the SC test at bus voltages up to 350 V, while fail at 400 V. Furthermore, its understanding is crucial to improving SC ruggedness in p-GaN HEMTs.

Study on Trapping Effects in AlGaN/GaN-on-Si Devices with Vertical Interconnect Structures

In this paper, AlGaN/GaN Schottky gate HEMTs on silicon based on vertical interconnect structures were fabricated and analyzed. The device with a vertical drain interconnect to the substrate shows worse current collapse based on drain lag measurement compared with both the conventional lateral device without vertical interconnect and the device with a vertical source interconnect to the substrate, implying that electrons are trapped in the epilayer due to existence of a vertical electric field. The trapped electrons in the epi and buffer layers introduce a positive shift in the threshold voltage by about 1.5 V together with an increase in the specific on-resistance, but show nearly no effect on the turn-on voltage of the Schottky junction.