Second Breakdown and Robustness of Vertical and Lateral GaN Power Field‐Effect Transistors

Abstract

Robustness of GaN power field‐effect transistors, including the vertical UMOSFET, vertical DMOSFET, and lateral p‐AlGaN gate HEMT is studied by analyzing their safe operating areas (SOA) using finite‐element‐analysis device simulation. At off‐state gate voltages, the devices are forced into high‐voltage, high‐current avalanche breakdown. Assuming isothermal conditions at 300 K, the simulated DMOSFET SOA exhibits high robustness, while the UMOSFET and the p‐AlGaN gate HEMT experiences current snapback. The simulated robustness of both the DMOSFET and the UMOSFET degrades when realistic temperature dependence is included in the non‐isothermal case, with current filamentation in high dissipation areas, leading to a more pronounced current snapback.