Gate-level Circuits Research Articles

Modular Timing Constraints for Delay-Insensitive Systems

This paper introduces ARCtimer, a framework for modeling, generating, verifying, and enforcing timing constraints for individual self-timed handshake components. The constraints guarantee that the component’s gate-level circuit implementation obeys the component’s handshake protocol specification. Because the handshake protocols are delayinsensitive, self-timed systems built using ARCtimer-verified components are also delay-insensitive. By carefully considering time locally, we can ignore time globally. ARCtimer comes early in the design process as part of building a library of verified components for later system use. The library also stores static timing analysis (STA) code to validate and enforce the component’s constraints in any self-timed system built using the library. The library descriptions of a handshake component’s circuit, protocol, timing constraints, and STA code are robust to circuit modifications applied later in the design process by technology mapping or layout tools. In addition to presenting new work and discussing related work, this paper identifies critical choices and explains what modular timing verification entails and how it works.

Design of an 8-Channel FFT Processor for IEEE 802.11ac MIMO-OFDM WLAN System

In this study, an area-efficient 8-channel 128-point fast Fourier transform (FFT) processor is proposed for IEEE 802.11ac standard MIMO-OFDM system. The proposed FFT processor is based on mixed-radix multi-path delay commutator (MRMDC) architecture and supports eight spatial data streams. Using input memory array transpose architecture and a bit-reversal circuit, the proposed FFT processor can generate eight input and output spatial data streams in natural order. Therefore, the processor can be used directly in MIMO-OFDM systems without additional input or output RAM. The proposed FFT processor is designed using hardware description language and synthesized to a gate-level circuit using a TSMC 90-nm CMOS standard cell library. Compared with other 8-channel MRMDC FFT processors, the proposed FFT processor can reduce the logic gate count of the MRMDC module by approximately 12.5 %.

A fast model for analysis and improvement of gate-level circuit reliability

Reliability is becoming one of increasingly critical issues for design of modern integrated circuits, due to the continuous scaling of CMOS technology and emerging nano-scale devices. This paper presents a novel method for reliability analysis in combinational circuits with unreliable devices. By using the concept of equivalent reliability, the proposed method promises improvements over the state-of-the-art methods in terms of efficiency, while keeping a high level of accuracy, in estimating the circuit reliability. This efficiency is achieved due to the fact that this work utilizes input probabilities and gate reliabilities directly for reliability evaluation, instead of taking (or sampling) a huge number of input vectors as with most existing approaches. Simulation results on benchmark circuits show that our approach obtains a significant speedup over other existing methods, especially when the reliability evaluation is repetitively needed for a same circuit in order to provide the reliability improvement for reliability-driven design applications.

面向晶体管级广义门电路的PTM可靠性计算

When the imprecise reliability of generalized gates is applied to the gate-level or high-level circuits, the errors could be easily over enlarged for the scale effect and other reasons, which leads to unreliable results. In this paper, the PTM model, which the effectiveness was proved by accurate gate-level circuit reliability estimation, was chosen to accurately calculate the structure reliability of generalized gates at the transistor-level; the structure logistic abstract of transistor-level generalized gates is analyzed and transformed into the style of gate-level structure logistic abstract having the same function with the pre-transform one; the failure points of circuit components and the main fault modes are extracted, and the corresponding probabilistic transfer matrixes oriented to faults are constructed; according to the characteristics of series-parallel circuit components, the structure reliabilities of transistor-level generalized gates are calculated by the gate-level PTM method under the fault conditions on input signals. Simulation results for typical generalized gates demonstrate the effectiveness of the proposed method; furthermore, the relation between generalized gates reliability and these main types faults is analyzed, and some interesting results are got.

Gate-Level Circuit Reliability Analysis: A Survey

Circuit reliability has become a growing concern in today’s nanoelectronics, which motivates strong research interest over the years in reliability analysis and reliability-oriented circuit design. While quite a few approaches for circuit reliability analysis have been reported, there is a lack of comparative studies on their pros and cons in terms of both accuracy and efficiency. This paper provides an overview of some typical methods for reliability analysis with focus on gate-level circuits, large or small, with or without reconvergent fanouts. It is intended to help the readers gain an insight into the reliability issues, and their complexity as well as optional solutions. Understanding the reliability analysis is also a first step towards advanced circuit designs for improved reliability in the future research.

소형 애플리케이션에 적합한 AES-128 기반 저면적 암호화 회로 설계

정보화 기술의 발전에 따라 웨어러블 장치, 휴대용 장치, RFID와 같은 소형 애플리케이션에 대한 관심이 증가하고 있고, 여기에 적용하기 위한 소형 암호화 회로의 중요성이 강조되고 있다. 본 논문에서는 소형 애플리케이션에 적합한 AES 기반 암호화 회로를 제안한다. 제안하는 회로에서는 저장 공간의 최소화, 연산 자원의 공유를 통해서 크기를 최소화 하였다. 제안하는 회로는 <TEX>$8{\times}16$</TEX> 비트 크기의 SRAM 두 개를 사용하였으며, 65nm 표준 셀 라이브러리를 이용하여 합성한 결과 2,241 개의 게이트로 구현되었고, 처리 속도는 초당 50.57M 비트이다. 따라서 저면적 암호화 회로를 필요로 하는 다양한 애플리케이션에 적용하여 사용할 수 있다. As the development of information technology, the interests in tiny applications such as wearable devices, portable devices and RFID are increased and the importance of low-area encryption circuit is emphasized. This paper proposes a compact architecture of AES-based encryption circuit suitable for tiny applications. The circuit area is reduced by minimizing storage space and sharing computation resources. The synthesized gate-level circuit using 65nm standard cell library consists of 2,241 gates and two <TEX>$8{\times}16$</TEX>-bit SRAMs. It can process data at a rate of 50.57Mbits per second. Therefore, the proposed encryption circuit is suitable for various applications requiring very small encryption circuit.

An Accurate Gate-level Stress Estimation for NBTI

Negative bias temperature instability (NBTI) has become a major factor determining circuit reliability. The effect of the NBTI on the circuit performance depends on the duty cycle which represents the stress and recovery conditions of each device in a circuit. In this paper, we propose an analytical model to perform more accurate duty cycle estimation at the gate-level. The proposed model allows accurate (average error rate: 3%) computation of the duty cycle without the need for expensive transistor-level simulations Furthermore, our model estimates the waveforms at each node, allowing various aging effects to be applied for a reliable gatelevel circuit aging analysis framework.

Area-efficient FFT processor for MIMO-OFDM based SDR systems

In this letter, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed FFT processor can support variable lengths of 64, 128, 256, 512, 1024, 1536 and 2048. By reducing the required number of non-trivial multipliers with a mixed-radix algorithm, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in a hardware description language (HDL) and synthesized to gate-level circuits using a 0.13µm CMOS standard cell library. With the proposed architecture, the gate count for the proposed FFT processor is 78.8K and the size of memory is 393.22Kbits, which are reduced by 40.9% and 19.7%, respectively, compared with the 4-channel radix-2 single-path delay feedback (R2SDF) with the 4-channel radix-3 SDF (R3SDF) FFT processor. Also, compared with the 4-channel radix-2 multi-path delay commutator (R2MDC) with the 4-channel R3SDF FFT processor, it is shown that the gate count and memory size are reduced by 33.8% and 18.5%, respectively.

Haar-like 특징을 이용한 고성능 보행자 및 차량 인식 회로 설계

본 논문은 Haar-like 특징을 이용한 고성능 보행자 및 차량 인식 회로를 제안한다. 제안하는 회로는 영상의 매 프레임 마다 슬라이딩 윈도우를 적용하여 Haar-like 특징을 추출하고 보행자 및 차량을 인식한다. Haar-like 특징 추출 회로는 슬라이딩 윈도우 당 200개의 Haar-like 특징을 추출하며, 추출된 특징들은 AdaBoost 인식 회로에서 사용된다. 제안하는 회로는 속도 향상을 위해 병렬 회로 구조를 적용하였으며 두 개의 슬라이딩 윈도우가 동시에 보행자 또는 차량을 인식한다. 제안하는 고성능 보행자 및 차량 인식 회로는 Verilog HDL로 설계하였으며 130nm 표준 셀 라이브러리를 이용하여 게이트 수준의 회로로 합성하였다. 합성된 회로는 1,388,260개의 게이트로 구성되며 최대 동작 주파수는 203MHz이다. 제안하는 회로는 <TEX>$640{\times}480$</TEX> 영상을 초당 약 47.8장 처리할 수 있기 때문에 보행자와 차량을 실시간으로 인식하기 위해 사용될 수 있다. This paper describes the design of high-performance pedestrian and vehicle detection circuit using the Haar-like features. The proposed circuit uses a sliding window for every image frame in order to extract Haar-like features and to detect pedestrians and vehicles. A total of 200 Haar-like features per sliding window is extracted from Haar-like feature extraction circuit and the extracted features are provided to AdaBoost classifier circuit. In order to increase the processing speed, the proposed circuit adopts the parallel architecture and it can process two sliding windows at the same time. We described the proposed high-performance pedestrian and vehicle detection circuit using Verilog HDL and synthesized the gate-level circuit using the 130nm standard cell library. The synthesized circuit consists of 1,388,260 gates and its maximum operating frequency is 203MHz. Since the proposed circuit processes about 47.8 <TEX>$640{\times}480$</TEX> image frames per second, it can be used to provide the real-time detection of pedestrians and vehicles.

Design of High-Performance Unified Circuit for Linear and Non-Linear SVM Classifications

This paper describes the design of a high- performance unified SVM classifier circuit. The proposed circuit supports both linear and non-linear SVM classifications. In order to ensure efficient classification, a 48x96 or 64x64 sliding window with 20 window strides is used. We reduced the circuit size by sharing most of the resources required for both types of classification. We described the proposed unified SVM classifier circuit using the Verilog HDL and synthesized the gate-level circuit using 65nm standard cell library. The synthesized circuit consists of 661,261 gates, operates at the maximum operating frequency of 152 MHz and processes up to 33.8 640x480 image frames per second.

Constructive Boolean circuits and the exactness of timed ternary simulation

We classify gate level circuits with cycles based on their stabilization behavior. We define a formal class of combinational circuits, the constructive circuits, for which signals settle to a unique value in bounded time, for any input, under a simple conservative delay model, called the up-bounded non-inertial (UN) delay. Since circuits with combinational cycles can exhibit asynchronous behavior, such as non-determinism or metastability, it is crucial to ground their analysis in a formal delay model, which previous work in this area did not do. We prove that ternary simulation, such as the practical algorithm proposed by Malik, decides the class of constructive circuits. We prove that three-valued algebra is able to maintain correct and exact stabilization information under the UN-delay model, and thus provides an adequate electrical interpretation of Malik's algorithm, which has been missing in the literature. Previous work on combinational circuits used the upbounded inertial (UI) delay to justify ternary simulation. We show that the match is not exact and that stabilization under the UI-model, in general, cannot be decided by ternary simulation. We argue for the superiority of the UN-model for reasons of complexity, compositionality and electrical adequacy. The UN-model, in contrast to the UI-model, is consistent with the hypothesis that physical mechanisms cannot implement non-deterministic choice in bounded time. As the corner-stone of our main results we introduce UN-Logic, an axiomatic specification language for UN-delay circuits that mediates between the real-time behavior and its abstract simulation in the ternary domain. We present a symbolic simulation calculus for circuit theories expressed in UN-logic and prove it sound and complete for the UN-model. This provides, for the first time, a correctness and exactness result for the timing analysis of cyclic circuits. Our algorithm is a timed extension of Malik's pure ternary algorithm and closely related to the timed algorithm proposed by Riedel and Bruck, which however was not formally linked with real-time execution models.

FPGA-based cooperative control of indoor multiple robots

Cooperative control of a group of mobile robots remains a challenging topic in robotics. In the emerging trend of ubiquitous robotics, real-time control using vision-based surveillance strategies requires embedded systems with limited computational performance and energy saving. In this paper, a control-system-on-chip architecture is developed for coordination of control of an indoor robotic formation by using a field programmable gate array (FPGA) chip. The prototype features capabilities of colour-based motion object tracking, inter-robot distance estimation, trajectory estimation, velocity control, formation initialisation and maintenance. All algorithms are implemented in pure register-transfer and gate-level circuits with localisation from a global monocular camera. Experiment results are included for miniature robots deployed in a line formation. The FPGA’s resource usage and power consumption are analysed to show efficiency of the proposed approach.

Resolution of Diagnosis Based on Transition Faults

The conventional detection conditions for transition faults do not predict fault effects that may be created when transition faults are activated and/or propagated by pulses (or hazards). For this, detection conditions that take hazards into consideration need to be used. However, since the occurrence of pulses cannot be predicted accurately based on a gate-level circuit description, the transition fault model becomes more susceptible to pattern-dependent effects, where errors on observed outputs that are predicted by the fault model may not appear in a circuit-under-diagnosis. This paper considers the implications of these pattern-dependent effects on the resolution of fault diagnosis based on transition faults.

H.264 움직임 예측을 위한 Luma와 Chroma 부화소 보간기 설계

본 논문은 H.264 움직임 예측을 위해 휘도 성분과 색차 성분의 부화소를 생성하는 효율적인 부화소 보간기 회로 설계에 대해 기술한다. 제안된 구조를 기반으로 한 회로는 보간 연산을 위해 입력 데이터를 버퍼링하지 않고 수평, 수직, 대각선의 부화소 보간을 병렬로 처리한다. 휘도성분에 대한 1/2 화소, 1/4 화소 보간과 색차 성분에 대한 1/8 화소 보간을 동시에 처리하여 회로 성능을 더욱 개선하였다. 회로 크기를 줄이기 위해 본 논문에서는 병렬로 보간 연산을 처리하는데 필요한 모든 중간 데이터를 레지스터 대신 내부 SRAM에 저장하였다. 제안된 구조를 레지스터 전달 수준의 회로로 기술하였고, FPGA 보드에서 동작을 검증하였다. 또한 구현된 회로를 130nm CMOS 표준 셀 라이브러리를 이용하여 게이트 수준의 회로로 합성하였다. 합성된 회로의 크기는 20,674 게이트이고 최대 동작 주파수는 244MHz이다. 회로에 사용된 SPSRAM의 전체 크기는 3,232 비트이다. 구현된 회로는 논리 게이트와 SRAM을 포함하여 다른 논문에서 제안한 회로에 비해 크기가 작고 성능도 우수하다. This paper describes an efficient design of the interpolation circuit to generate the luma and chroma sub-pixels for H.264 motion estimation. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolations in parallel. The performance of the circuit is further improved by simultaneously processing the 1/2-pixel and 1/4-pixel interpolations for luma components and the 1/8-pixel interpolations for chroma components. In order to reduce the circuit size, we store the intermediate data required to process all the interpolations in parallel in the internal SRAM's instead of registers. We described the proposed circuit at register transfer level and verified its operation on FPGA board. We also synthesized the gate-level circuit using 130nm CMOS standard cell library. It consists of 20,674 gates and has the maximum operating frequency of 244MHz. The total number of SPSRAM bits used in our circuit is 3,232. The size of our circuit (including logic gates and SRAM's) is smaller than others and the performance is still comparable to them.

DESIGN AND IMPLEMENTATION OF SYMBOL DETECTOR FOR MIMO SPATIAL MULTIPLEXING SYSTEMS

In this paper, we propose an efficient symbol detection algorithm for multiple-input multiple-output spatial multiplexing (MIMO-SM) systems and present its design and implementation results. By enhancing the error performance of the first detected symbol that causes error propagation, the proposed algorithm achieves a considerable performance gain compared with the conventional sorted QR decomposition (SQRD) based detection and the ordered successive detection (OSD) algorithms. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by a simulation. In the case of a 16QAM MIMO-SM system with 4 transmit and 4 receive (4 × 4) antennas, at BER = 10-3 the proposed algorithm results in a gain improvement of about 2.5–13.5 dB over the previous algorithms. The proposed detection algorithm was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18 μm 1.8 V CMOS standard cell library. The results show that the proposed algorithm can be implemented without increasing the hardware costs significantly.

SAT based timing analysis for fixed and rise/fall gate delay models

This paper proposes a SAT based technique for timing analysis by an accurate modeling of event propagation within gate-level circuits. The accuracy of the result depends on the level of detail with which circuit activity is modeled. However, the combinatorial blowup in the size and complexity of the problem is the main bottleneck in any detailed modeling. The proposed technique overcomes this problem by an efficient SAT modeling of events at the nodes of the circuit which scales very smoothly with increase in size of the circuit without sacrificing on accuracy even with industry standard gate delays of 0.01ns granularity. This improvement in performance enables the modeling of more complex gate delay models like the rise/fall delay model which can simulate circuit activity more realistically than the fixed gate delay model.

Site-Specific Analysis of Advanced Packaging Enabled by Focused Ion Beams

Abstract Packaging integration continues to increase in complexity, driving more samples into FA labs for development support and analysis. For many of the jobs, there is also a need for larger removal volumes, compounding the demand for tool time and throughput. Focused ion beam (FIB) and dual-beam FIB/SEM systems are helping to relieve the pressure with their ability to create site-specific cross sections and to facilitate gate-level circuit rewire and debug. This article reviews the impact of packaging trends on failure analysis along with recent improvements in FIB technology. It also presents examples that illustrate how these new FIB techniques are being applied to solve emerging packaging challenges.

The Inclusive-AND (Equivalence, Exclusive-NOR (EXNOR, XNOR)) and Exclusive-OR (EXOR, XOR) Gates in Mixed Logic

Mixed logic notation simplifies the analysis and design of digital circuits and supports self-documenting gate level circuits. Additionally, it provides alternative implementations which could result in reducing the number of gates. The current symbol of the Equivalence gate as an Exclusive OR with the output ASSERTED LOW (Exclusive NOR) is troubling when we want to think of the output ASSERTED HIGH. This had impeded extending the mixed logic approach to Exclusive OR. We suggest introducing an alternative distinct symbol for the Equivalence (Inclusive-AND) gate to facilitate the application of the mixed logic concepts to both the Exclusive-OR and the Inclusive-AND gates.

Implementation and Analysis of Probabilistic Methods for Gate-Level Circuit Reliability Estimation

The development of VLSI technology results in the dramatically improvement of the performance of integrated circuits. However, it brings more challenges to the aspect of reliability. Integrated circuits become more susceptible to soft errors. Therefore, it is imperative to study the reliability of circuits under the soft error. This paper implements three probabilistic methods (two pass, error propagation probability, and probabilistic transfer matrix) for estimating gate-level circuit reliability on PC. The functions and performance of these methods are compared by experiments using ISCAS85 and 74-series circuits.

Active mode leakage reduction using fine-grained forward body biasing strategy

Leakage power minimization has become an important issue with technology scaling. Variable threshold voltage schemes have become popular for standby power reduction. In this work we look at another emerging aspect of this potent problem which is leakage power reduction in active mode of operation. In gate level circuits, a large number of gates are not switching in active mode at any given point in time but nevertheless are consuming leakage power. We propose a fine-grained forward body biasing (FBB) scheme for active mode leakage power reduction in gate level circuits without any delay penalty. Our results show that our optimal polynomial time FBB allocation algorithm results in 70.2% reduction in leakage currents. We also present an exact standard-cell placement driven FBB allocation algorithm that effectively reduces the area penalty using the post-placement area slack and results in 56.5%, 62.8% and 66.1% reduction in leakage currents for 0%, 4% and 8% area slack, respectively. Furthermore, we present a heuristic to solve the standard-cell placement driven FBB allocation problem that is computationally efficient and results in leakage within 2% of that from the exact formulation.