A fast model for analysis and improvement of gate-level circuit reliability

Abstract

Reliability is becoming one of increasingly critical issues for design of modern integrated circuits, due to the continuous scaling of CMOS technology and emerging nano-scale devices. This paper presents a novel method for reliability analysis in combinational circuits with unreliable devices. By using the concept of equivalent reliability, the proposed method promises improvements over the state-of-the-art methods in terms of efficiency, while keeping a high level of accuracy, in estimating the circuit reliability. This efficiency is achieved due to the fact that this work utilizes input probabilities and gate reliabilities directly for reliability evaluation, instead of taking (or sampling) a huge number of input vectors as with most existing approaches. Simulation results on benchmark circuits show that our approach obtains a significant speedup over other existing methods, especially when the reliability evaluation is repetitively needed for a same circuit in order to provide the reliability improvement for reliability-driven design applications.