While hysteretic effects upon gate sweeps in carbon nanotube transistors can be useful for memory devices, they may hamper the reliable readout of CNFET-based sensors. Here, we demonstrate the use of our recent hysteresis-free, suspended nanotube transistor fabrication method to evaluate the influence of dielectric layers on gate characteristics. The atomic layer deposition of Al2O3 induced substantial hysteresis in a previously hysteresis-free device. The extraction of electrical device properties before and after an individual processing step provides an insight into the fundamental issue of hysteresis, which is of particular relevance for nanoscale devices with electrical field-strength enhancement due to nanoscale dimensions. Gate hysteresis appears after atomic layer deposition of Al2O3 onto the previously hysteresis-free carbon nanotube transistor.