Intrinsic doping and gate hysteresis in graphene field effect devices fabricated onSiO2 substrates

Abstract

We have studied the intrinsic doping level and gate hysteresisof graphene-based field effect transistors (FETs) fabricated overSi/SiO2 substrates. It was found that the high p-doping level of graphene in some as-prepareddevices can be reversed by vacuum degassing at room temperature or abovedepending on the degree of hydrophobicity and/or hydration of the underlyingSiO2 substrate. Charge neutrality point (CNP) hysteresis, consisting of the shift of thecharge neutrality point (or Dirac peak) upon reversal of the gate voltage sweepdirection, was also greatly reduced upon vacuum degassing. However, another type ofhysteresis, consisting of the change in the transconductance upon reversal of thegate voltage sweep direction, persists even after long-term vacuum annealing at200 °C, whenSiO2 surface-bound water is expected to be desorbed. We propose a mechanismfor this transconductance hysteresis that involves water-related defects,formed during the hydration of the near-surface silanol groups in the bulkSiO2, that can act as electron traps.