Gate Hysteresis Research Articles

Impact of interface traps on charge noise and low-density transport properties in Ge/SiGe heterostructures

Hole spins in Ge/SiGe heterostructures have emerged as an interesting qubit platform with favourable properties such as fast electrical control and noise-resilient operation at sweet spots. However, commonly observed gate-induced electrostatic disorder, drifts, and hysteresis hinder reproducible tune-up of SiGe-based quantum dot arrays. Here, we study Hall bar and quantum dot devices fabricated on Ge/SiGe heterostructures and present a consistent model for the origin of gate hysteresis and its impact on transport metrics and charge noise. As we push the accumulation voltages more negative, we observe non-monotonous changes in the low-density transport metrics, attributed to the induced gradual filling of a spatially varying density of charge traps at the SiGe-oxide interface. With each gate voltage push, we find local activation of a transient low-frequency charge noise component that completely vanishes again after 30 hours. Our results highlight the resilience of the SiGe material platform to interface-trap-induced disorder and noise and pave the way for reproducible tuning of larger multi-dot systems.

Analysis and EOT Scaling on Top‐ and Double‐Gate 2D CVD‐Grown Monolayer MoS2 FETs

Abstract2D layered semiconductors have attracted considerable attention for beyond‐Si complementary metal‐oxide‐semiconductor (CMOS) technologies. They can be prepared into ultrathin channel materials toward ultrascaled device architectures, including double‐gate field‐effect‐transistors (DGFETs). This work presents an experimental analysis of DGFETs constructed from chemical vapor deposition (CVD)‐grown monolayer (1L) molybdenum disulfide (MoS2) with atomic layer deposition (ALD) of hafnium oxide (HfO2) high‐k gate dielectrics (top and bottom). This extends beyond previous studies of DGFETs based mostly on exfoliated (few‐nm thick) MoS2 flakes, and advances toward large‐area wafer‐scale processing. Here, significant improvements in performance are obtained with DGFETs (i.e., improvements in ON/OFF ratio, ON‐state current, sub‐threshold swing, etc.) compared to single top‐gate FETs. In addition to multi‐gate device architectures (e.g., DGFETs), the scaling of the equivalent oxide thickness (EOT) is crucial toward improved electrostatics required for next‐generation transistors. However, the impact of EOT scaling on the characteristics of CVD‐grown MoS2 DGFETs remains largely unexplored. Thus, this work studies the impact of EOT scaling on subthreshold swing (SS) and gate hysteresis using current–voltage (I–V) measurements with varying sweep rates. The experimental analysis and results elucidate the basic mechanisms responsible for improvements in CVD‐grown 1L‐MoS2 DGFETs compared to standard top‐gate FETs.

Controllable Synthesis of Transferable Ultrathin Bi2Ge(Si)O5 Dielectric Alloys with Composition-Tunable High-κ Properties.

Two-dimensional (2D) alloys hold great promise to serve as important components of 2D transistors, since their properties allow continuous regulation by varying their compositions. However, previous studies are mainly limited to the metallic/semiconducting ones as contact/channel materials, but very few are related to the insulating dielectrics. Here, we use a facile one-step chemical vapor deposition (CVD) method to synthesize ultrathin Bi2SixGe1-xO5 dielectric alloys, whose composition is tunable over the full range of x just by changing the relative ratios of the GeO2/SiO2 precursors. Moreover, their dielectric properties are highly composition-tunable, showing a record-high dielectric constant of >40 among CVD-grown 2D insulators. The vertically grown nature of Bi2GeO5 and Bi2SixGe1-xO5 enables polymer-free transfer and subsequent clean van der Waals integration as the high-κ encapsulation layer to enhance the mobility of 2D semiconductors. Besides, the MoS2 transistors using Bi2SixGe1-xO5 alloy as gate dielectrics exhibit a large Ion/Ioff (>108), ideal subthreshold swing of ∼61 mV/decade, and a small gate hysteresis (∼5 mV). Our work not only gives very few examples on controlled CVD growth of insulating dielectric alloys but also expands the family of 2D single-crystalline high-κ dielectrics.

Electrical switching of a bistable moiré superconductor.

Electrical control of superconductivity is critical for nanoscale superconducting circuits including cryogenic memory elements1-4, superconducting field-effect transistors (FETs)5-7 and gate-tunable qubits8-10. Superconducting FETs operate through continuous tuning of carrier density, but no bistable superconducting FET, which could serve as a new type of cryogenic memory element, has been reported. Recently, gate hysteresis and resultant bistability in Bernal-stacked bilayer graphene aligned to its insulating hexagonal boron nitride gate dielectrics were discovered11,12. Here we report the observation of this same hysteresis in magic-angle twisted bilayer graphene (MATBG) with aligned boron nitride layers. This bistable behaviour coexists alongside the strongly correlated electron system of MATBG without disrupting its correlated insulator or superconducting states. This all-van der Waals platform enables configurable switching between different electronic states of this rich system. To illustrate this new approach, we demonstrate reproducible bistable switching between the superconducting, metallic and correlated insulator states of MATBG using gate voltage or electric displacement field. These experiments unlock the potential to broadly incorporate this new switchable moiré superconductor into highly tunable superconducting electronics.

All-Aerosol-Jet-Printed Carbon Nanotube Transistor with Cross-Linked Polymer Dielectrics.

The printability of reliable gate dielectrics and their influence on the stability of the device are some of the primary concerns regarding the practical application of printed transistors. Major ongoing research is focusing on the structural properties of dielectric materials and deposition parameters to reduce interface charge traps and hysteresis caused by the dielectric-semiconductor interface and dielectric bulk. This research focuses on improving the dielectric properties of a printed polymer material, cross-linked polyvinyl phenol (crPVP), by optimizing the cross-linking parameters as well as the aerosol jet printability. These improvements were then applied to the fabrication of completely printed carbon nanotube (CNT)-based thin-film transistors (TFT) to reduce the gate threshold voltage (Vth) and hysteresis in Vth during device operation. Finally, a fully aerosol-jet-printed CNT device was demonstrated using a 2:1 weight ratio of PVP with the cross-linker poly(melamine-co-formaldehyde) methylated (PMF) in crPVP as the dielectric material. This device shows significantly less hysteresis and can be operated at a gate threshold voltage as low as -4.8 V with an on/off ratio of more than 104.

Fabrication and characterization of InSb nanosheet/hBN/graphite heterostructure devices

Semiconductor InSb nanosheet/hexagonal boron nitride (hBN)/graphite trilayers are fabricated, and single- and double-gate devices made from the trilayers are realized and characterized. The InSb nanosheets employed in the trilayer devices are epitaxially grown, free-standing, zincblende crystals and are in micrometer lateral sizes. The hBN and graphite flakes are obtained by exfoliation. Each trilayer is made by successively stacking an InSb nanosheet on an hBN flake and on a graphite flake using a home-made alignment stacking/transfer setup. The fabricated single- and double-gate devices are characterized by electrical and/or magnetotransport measurements. In all these devices, the graphite and hBN flakes are employed as the bottom gates and the gate dielectrics. The measurements of a fabricated single bottom-gate field-effect device show that the InSb nanosheet in the device has an electron field-effect mobility of ∼7300 cm2 V−1 s−1 and a low gate hysteresis of ∼0.05 V at 1.9 K. The measurements of a double-gate Hall-bar device show that both the top and the bottom gate exhibit strong capacitive couplings to the InSb nanosheet channel and can thus tune the nanosheet channel conduction effectively. The electron Hall mobility in the InSb nanosheet of the Hall-bar device is extracted to be larger than 1.1 × 104 cm2 V−1 s−1 at a sheet electron density of ∼6.1 × 1011 cm −2 and 1.9 K and, thus, the device exhibits well-defined Shubnikov–de Haas oscillations.

Review-Hysteresis in Carbon Nano-Structure Field Effect Transistor.

In recent decades, the research of nano-structure devices (e.g., carbon nanotube and graphene) has experienced rapid growth. These materials have supreme electronic, thermal, optical and mechanical properties and have received widespread concern in different fields. It is worth noting that gate hysteresis behavior of field effect transistors can always be found in ambient conditions, which may influence the transmission appearance. Many researchers have put forward various views on this question. Here, we summarize and discuss the mechanisms behind hysteresis, different influencing factors and improvement methods which help decrease or eliminate unevenness and asymmetry.

Graphene-Based Sensor for Detection of Bacterial Pathogens.

Microbial colonization to biomedical surfaces and biofilm formation is one of the key challenges in the medical field. Recalcitrant biofilms on such surfaces cause serious infections which are difficult to treat using antimicrobial agents, due to their complex structure. Early detection of microbial colonization and monitoring of biofilm growth could turn the tide by providing timely guidance for treatment or replacement of biomedical devices. Hence, there is a need for sensors, which could generate rapid signals upon bacterial colonization. In this study, we developed a simple prototype sensor based on pristine, non-functionalized graphene. The detection principle is a change in electrical resistance of graphene upon exposure to bacterial cells. Without functionalization with specific receptors, such sensors cannot be expected to be selective to certain bacteria. However, we demonstrated that two different bacterial species can be detected and differentiated by our sensor due to their different growth dynamics, adherence pattern, density of adhered bacteria and microcolonies formation. These distinct behaviors of tested bacteria depicted distinguishable pattern of resistance change, resistance versus gate voltage plot and hysteresis effect. This sensor is simple to fabricate, can easily be miniaturized, and can be effective in cases when precise identification of species is not needed.

In-Place Printing of Flexible Electrolyte-Gated Carbon Nanotube Transistors with Enhanced Stability.

Ion gel-based dielectrics have long been considered for enabling low-voltage operation in printed thin-film transistors (TFTs), but their compatibility with in-place printing (a streamlined, direct-write printing approach where devices never leave the printer mid- or post-process) remains unexplored. Here, we demonstrate a simple and rapid 4-step in-place printing procedure for producing low-voltage electrolyte-gated carbon nanotube (CNT) thin-film transistors at low temperature (80 °C). This process consists of the use of polymer-wrapped CNT inks for printed channels, silver nanowire inks for printed electrodes, and imidazolium-based ion gel inks for printed gate dielectrics. We find that the efficacy of rinsing CNT films and printing an ion gel in-place is optimized using an elevated platen temperature (as opposed to external rinsing or post-process annealing), where resultant devices exhibited on/off-current ratios exceeding 103, mobilities exceeding 10 cm2V-1s-1, and gate hysteresis of only 0.1 V. Additionally, devices were tested under mechanical strain and long-term bias, showing exceptional flexibility and electrochemical stability over the course of 14-hour bias tests. The findings presented here widen the potential scope of print-in-place (PIP) devices and reveal new avenues of investigation for the improvement of bias stress stability in electrolyte-gated transistors.

Gate Bias Stress Instability and Hysteresis Characteristics of InAs Nanowire Field-Effect Transistors.

Because of the excellent electrical properties, III-V semiconductor nanowires are promising building blocks for next-generation electronics; however, their rich surface states inevitably contribute large amounts of charge traps, leading to gate bias stress instability and hysteresis characteristics in nanowire field-effect transistors (FETs). Here, we investigated thoroughly the gate bias stress and hysteresis effects in InAs nanowire FETs. It is observed that the output current decreases together with the threshold voltage shifting to the positive direction when a positive gate bias stress is applied, and vice versa for the negative gate bias stress. For double-sweep transfer characteristics, the significant hysteresis behavior is observed, depending heavily on the sweeping rate and range. On the basis of complementary investigations of these devices, charge traps are confirmed to be the dominant factor for these instability effects. Importantly, the hysteresis can be simulated well by utilizing a combination of the rate equation for electron density and the empirical model for electron mobility. This provides an accurate evaluation of carrier mobility, which is in distinct contrast to the overestimation of mobility when using the transconductance for calculation. All these findings are important for understanding the charge trap dynamics to further enhance the device performance of nanowire FETs.

Investigation of electrical performance and operation stability of RF-sputtered InSnZnO thin film transistors by oxygen-ambient rapid thermal annealing

We investigated the electrical properties and operational stability of amorphous indium-tin-zinc-oxide (a-ITZO) thin-film transistors (TFTs). We fabricated the a-ITZO TFTs using deposition by radio frequency sputtering at room temperature followed by a rapid thermal annealing (RTA) process at different temperatures and oxygen pressure (P O2). This is a more practical annealing route compared to a conventional furnace. Based on film densification and oxygen vacancy optimization, the a-ITZO TFTs exhibited 9.8 cm2 Vs−1, 0.82 V/decade and 1.39 V, for saturation mobility, sub-threshold swing and threshold voltage, respectively. Operation stability tests and hysteresis behavior of a-ITZO TFTs suggest that oxygen vacancy concentration of a-ITZO thin films gradually decreases under higher P O2, consequently affecting the threshold voltage and the shift seen after a gate bias stress test. This observation suggests that gate bias stress and hysteresis stability of an a-ITZO device is due to the effect of oxygen-controlled pressure in the RTA process. This a-ITZO TFTs electrical characterization qualitatively coincides with x-ray photoelectron spectroscopic analyses of oxygen vacancy concentration in a-ITZO thin films. Thus, our systematic a-ITZO thin film optimization using the oxygen-ambient RTA process is a practical basis for high-performance amorphous oxide semiconductor TFT post-annealing methods.

The origin of gate bias stress instability and hysteresis in monolayer WS2 transistors

Due to the ultra-thin nature and moderate carrier mobility, semiconducting two-dimensional (2D) materials have attracted extensive attention for next-generation electronics. However, the gate bias stress instability and hysteresis are always observed in these 2D materials-based transistors that significantly degrade their reliability for practical applications. Herein, the origin of gate bias stress instability and hysteresis for chemical vapor deposited monolayer WS2 transistors are investigated carefully. The transistor performance is found to be strongly affected by the gate bias stress time, sweeping rate and range, and temperature. Based on the systematical study and complementary analysis, charge trapping is determined to be the major contribution for these observed phenomena. Importantly, due to these charge trapping effects, the channel current is observed to decrease with time; hence, a rate equation, considering the charge trapping and time decay effect of current, is proposed and developed to model the phenomena with excellent consistency with experimental data. All these results do not only indicate the validity of the charge trapping model, but also confirm the hysteresis being indeed caused by charge trapping. Evidently, this simple model provides a sufficient explanation for the charge trapping induced gate bias stress instability and hysteresis in monolayer WS2 transistors, which can be also applicable to other kinds of transistors.

Exfoliated hexagonal BN as gate dielectric for InSb nanowire quantum dots with improved gate hysteresis and charge noise

We characterize InSb quantum dots induced by bottom finger gates within a nanowire that is grown via the vapor–liquid–solid process. The gates are separated from the nanowire by an exfoliated 35 nm thin hexagonal BN flake. We probe the Coulomb diamonds of the gate-induced quantum dot exhibiting a charging energy of ∼2.5 meV and orbital excitation energies up to 0.3 meV. The gate hysteresis for sweeps covering 5 Coulomb diamonds reveals an energy hysteresis of only 60 μeV between upward and downward sweeps. Charge noise is studied via long-term measurements at the slope of a Coulomb peak revealing a potential fluctuation of ∼1 μeV/Hz at 1 Hz. This makes h-BN a dielectric with the currently lowest gate hysteresis and lowest low-frequency potential fluctuations reported for low-gap III–V nanowires. The extracted values are similar to state-of-the-art quantum dots within Si/SiGe and Si/SiO2 systems.

Facile Photo-cross-linking System for Polymeric Gate Dielectric Materials toward Solution-Processed Organic Field-Effect Transistors: Role of a Cross-linker in Various Polymer Types.

Energy-efficient solution-processed organic field-effect transistors (OFETs) are highly sought after in the low-cost printing industry as well as for the manufacture of flexible and other next-generation devices. The fabrication of such electronic devices requires high-functioning insulating materials that are chemically and mechanically robust to avoid lowering insulating properties during the device fabrication process or utilization of devices. In this study, we report a facile, fluorinated, UV-assisted cross-linker series using a fluorophenyl azide (FPA), which reacts with the C-H groups of a conventional polymer. This demonstrates the application of the cross-linked films in OFET gate dielectrics. The effects of the cross-linkable chemical structure of the FPA series on the cross-linking chemistry, photopatternability, and dielectric properties of the resulting films are investigated for low/high-k or amorphous/crystalline polymeric gate dielectric materials. The characteristics of insulating layers and behavior of OFETs containing these cross-linked gate dielectrics (for example, leakage current density (J), hysteresis, and charge trap density) depend on the polymer type. Furthermore, an organic-based complementary inverter and various printable OFETs with excellent electrical characteristics are successfully fabricated. Thus, these reported cross-linkers that enable the solution process and patterning of well-developed conventional polymer dielectric materials are promising for the realization of a more sustainable next-generation industrial technology for flexible and printable devices.

Carbon Nanotube Transistors as Gas Sensors: Response Differentiation Using Polymer Gate Dielectrics

The high sensitivity of carbon nanotube devices as gas sensors is generally attributed to the large surface area of the material, whereas selectivity is often imparted by the “lock-and-key” mechanism. In contrast with this picture, where little function is conferred to the underlying substrate, we demonstrate that bottom gate carbon nanotube network field-effect transistors (CNN-FETs) fabricated on a variety of polymer dielectrics, but with the same pristine carbon nanotubes, show differentiated responses to analytes. Interaction with the environment thus occurs not only directly with carbon nanotubes but is often mediated by the substrate. In a broad survey of polymers, we identify several materials suitable as the gate dielectric of printed devices and that yield a vanishing gate hysteresis in ambient air. The other two classes of polymers that induce a lagging or advancing hysteresis in CNN-FETs are found desirable for gas sensing applications. Moreover, we have tested CNN-FETs with different polymer g...

Flexible, Print-in-Place 1D-2D Thin-Film Transistors Using Aerosol Jet Printing.

Semiconducting carbon nanotubes (CNTs) printed into thin films offer high electrical performance, significant mechanical stability, and compatibility with low-temperature processing. Yet, the implementation of low-temperature printed devices, such as CNT thin-film transistors (CNT-TFTs), has been hindered by relatively high process temperature requirements imposed by other device layers-dielectrics and contacts. In this work, we overcome temperature constraints and demonstrate 1D-2D thin-film transistors (1D-2D TFTs) in a low-temperature (maximum exposure ≤80 °C) full print-in-place process (i.e., no substrate removal from printer throughout the entire process) using an aerosol jet printer. Semiconducting 1D CNT channels are used with a 2D hexagonal boron nitride (h-BN) gate dielectric and traces of silver nanowires as the conductive electrodes, all deposited using the same printer. The aerosol jet-printed 2D h-BN films were realized via proper ink formulation, such as utilizing the binder hydroxypropyl methylcellulose, which suppresses redispersion between adjacent printed layers. In addition to an ON/OFF current ratio up to 3.5 × 105, channel mobility up to 10.7 cm2·V-1·s-1, and low gate hysteresis, 1D-2D TFTs exhibit extraordinary mechanical stability under bending due to the nanoscale network structure of each layer, with minimal changes in performance after 1000 bending test cycles at 2.1% strain. It is also confirmed that none of the device layers require high-temperature treatment to realize optimal performance. These findings provide an attractive approach toward a cost-effective, direct-write realization of electronics.

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p-channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage (Vth) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al2O3) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep Vth shift (ΔVth) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.

Enhanced Device Stability of Ionic Gating Molybdenum Disulfide Transistors

The application of ion gels as gate dielectrics having an excellent mechanical flexibility and high capacitance to molybdenum disulfide (MoS2) devices has been extensively studied; however, some issues remain unaddressed with regard to device stability such as gate leakage current, hysteresis, and bias stress instability. This study suggests a fabrication process for the ionic gating of the MoS2 device to enhance the device stability by laminating the ion gel film onto the MoS2 transistor using a cut‐and‐stick method and adding a passivation layer to remove unintentional parasitic capacitances generated by the capacitive coupling effect. The ionic gating MoS2 transistor fabricated via this process operates at a low voltage (<1 V) and exhibits superior electrical characteristics such as low gate leakage currents (≈10−11 A), high on–off ratio (>106), and low hysteresis (<0.05 V). To further investigate the device stability, bias stress instability of the ionic gating MoS2 transistor is examined. The charge‐trapping mechanism is the main cause of threshold voltage shifts under gate bias stress.

Enhancement-mode AlGaN channel high electron mobility transistor enabled by p-AlGaN gate

This work exhibits the ability to shift the threshold voltage of an Al0.45Ga0.55N/Al0.3Ga0.7N high electron mobility transistor through the implementation of a 100 nm thick p-Al0.3Ga0.7N gate. A maximum threshold voltage of +0.3 V was achieved with a 3 μm gate length. In addition to achieving enhancement-mode operation, this work also shows the capability to obtain high saturated drain current (>50 mA/mm), no gate hysteresis, high ION,MAX/IOFF,MIN ratio of >109, and exceptionally low gate leakage current of 10−6 mA/mm even under high forward bias of Vgs = 8 V.

Stability Improvement of Nitrogen Doping on IGO TFTs under Positive Gate Bias Stress and Hysteresis Test

Thin-film transistors (TFTs) using indium-gallium-oxide (IGO) semiconductor materials as channel layers were fabricated. In this study, nitrogen was introduced in the process of channel deposition to investigate its effect on device performance. The experimental results showed that moderate nitrogen doping can significantly improve the device stability under positive gate bias stress owing to the reduction of oxygen vacancies. Furthermore, for the purpose of understanding the influence of different doping levels, the nitrogen doping ratio was modulated in ascending order from 0 sccm to 5 sccm. Among the fabricated c-IGO TFTs, the one with 2 sccm nitrogen doping exhibited the least threshold voltage shift. In addition, the hysteresis measurement further confirmed that the interface traps between the channel and the dielectric were significantly passivated in nitrogen-doped TFT. In this regard, the method of in-situ nitrogen doping was certified to serve an efficient way of fabricating a passivation-free TFT and improve the device stability simultaneously.