Equivalent Gate Research Articles

An efficient VLSI architecture of VLD for AVS HDTV decoder

In this paper, we present a VLSI design of variable length code decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode fixed length code, unsigned or signed k-th Exp-Golomb code, and AVS 2-D variable length code. Furthermore, it has a pre-processing submodule, which can perform start code detection and de-stuffing for the input bitstream. The proposed architecture has been described in Verilog HDL, simulated with VCS digital simulator, and implemented using 0.18 /spl mu/ Artisan CMOS cells library by synopsys design compiler. The circuit costs about 15k equivalent logic gates (not including 4 kb on-chip SRAM). And the critical path is less than 6 ns in the worst case. This design has been implemented in a single chip AVS HDTV decoder, AVS101, which can support real-time decoding for NTSC, PAL, 720p 60 frames/s or 1080i 60 fields/s programs. Although the architecture was originally designed for AVS video standard, it can be easily adapted to other coding standards.

Thermal Degradation of HfSiON Dielectrics Caused by TiN Gate Electrodes and Its Impact on Electrical Properties

We studied thermal reactions in TiN/HfSiON gate stacks and discussed their impact on electrical properties. Physical analysis revealed that reactions at the metal/high-k interface form a polycrystalline TiO2 layer at 700 °C. The interface between the TiN electrode and the ultrathin TiO2 interlayer remained smooth and the formation of this high-permittivity metal oxide layer did not cause any electrical degradation in terms of equivalent oxide thickness (EOT) versus gate leakage (Ig) characteristics. However, interface roughness and electrical degradation, such as increases in electrical thickness and interface-trap density, were present after annealing at 900 °C. At 1100 °C, we observed marked increases in EOT and Ig, which respectively indicated oxide (SiO2) growth at the bottom interface and dielectric degradation both of the interface TiO2 and HfSiON layers.

Low-frequency noise in TaSiN/HfO/sub 2/ nMOSFETs and the effect of stress-relieved preoxide interfacial layer

Low-frequency noise characteristics are reported for TaSiN-gated n-channel MOSFETs with atomic-layer deposited HfO/sub 2/ on thermal SiO/sub 2/ with stress-relieved preoxide (SRPO) pretreatment. For comparison, control devices were also included with chemical SiO/sub 2/ resulting from standard Radio Corporation of America clean process. The normalized noise spectral density values for these devices are found to be lower when compared to reference poly Si gate stack with similar HfO/sub 2/ dielectric. Consequently, a lower oxide trap density of /spl sim/4/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ is extracted compared to over 3/spl times/10/sup 18/ cm/sup -3/eV/sup -1/ values reported for poly Si devices indicating an improvement in the high-/spl kappa/ and interfacial layer quality. In fact, this represents the lowest trap density values reported to date on HfO/sub 2/ MOSFETs. The peak electron mobility measured on the SRPO devices is over 330 cm/sup 2//V/spl middot/s, much higher than those for equivalent poly Si or metal gate stacks. In addition, the devices with SRPO SiO/sub 2/ are found to exhibit at least /spl sim/10% higher effective mobility than RCA devices, notwithstanding the differences in the high-/spl kappa/ and interfacial layer thicknesses. The lower Coulomb scattering coefficient obtained from the noise data for the SRPO devices imply that channel carriers are better screened due to the presence of SRPO SiO/sub 2/, which, in part, contributes to the mobility improvement.

Reliable extraction of cycling induced interface states implementing realistic P/E stresses in reference cell: comparison with flash memory cell

The cycling induced interface states in floating-gate EEPROM cells are reliably extracted by implementing accurate program/erase stresses in the reference cell. The interface states measured directly from the memory cell via charge pumping are shown different from those obtained conventionally from the reference cell. The reasons for these different levels of extraction are elucidated and a new method is presented for accurate determination of interface trap density. The technique is based on introducing the equivalent gate voltage with offset voltage at the reference cell by which to simulate realistically the cycling stresses as occur in the flash memory cell itself.

Design and implementation of a Java processor

Java is widely applied in current embedded systems due to its object-oriented features and advantages such as security, robustness, and platform independence. A Java virtual machine is needed to execute Java programs. However, in most of the existing solutions to Java virtual machines, the overhead of executing object-oriented related instructions is significant and becomes the bottleneck of system performance. To solve this problem, a novel Java processor called jHISC is proposed, which mainly targets J2ME and embedded applications. In jHISC, the object-oriented related instructions are implemented by hardware directly, as a hardware-readable data structure is used to represent the object. The complete system with 4 kB instruction cache and 8 kB data cache is described by VHDL and implemented in a Xilinx Virtex FPGA. It occupies 601 859 equivalent gates and the maximum clock frequency of the system is about 30 MHz. Compared with PicoJava II, the overall performance is speeded up 1 to 7.4 times and the execution efficiency of object-oriented related bytecodes is improved by 0.91 to 13.2 times for the same clock frequency.

Optimizing Hardware Function Evaluation

We present a methodology and an automated system for function evaluation unit generation. Our system selects the best function evaluation hardware for a given function, accuracy requirements, technology mapping, and optimization metrics, such as area, throughput, and latency. Function evaluation f(x) typically consists of range reduction and the actual evaluation on a small convenient interval such as [0, /spl pi//2) for sin(x). We investigate the impact of hardware function evaluation with range reduction for a given range and precision of x and f(x) on area and speed. An automated bit-width optimization technique for minimizing the sizes of the operators in the data paths is also proposed. We explore a vast design space for fixed-point sin(x), log(x), and /spl radic/x accurate to one unit in the last place using MATLAB and ASC, a stream compiler for field-programmable gate arrays (FPGAs). In this study, we implement over 2,000 placed-and-routed FPGA designs, resulting in over 100 million application-specific integrated circuit (ASIC) equivalent gates. We provide optimal function evaluation results for range and precision combinations between 8 and 48 bits.

MOSFET optimization in deep submicron technology for charge amplifiers

The optimization of the input MOSFET for charge amplifiers in deep submicron technologies is discussed. After a review of the traditional approach, the impact of properly modeling the equivalent series noise and gate capacitance of the MOSFET is presented. It is shown that the enhanced MOSFET model, when compared to the classical, produces a different resolution estimate and input MOSFET optimization result. The minimum channel length and the maximum allocated power are not always the best choice in terms of resolution. Also, in an optimized front-end, the low frequency noise contribution to the Equivalent Noise Charge may depend on the time constant of the filter. As an example, results from the commercial TSMC 0.25 mum CMOS technology are reported

Modeling the partition of noise from the gate-tunneling current in MOSFETs

Expressions for the spectral densities of the gate/source and gate/drain noise currents caused by current flow through the gate oxide of MOSFETs are derived. It is shown that these noise currents can also be expressed in terms of equivalent gate and drain noise currents, and by linearizing the position dependence of the gate current density, simple analytic expressions for these equivalent noise currents and their correlation are obtained in terms of the total gate current and the drain/source partition ratio. It is also shown that the predictions of this simple theory are consistent with published experimental data and results from numerical simulations.

Model to Predict Gate Tunneling Current of Plasma Oxynitrides

Two key parameters for silicon MOSFET scaling, equivalent oxide thickness (EOT) and gate leakage current density (J/sub g/) are measured and modeled for silicon oxynitride (Si-O-N) gate dielectrics formed by plasma nitridation of SiO/sub 2/. It is found that n-MOSFET inversion J/sub g/ is larger than p-MOSFET inversion J/sub g/ when the gate dielectric consists of less than 27% nitrogen atoms, indicating substrate injection of electrons is dominant for this range of plasma nitrided Si-O-N. To examine the intrinsic scaling of Si-O-N, we model EOT and n-MOSFET J/sub g/ for sub-2-nm physically thick gate dielectrics as a function of film physical thickness and nitrogen content. The model has four free fitting parameters and unlike existing models does not assume a priori the values of the oxide and nitride dielectric constant, barrier height, or effective mass. It indicates that at a given EOT, leakage current of n-MOSFETs with Si-O-N gate dielectrics reaches a minimum at a specific nitrogen content. Through the use of this model, we find that plasma nitrided Si-O-N can meet the 65-nm International Technology Roadmap for Semiconductors specifications for J/sub g/, and we estimate the nitrogen concentration required for each node and application.

Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology

High-κ gate dielectrics and metal gate electrodes are required for enabling continued equivalent gate oxide thickness scaling, and hence high performance, and for controlling gate oxide leakage for both future silicon and emerging non-silicon nanoelectronic transistors. In addition, high-κ gate dielectrics and metal gates are required for the successful demonstration of high performance logic transistors on high-mobility non-silicon substrates with high ION/IOFF ratios.

Application of high-K gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology

High-k gate dielectrics and metal gate electrodes are required for enabling continued equivalent gate oxide thickness scaling, and hence high performance, and for controlling gate oxide leakage for...

IEEE P1647 and P1800: two approaches to standardization and language design

Verification is currently the hot topic in EDA. The move to deep-submicron feature sizes in the latest IC designs has caused a paradigm shift, moving the emphasis from design to verification. Designers must create ICs with upwards of 50 million equivalent gates and still meet cost and time-to-market constraints. To do this, they are limiting new logic to a minimum and relying heavily on the reuse of existing functional blocks and embedded memory to create the required chip functionality. This trend puts even more pressure on the already difficult problem of verifying these massive chips. To cope with these increased demands, chip designers, and therefore the EDA industry, have moved to using specialized languages and tools that improve the efficiency of the verification process. Previously, verification involved writing a testbench in a hardware description language (HDL) such as Verilog (IEEE-1364) or VHDL (IEEE-1076). By using the same language for design and verification, the processes tend to be a continuum rather than distinct parts. This is a simple mechanism seemingly not requiring additional training, but it has serious shortcomings when applied to very complex problems. Large projects tend to use specialized languages and, in many cases, separate teams of verification engineers working independently from the design team. Two verification languages emerged in the mid-1990s: Verisity's e and System Science's Vera. These two languages have followed two very different paths.

CORDIC-based architecture with channel state information for OFDM baseband receiver

An efficient architecture for OFDM baseband receiver based on coordinate rotation digital computer (CORDIC) algorithm is proposed with channel state information (CSI). Two dual-mode CORDIC modules are designed for synchronization and equalization. A modified demapping method using CSI helps to provide sub-channel status, and therefore decreases the packet error rates especially for some sub-channels with extremely low SNR. A combined algorithm suitable for CORDIC is proposed for not only the estimation and compensation of channels but synchronization for carrier frequency offset and sampling clock offset. Allocation, timing analysis and complexity for all functional blocks in the receiver are proposed, including front-end processing, FFT, inner receiver, and outer receiver. Complete tests for packet error rate are simulated under an integrated platform considering of RF front-end non-ideal parameters, filters, quantization, and channel models. Simulation results of practical circuits on AWGN and channel models are presented and prove the improvement of the receiver. The design occupies about 424 k equivalent gate count and 7.3 mm/sup 2/ core size in 0.18-/spl mu/m CMOS.

Thermally robust TaTb/sub x/N metal gate electrode for n-MOSFETs applications

In this letter, we study Terbium (Tb)-incorporated TaN (TaTb/sub x/N) as a thermally robust N-type metal gate electrode for the first time. The work function of the Ta/sub 0.94/Tb/sub 0.06/N/sub y/ metal gate is determined to be /spl sim/4.23 eV after rapid thermal anneal at 1000/spl deg/C for 30 s, and can be further tuned by varying the Tb concentration. Moreover, the TaTb/sub x/N-SiO/sub 2/ gate stack exhibits excellent thermal stability up to 1000/spl deg/C with no degradation to the equivalent oxide thickness, gate leakage, and time-dependent dielectric breakdown (TDDB) characteristics. These results suggest that Tb-incorporated TaN (TaTb/sub x/N) could be a promising metal gate candidate for n-MOSFET in a dual-metal gate Si CMOS process.

AES implementation on a grain of sand

The authors present a hardware implementation of the advanced encryption standard (AES) which is optimised for low-resource requirements. The standard-cell implementation on a 0.35 µm CMOS process from Philips Semiconductors occupies an area of only 0.25 mm2. This compares roughly to 3400 gate equivalents or to the size of a small grain of sand. The authors believe that this size will serve for a long time as a reference for AES-128 implementations that support encryption and decryption including key setup. Their manufactured silicon implementation is fully operational. Measurements verified the excellent performance predicted by simulation. The maximum clock frequency of 80 MHz allows a data throughput rate of 9.9 Mbps. Besides low-resource optimisation, the circuit is optimised for low-power operation. For use in low-throughput applications, the AES module draws only a current of 3.0 µA when operated at 100 kHz and 1.5 V. This nearly ignorable power consumption in combination with the extreme area efficiency allows new fields of applications for AES which were beyond imagination before.

Efficient Realization of Parity Prediction Functions in FPGAs

In this paper, we propose an AND/XOR-based technology mapping method for efficient realization of parity prediction functions in field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve an excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as parity prediction functions, efficiently. We conduct experiments using the parity prediction functions with respect to MCNC benchmark circuits. With the proposed approach, the number of configurable logic blocks (CLBs) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), respectively. The total equivalent gate counts are reduced by 65.5%, maximum combinational path delay is reduced by 56.7%, and maximum net delay is reduced by 80.5% compared to conventional methods.

A low-power DS-CDMA RAKE receiver utilizing resource allocation techniques

This paper presents architectural and implementation innovations made to realize a self-contained front-end processor for any DS-CDMA-based system. At the heart of the ASIC is a highly flexible RAKE processing engine that utilizes a unique resource allocation technique for maximum flexibility. The front-end of the chip consists of a matched filter and an all digital timing and frequency recovery loop based on interpolation and direct digital frequency synthesis (DDFS) techniques. A highly configurable multipath combiner is used to generate the final demodulated symbols by combining contributions from different multipath in a maximal ratio combining scheme. The combiner is also instrumental in performing channel estimation/correction and in closing the loop on the timing and frequency recovery circuits. The chip also features a multipath searcher which performs an energy scan of the wireless channel to decide on new valid multipath. To minimize power consumption and enhance the flexibility of the architecture a unique data tagging technique is utilized to decouple the sampling rate of the incoming data from the processing frequency of different blocks of the ASIC. All resources are programmable via a microcontroller interface that provides firmware control over system resources. Furthermore, the architecture supports the concept of design reuse by enabling simple modular expansion as a means of increasing resources. The resulting layout area is 8.29 mm/sup 2/ in a 0.18-/spl mu/m 1-poly 6-metal CMOS process and consists of 320000 equivalent gates. The core consumes a total of 4.032 mW in a typical load scenario including full demodulation of two RAKE fingers and simultaneous searching for new multipath.

Effect of technology scaling on the 1/ f noise of deep submicron PMOS transistors

A thorough investigation of technology scaling on the 1/ f noise characteristics of pMOSFETs from four advanced CMOS technologies with dual gate oxide thickness is reported for the first time. The results show that the current spectral noise density S Id of thin gate oxide transistors increases by approximately 1–2 orders of magnitude when scaling from 350 to 130 nm. This increase can be attributed to the changeover from thermal oxides to nitrided oxides from 250 nm and below. The magnitude of increase is influenced by the degree of nitridation. In comparison with the thin gate oxide non-nitrided transistors from the 350 nm node, nitridation has increased the S Id of architecturally equivalent thick gate oxide transistors from the 250 nm to 130 nm nodes by a maximum of an order of magnitude. The experimentally observed 1/ f noise trends correlate well with the BSIM3v3 flicker noise model.

The Changing Effect of N 2 / O 2 Gas Flow Rate Ratios on Ultrathin Nitrogen-Enriched Oxynitride Gate Dielectrics

We report the growth of an ultrathin 1.0 nm (equivalent oxide oxynitride gate dielectric by rapid thermal processing (RTP) in high- but low- gas flow ambient. The effect of the changing gas flow ratio on the characteristics of oxynitride films was investigated. High-quality oxynitride film could be formed by RTP in an optimum gas flow ratio of 5/1. Detailed characterization (transmission electron microscopy, J-E capacitance-voltage, stress-induced leakage current, charge-trapping properties) demonstrated the high quality of the oxynitride dielectric and showed that low leakage current density at 1 V, was 1.85 orders of magnitude lower than that of These improvements are attributed to the presence of nitrogen at the interface and in the bulk of the oxynitride. © 2004 The Electrochemical Society. All rights reserved.

Impact of technology scaling on the 1∕f noise of thin and thick gate oxide deep submicron NMOS transistors

This study discusses the composite effect of channel length and gate oxide thickness scaling, coupled with the effect of gate dielectric nitridation on the 1/f noise of minimum channel length NMOS transistors. These transistors have been taken from four advance CMOS technologies with dual gate oxide thickness. The result shows that the current noise spectral density SId of a thin gate oxide transistor increases by approximately 1.5 orders of magnitude when scaling from 350 nm to 130 nm. This increase is closely correlated to the changeover from thermal oxides to nitrided oxides from 250 nm and below. This work also investigates the effect of nitridation on thick gate oxide transistors and compares them to their architecturally equivalent thin gate oxide non-nitrided counterpart from 350 nm technology. The comparison reveals that nitridation has increased the SId of architecturally equivalent thick gate oxide transistors from 250 nm to 130 nm technologies by a maximum of 1.25 orders of magnitude. The experimental 1/f noise trends have been verified with simulations using the BSIM3v3 flicker noise model.