Equivalent Gate Research Articles

Design and Characterization of SEU Hardened Circuits for SRAM-Based FPGA

The mitigation of single-event upset (SEU) in SRAM-based field-programmable gate array (FPGA) is increasingly important as utilization and demand for SRAM-based FPGA dramatically increased in radiation environments such as space. As D flip-flop (DFF) and memory [including block random-access memory (BRAM) and configuration random-access memory (CRAM)] are constituted as the key elements in an FPGA, it is fundamentally necessary to develop radiation hardening techniques targeted for enhanced reliability of DFF and memory. A novel SEU hardened memory design for FPGA is proposed with capabilities of multibit upset protection. We further developed two prototype FPGA chips, one with SEU and the other without SEU hardening for comparison. The FPGA chips are fabricated in a standard 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process and have a volume of three million equivalent logic gates. In terms of SEU cross section, CRAM in the hardened FPGA design is about four orders of magnitude lower than in the unhardened FPGA design, while BRAM demonstrates a reduction by three orders of magnitude. On the conditions of linear energy transfer being up to 14 MeV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot$ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg, no SEU errors were observed from DFF in the hardened FPGA design.

Transistor Count Reduction by Gate Merging

A large set of ASICs uses much more transistors than its necessity, as they use a library of cells with a limited amount of logic functions. This small number of logic functions in a traditional cell library represents an inherent limitation in the optimization of the number of transistors. In modern technologies, static power consumption is related to the number of transistors. To reduce leakage power, it is necessary to optimize the number of transistors. Therefore, it demands the use of a library-free physical design approach, using tools to allow the automatic layout synthesis of any transistor network. The goal of this paper is to present a new method to optimize the logical netlist, willing to reduce the number of transistors and connections, as well as the number of vias. Post-processing of the original logic netlist generated in a traditional design flow is completed, and a set of basic cells is replaced by just one new equivalent logic gate, thus simultaneously reducing the number of transistors. The connected cells of unitary fanout are considered to be merged into a new complex gate (usually not available in a traditional cell library). This approach is capable to reduce the number of transistors of a circuit by 21% on average when compared to the traditional solution, and by 4% when compared to other logic minimization tools. This provides an important leakage power reduction.

An IEEE Single Precision Floating Point Arithmetic-Based Apodization Architecture for Portable Ultrasound Imaging System

Portable ultrasound systems are useful in point-of-care diagnostic. Improving the image contrast and spatial resolution over a large range of imaging depths while maintaining the minimum area and power are the desiderata in case of ultrasound systems. Adaptive apodization is used for obtaining high contrast and spatial resolution ultrasound images; however, the implementation of adaptive apodization in hardware consumes large area and power. In this paper, an adaptive algorithm is presented for obtaining good image contrast and resolution using low computational complexity. In the proposed apodization algorithm, minimum and maximum variance criteria and normalized cross-correlation are used to enhance the image contrast and spatial resolution over a large range of imaging depths. A resource optimized, IEEE single precision arithmetic-based architecture of the proposed method is also presented in this paper. Field II toolbox and the experimental data taken from the plane-wave imaging challenge in medical ultrasound are used for evaluating the performance of the proposed methods. Simulation and experimental results demonstrate that the proposed method provides better resolution coupled with the improved contrast performance than conventional dual apodization with cross-correlation methods. The architecture of the proposed method consumes 358.66-mW dynamic power and 1122.1 k NAND-2 equivalent gates are found to be in UMC 90-nm CMOS standard cell library. Implementation of the proposed method requires the calculation of inverse square root. A quadratic approximation-based inverse square root calculation method and its datapath to support IEEE single precision arithmetic are also presented. The datapath of the inverse square root calculator reduces the memory requirement up to 70% which need to be adopted in pursuit of higher performances.

A 1 Gbps Chaos-Based Stream Cipher Implemented in 0.18 μm CMOS Technology

In this work, a novel chaos-based stream cipher based on a skew tent map is proposed and implemented in a 0.18 μm CMOS (Complementary Metal-Oxide-Semiconductor) technology. The proposed ciphering algorithm uses a linear feedback shift register that perturbs the orbits generated by the skew tent map after each iteration. This way, the randomness of the generated sequences is considerably improved. The implemented stream cipher was capable of achieving encryption speeds of 1 Gbps by using an approximate area of ~ 20 , 000 2-NAND equivalent gates, with a power consumption of 24.1 mW. To test the security of the proposed cipher, the generated keystreams were subjected to National Institute of Standards and Technology (NIST) randomness tests, proving that they were undistinguishable from truly random sequences. Finally, other security aspects such as the key sensitivity, key space size, and security against reconstruction attacks were studied, proving that the stream cipher is secure.

Subthreshold analytical model for dual-material double gate ferroelectric field effect transistor (DMGFeFET)

In this work, an analytical model for dual-material double gate ferroelectric field effect transistor (DMGFeFET) has been developed to investigate the impact of dual-material gate (DMG) and ferroelectric insulator on electrostatic integrity of the device. Landau–Khalatnikov equation along with Poisson’s equation has been used to obtain various parameters such as potential profile distribution, threshold voltage roll-off, drain induced barrier lowering, subthreshold slope etc. The results obtained have been comprehensively compared with equivalent dual-material double gate FET (DMGFET) and it has been demonstrated that DMGFeFET leads to significant improvement in gate controllability as well as substantial reduction in DIBL values. Furthermore, the proposed device exhibits reduction in subthreshold current by 3 orders as compared to conventional DMGFET, thereby implying reduced static power dissipation and efficient device operation. The results obtained using developed model have been validated by numerical simulation results obtained by ATLAS Silvaco tool.

Non-local quantum functions and the distributed Deutsch-Jozsa algorithm

Non-local implementations of quantum gates are a vital part of quantum networks. We find an optimal non-local implementation of quantum functions, the quantum gate equivalent of a switch statement. Then, we apply this result to the Deutsch-Jozsa problem, obtaining a distributed Deutsch-Jozsa algorithm and we show the relative efficiency improvement. As an application, we find a non-cooperative game based upon the original Deutsch-Jozsa problem where a classical agent has at most a 50% probability of winning, while a quantum agent can win every time.

A Fractional-Order Partially Non-Linear Model of a Laboratory Prototype of Hydraulic Canal System.

This article addresses the identification of the nonlinear dynamics of the main pool of a laboratory hydraulic canal installed in the University of Castilla La Mancha. A new dynamic model has been developed by taking into account the measurement errors caused by the different parts of our experimental setup: (a) the nonlinearity associated to the input signal, which is caused by the movements of the upstream gate, is avoided by using a nonlinear equivalent upstream gate model, (b) the nonlinearity associated to the output signal, caused by the sensor’s resolution, is avoided by using a quantization model in the identification process, and (c) the nonlinear behaviour of the canal, which is related to the working flow regime, is taken into account considering two completely different models in function of the operating regime: the free and the submerged flows. The proposed technique of identification is based on the time-domain data. An input pseudo-random binary signal (PRBS) is designed depending on the parameters of an initially estimated linear model that was obtained by using a fundamental technique of identification. Fractional and integer order plus time delay models are used to approximate the responses of the main pool of the canal in its different flow regimes. An accurate model has been obtained, which is composed of two submodels: a first order plus time delay submodel that accurately describes the dynamics of the free flow and a fractional-order plus time delay submodel that properly describes the dynamics of the submerged flow.

Fault-Tolerant Logical Gates in the IBM Quantum Experience.

Quantum computers will require encoding of quantum information to protect them from noise. Fault-tolerant quantum computing architectures illustrate how this might be done but have not yet shown a conclusive practical advantage. Here we demonstrate that a small but useful error detecting code improves the fidelity of the fault-tolerant gates implemented in the code space as compared to the fidelity of physically equivalent gates implemented on physical qubits. By running a randomized benchmarking protocol in the logical code space of the [4,2,2] code, we observe an order of magnitude improvement in the infidelity of the gates, with the two-qubit infidelity dropping from 5.8(2)% to 0.60(3)%. Our results are consistent with fault-tolerance theory and conclusively demonstrate the benefit of carrying out computation in a code space that can detect errors. Although the fault-tolerant gates offer an impressive improvement in fidelity, the computation as a whole is not below the fault-tolerance threshold because of noise associated with state preparation and measurement on this device.

New Encryption technique for improving time and speed for Embedded Applications

Lightweight cryptography is an interesting fieldthat strikes the perfect balance in providing security, higher throughput, lowpower consumption, and compactness. In recent years, many compact algorithms like PRESENT, CLEFIA, SEA, TEA, LED, ZORRO, Hummingbird, and KANTAN have made the mark to be used as lightweight crypto engines. In this paper, we present the design of a new lightweight compact encryption system based on bit permutation instruction group operation (GRP), which is widely studied and extensively researched. Using the S-box of PRESENT, we have added the confusion property for GRP, because all the existing algorithms using bit permutation instructions do not have this confusion property. By comparing the existing S-boxes of compact algorithms and its cryptanalysis, a new hybrid system is proposed in this paper that provides more compact results in terms of both memory space and gate equivalents. A hybrid cryptosystem, which consists of GRP and S-box of PRESENT, is designed and implemented on a 32-bit processor. This fusion has resulted in a lightweight cipher that is the most compact implementation, till now, in terms of memory requirement. We have tested and verified this on an LPC2129 processor. Various S-boxes of recently used lightweight algorithms, such as PRESENT and CLEFIA, are designed and analyzed to create a perfect fusion that should be resistant to attacks. Using the S-box of PRESENT, it helps in further reducing the gate complexity. This hybrid model results in 2125 gate equivalents, which is better than other light variant models like DESXL, CLEFIA, and AES. Moreover, GRP properties are very helpful not only to attain the desired avalanche effect, but also as it results in a compact implementation in hardware. This paper proposes a novel approach that will have a positive impact in the field of lightweight encryption protocols.

Fabrication and Charge Deduction Based Sensitivity Analysis of GaN MOS-HEMT Device for Glucose, MIG, C-erbB-2, KIM-1, and PSA Detection

This paper presents the applicability of a high-resolution AlGaN/AlN/GaN metal oxide semiconductor-high electron mobility transistor (MOS-HEMT) for multiple bio detection and analysis of its sensitivity through a charge deduction based approach. The biomarkers of interest chosen in this paper include c-erbB-2, the breast cancer biomarker whose detection from saliva has been modeled. In this approach, the effective gate bias deduced through the model is applied to the fabricated device. High sensitivity of 0.054 mA/μgmL -1 , about nine times higher than the existing/conventional device, is attained here due to the modification of device epi design and use of MOS-gate. Similarly equivalent gate bias/interface charge has been deduced for other biomarkers such as prostate specific antigen, kidney injury molecule, monokine induced by interferon gamma, and glucose oxidase Enzyme, and effective sensitivities of 0.91 mA/μgmL -1 , 0.254 mA/μgmL -1 , 0.48 mA/ngmL -1 , and 2.06 mA/mmolL -1 , respectively, have been attained. The aim of the paper is developing an analytical model to analyze the sensitivity of the fabricated MOS-HEMT device with Al2O3 as gate dielectric (using on wafer testing) before the real packaging or sample introduction to ensure the device usability as a sensor for a dedicated detection. The methodology used here has been validated by comparison of the device sensitivity with real-time pH detection sensitivity. The device showcases high sensitivity of 1.83 mA/pH. The comparison of sensitivity with existing systems proves that the fabricated device overpowers the existing systems with huge marginal increase in sensitivities attained.

A Modular Multiplier Implemented With Truncated Multiplication

In this brief, we propose a modular multiplication algorithm with four truncated multiplications to reduce the critical path. According to our algorithm, a high-speed 3-stage modular multiplier is constructed. Moreover, synthesized with TSMC 90 nm, our design can perform a 256-bit modular multiplication for every clock period of 3.58 ns with circuit scale of approximately 629K equivalent gates. Further, by utilizing the modular multiplier, an elliptic curves cryptography processor is constructed, and it can perform a scalar multiplication in 19.4 $\mu \text{s}$ , which is one of the fastest to date in published literatures.

Bipartite unitary gates and billiard dynamics in the Weyl chamber

Long time behavior of a unitary quantum gate $U$, acting sequentially on two subsystems of dimension $N$ each, is investigated. We derive an expression describing an arbitrary iteration of a two-qubit gate making use of a link to the dynamics of a free particle in a $3D$ billiard. Due to ergodicity of such a dynamics an average along a trajectory $V^t$ stemming from a generic two-qubit gate $V$ in the canonical form tends for a large $t$ to the average over an ensemble of random unitary gates distributed according to the flat measure in the Weyl chamber - the minimal $3D$ set containing points from all orbits of locally equivalent gates. Furthermore, we show that for a large dimension $N$ the mean entanglement entropy averaged along a generic trajectory coincides with the average over the ensemble of random unitary matrices distributed according to the Haar measure on $U(N^2)$.

Fast Low-Complexity Triple-Error-Correcting BCH Decoding Architecture

An efficient decoding architecture for triple-error-correcting BCH codes is proposed by utilizing a lookup table (LUT) that stores the roots of the error locator polynomial instead of using the Chien search. Two roots of the polynomial equation are precomputed and stored in the LUT in order to relax the hardware complexity. To relax the complexity further, a new method to compress the LUT is additionally proposed. While a large portion of the LUT is filled with unnecessary information in the previous designs, this brief eliminates the redundant information by investigating an algebraic property of the equation. For BCH codes over GF(210), the LUT size is reduced to 18% of the previous work. As a result, the proposed decoding architecture reduces the decoding latency by 38% and the equivalent gate count by up to 40% compared to the previous work, achieving a fast low-complexity triple-error-correcting BCH decoder.

Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs

Manufacturing defects that do not affect the functional operation of low power integrated circuits (ICs) can nevertheless impact their power saving capability. We show that stuck-ON faults on the power switches and resistive bridges between the power networks can impair the power saving capability of power-gating designs. For quantifying the impact of such faults on the power savings of power-gating designs, we propose a diagnosis technique that targets bridges between the power networks. The proposed technique is based on the static power analysis of a power-gating design in stand-by mode and it utilizes a novel on-chip signature generation unit, which is sensitive to the voltage level between power rails, the measurements of which are processed off-line for the diagnosis of bridges that can adversely affect power savings. We explore, through SPICE simulation of the largest IWLS’05 benchmarks synthesized using a 32 nm CMOS technology, the tradeoffs achieved by the proposed technique between diagnosis accuracy and area cost and we evaluate its robustness against process variation. The proposed technique achieves a diagnosis resolution that is higher than 98.6% and 97.9% for bridges of ${R}~{\gtrsim }~{10~{ M}\Omega }$ (weak bridges) and bridges of ${R~\lesssim~10~{ M}\Omega }$ (strong bridges), respectively, and a diagnosis accuracy higher than 94.5% for all the examined defects. The area overhead is small and scalable: it is found to be 1.8% and 0.3% for designs with 27 K and 157 K gate equivalents, respectively.

Arithmetic of $$\tau $$ τ -adic expansions for lightweight Koblitz curve cryptography

Koblitz curves allow very efficient elliptic curve cryptography. The reason is that one can trade expensive point doublings to cheap Frobenius endomorphisms by representing the scalar as a $$\tau $$ -adic expansion. Typically elliptic curve cryptosystems, such as ECDSA, also require the scalar as an integer. This results in a need for conversions between integers and the $$\tau $$ -adic domain, which are costly and hinder the use of Koblitz curves on very constrained devices, such as RFID tags, wireless sensors, or certain applications of the Internet of things. We provide solutions to this problem by showing how complete cryptographic processes, such as ECDSA signing, can be completed in the $$\tau $$ -adic domain with very few resources. This allows outsourcing conversions to a more powerful party. We provide several algorithms for performing arithmetic operations in the $$\tau $$ -adic domain. In particular, we introduce a new representation allowing more efficient and secure computations compared to the algorithms available in the preliminary version of this work from CARDIS 2014. We also provide datapath extensions with different speed and side-channel resistance properties that require areas from less than one hundred to a few hundred gate equivalents on 0.13- $$\upmu $$ m CMOS. These extensions are applicable for all Koblitz curves.

Fast adaptive motion estimation algorithm and its efficient VLSI system for high definition videos

Motion estimation (ME) plays an important part in the functioning of the video codec by identifying and reducing the temporal redundancies in between successive frames of a video sequence. Block matching algorithm (BMA) has been accepted as one of the finest approaches for motion estimation due to its efficiency and ease of implementation. This paper presents a new and improved iterative and adaptive search strategy for block-based motion estimation along with its efficient hardware implementation. Since it is expected that there will be more demand for streaming video services on mobile devices, designing fine tuning algorithm with dedicated efficient hardware would provide significant benefits. The present motion estimation algorithm is adaptive in nature that takes into consideration the motion content of the current frame while predicting the motion vector. The adaptive nature of the search eases the complexity of motion estimation and the algorithm makes use of the correlation present among the motion vectors of the neighboring blocks to lower the number of search position. Traditionally, such adaptive algorithms are executed by CPU cores running a software stack. Since software involves a significant amount of overheads like fetching into cache, branches, stalls etc., the efficiency of the proposed algorithm can be overshadowed by the hardware platform. To avoid this, compact hardware architecture was developed which stands ahead of other existing architectures as shown in comparison. The VLSI design for the proposed algorithm presented in this work deals with the generation of the adaptive search pattern and use of interleaved memory organization fasten the operational speed. A profitable data re-use scheme and involvement of minimum processing elements required for parallelization reduce the on-chip area. Working at a frequency of 243 MHz, the proposed design can process 66 720p HD (1280 × 720) frames in one second consuming an area of 38.2 K gate equivalent. Hence, the proposed design can be incorporated in video codecs to be used in commercial devices like camcorders, smart phones and other portable, battery-powered video consumer devices. The proposed research method achieves significantly improved results both in terms of algorithmic metrics (PSNR) as well hardware performance (speed, area).

Towards Wearability in Cryptographic Systems: A Novel Architecture Based on Rainbow Scheme for Wearable Devices

Wearable devices are examples of the Internet of Things, which often enable objects to exchange data with other connected devices, without requiring human intervention. Since quantum computers have been a potential threat to most of the public cryptographic systems, the data security has been the focuses of the users of wearable devices. Among public cryptographic systems, Multivariate Public Key Cryptography (MPKC) is one of the most popular candidates, which can resist quantum computer attacks. MPKC is based on a NP-hard problem, which includes Rainbow, UOV, enTTS schemes. We propose a novel architecture based on Rainbow scheme for wearable devices, which is one of the most efficient schemes of MPKC. In order to validate our design and verify its effectiveness, an experiment is carried out by using TSMC-0.18 μm standard cell CMOS Application Specific Integrated Circuit, which shows that the executing time of Rainbow is 3.8 ms and its area is 3500 gate equivalents. The results demonstrate that our design is well suit for wearable devices.

Leveraging spectral sparsity to realize enhanced separation of gas-phase ion populations

When coupled with mass spectrometry, gas-phase ion mobility can enable the separation of isomers provided sufficient resolution. However, traditional limits on drift tube ion mobility resolution have been imposed by thermal diffusion and the duration of the initial ion gate pulse width. We demonstrate the first application of a post processing technique, specifically basis pursuit denoising (BPDN), for multiplexed IMS–MS experiments that not only minimizes data acquisition times, but realizes resolutions that exceed traditional predicted values. The multiplexing waveform used was based upon linear frequency modulation of the ion gate producing an ion gate pulsing sequence with a 50% duty cycle. This pulsing sequence further maximizes ion transmission and improved ion statistics in the m/z domain. Traditional, single pulse (signal averaged) and multiplexing IMS acquisitions demonstrate lowered resolution at extended ion gate pulse widths and minimizing this parameter results in decreased sensitivity from gate depletion effects and lowered ion gate duty cycle. Signal processing techniques involving BPDN was demonstrated on experimentally acquired IMS–MS data using the diastereoisomer ractopamine which exhibits two distinct gas-phase conformations with K0 values differing by 0.022cm2V−1s−1. Systematically adjusting the experimental parameters related to effective ion gate pulse width, we illustrate the capacity of this method to yield peak resolutions >1.0 for ion gate pulse widths that routinely yield unresolved arrival time distributions utilizing standard deconvolution procedures or equivalent gate pulse widths that utilize traditional signal averaged IMS datasets. When viewed from the perspective of a single peak, BPDN can increase the observed resolving power by more than a factor of 2. Because resolution and ion throughput are simultaneously maximized, the application of this optimization method represents a fundamentally different approach to multiplexed IMS signal processing.

Design of ultra‐low power AES encryption cores with silicon demonstration in SOTB CMOS process

The design of ultra-low power advanced encryption standard (AES) encryption cores for emerging wireless networks and Internet of things systems by combining optimised architectures, a simple clock gating technique and an advanced 65 nm silicon on thin buried oxide (SOTB) CMOS process is presented. The implementation results show that the proposed 2-Sbox AES encryption core requires the smallest number of clock cycles and achieves the lowest power consumption of 0.4 µW/MHz which is 3.3× lower than that of the best previous presented AES encryption core, with a very small area overhead. Moreover, the proposed 1-Sbox AES encryption core consumes very low hardware resources of 2.4 kgates gate equivalent.

Vector Instruction Set Extensions for Efficient Computation of &lt;sc&gt;Keccak&lt;/sc&gt;

We investigate the design of a new instruction set for the Keccak permutation, a cryptographic kernel for hashing, authenticated encryption, keystream generation and random-number generation. Keccak is the basis of the SHA-3 standard and the newly proposed Keyak and Ketje authenticated ciphers. We develop the instruction extensions for a 128-bit interface, commonly available in the vector-processing unit of many modern processors. We examine the trade-off between flexibility and efficiency, and we propose a set of six custom instructions to support a broad range of Keccak -based cryptographic applications. We motivate our custom-instruction selections using a design space exploration that considers various methods of partitioning the state and the operations of the Keccak permutation, and we demonstrate an efficient implementation of this permutation with the proposed instructions. To evaluate their performance, we integrate a simulation model of the proposed ARM NEON vector instructions into the GEM5 micro-architecture simulator. With this simulation model, we evaluate the performance improvement for several cryptographic operations that use the Keccak permutation. Compared to a state-of-the-art NEON software implementation, we demonstrate a performance improvement of 2.2x for SHA-3. Compared to optimized 32-bit assembly programming, we demonstrate a performance improvement of 2.6x, 1.6x, and 1.4x for River Keyak , Ketje SR and Ketje JR respectively. The proposed instructions require 4,658 gate-equivalent (GE) in 90 nm, which represents only a tiny fraction of the hardware cost of a modern processor.