Equivalent Gate Research Articles

High Resolving Power Electrospray Ionization Ion Mobility Spectrometer Based on Fourier Deconvolution Multiplexing.

The resolving power of the drift tube ion mobility spectrometry (IMS) is mainly dependent on the drift length, the drift voltage, the pulse width of an ion gate, and the pressure inside the drift tube. Electrospray ionization (ESI)-IMS is a highly sensitive and reliable technique for the detection and analysis of nonvolatile compounds, and high resolving power is necessary to separate structurally similar compounds. To improve the analytical performance of atmospheric pressure ESI-IMS, the Fourier deconvolution (FD) multiplexing technique is investigated as an effective and convenient means to improve the resolving power as well as the signal-to-noise ratio. By reducing the equivalent ion gate opening width to 5 μs using a typical Tyndall-Powell ion shutter, a high resolving power RP up to 170 can be achieved with a drift length of 12 cm and a drift voltage of 10 kV. Rhodamine 6G (R6G), sodium dodecyl sulfate (SDS), methacycline, oxytetracycline, and ractopamine were evaluated using the FD-ESI-IMS, and mixtures with similar ion mobility can be well separated without prolonging the drift length.

GFLE: a low-energy lightweight block cipher based on a variant of generalized Feistel structure

Low-energy lightweight block ciphers are essential for applications with extremely resource-constrained to reduce energy and maintain security. The trade-off between diffusion property and area is a widely studied issue in the design of low-energy block ciphers. In this paper, a low-energy lightweight block cipher named as GFLE is presented. The core cipher of GFLE uses a variant of the Generalized Feistel Structure (GFS) with 4-branch, which combines the Type-II GFS with the simplified Lai-Massey. The DRmax of GFLE has a one-round improvement over the Type-II GFS optimized by Suzaki et al and the security margin is achieved in a shorter number of rounds. Moreover, an S-box with low-energy and good cryptographic properties is proposed by searching combinations based on gate-level circuits using a depth-first strategy. It exhibits better security properties and hardware performance compared to other S-boxes. The block cipher GFLE is implemented in ASIC with UMC 0.18 μm. It has been proved that the energy of GFLE is lower than Midori, WARP, SKINNY, CRAFT, etc in unified encryption and decryption (ED) circuits. GFLE reduces energy by 61.59% compared with SKINNY. The results show that GFLE in ED circuits consumes only 1596 Gate Equivalents (GEs) and 6.36 μ J/bit in area and energy, respectively.

Randomness Generation for Secure Hardware Masking – Unrolled Trivium to the Rescue

Masking is a prominent strategy to protect cryptographic implementations against side-channel analysis. Its popularity arises from the exponential security gains that can be achieved for (approximately) quadratic resource utilization. Many variants of the countermeasure tailored for different optimization goals have been proposed. The common denominator among all of them is the implicit demand for robust and high entropy randomness. Simply assuming that uniformly distributed random bits are available, without taking the cost of their generation into account, leads to a poor understanding of the efficiency vs. security tradeoff of masked implementations. This is especially relevant in case of hardware masking schemes which are known to consume large amounts of random bits per cycle due to parallelism. Currently, there seems to be no consensus on how to most efficiently derive many pseudo-random bits per clock cycle from an initial seed and with properties suitable for masked hardware implementations. In this work, we evaluate a number of building blocks for this purpose and find that hardware-oriented stream ciphers like Trivium and its reduced-security variant Bivium B outperform most competitors when implemented in an unrolled fashion. Unrolled implementations of these primitives enable the flexible generation of many bits per cycle, which is crucial for satisfying the large randomness demands of state-of-the-art masking schemes. According to our analysis, only Linear Feedback Shift Registers (LFSRs), when also unrolled, are capable of producing long non-repetitive sequences of random-looking bits at a higher rate per cycle for the same or lower cost as Trivium and Bivium B. Yet, these instances do not provide black-box security as they generate only linear outputs. We experimentally demonstrate that using multiple output bits from an LFSR in the same masked implementation can violate probing security and even lead to harmful randomness cancellations. Circumventing these problems, and enabling an independent analysis of randomness generation and masking, requires the use of cryptographically stronger primitives like stream ciphers. As a result of our studies, we provide an evidence-based estimate for the cost of securely generating n fresh random bits per cycle. Depending on the desired level of black-box security and operating frequency, this cost can be as low as 20 n to 30 n ASIC gate equivalents (GE) or 3 n to 4 n FPGA look-up tables (LUTs), where n is the number of random bits required. Our results demonstrate that the cost per bit is (sometimes significantly) lower than estimated in previous works, incentivizing parallelism whenever exploitable. This provides further motivation to potentially move low randomness usage from a primary to a secondary design goal in hardware masking research.

LPHD: A low power and high diffusion lightweight block cipher

AbstractSmart door locks pose a large number of threats such as network attacks. Its storage area and power of cipher are severely limited because the wireless nodes of smart door locks are mostly battery‐powered. Therefore, effective security solutions are urgently needed. In this paper, a new lightweight block cipher with low power named LPHD is proposed to ensure the security of the master control chip of the smart door lock terminal. We design a scheme of low power S‐box and construct the two‐stage permutation layer (TP structure) suitable for LPHD by filtering the sets of 8‐bit permutations. LPHD proposes a variant of the 8‐branch generalized Feistel structure (GFS) to realize that the bits of all branches are affected in one encryption round. The problem of slow diffusion in the standard Feistel structure is solved. The key schedule adopts the nonlinear design and reuses the encryption process of LPHD. It improves the security of the cipher and reduces hardware overhead. Moreover, we evaluate the hardware implementation and security of LPHD. The results show that LPHD for the unified encryption and decryption circuits requires only 1276 Gate Equivalents (GEs) and 1.914 W on UMC 0.18 m, which is better than other lightweight block ciphers such as SKINNY, PRESENT, and IVLBC. In summary, LPHD provides sufficient security for the master control chip of the smart door lock terminal.

Manipulation of bilayer MoS2-based MESFET with flexoelectric polarization field

We propose a bilayer MoS2-based metal-semiconductor field-effect transistor (MESFET) with the characteristic of mechanical modulation of its performance through flexoelectricity. The MESFET sample is fabricated with the bilayer MoS2 and the Si/SiO2 substrate as well as the gate electrode of Pt and the source/drain electrode of Ag/Au. The current-voltage relationships of the fabricated MESFET under the action of different gate voltages and tip forces as well as their combinations are measured with AFM. The tip force produces a strain gradient induced flexoelectric polarization field and thus changes the effective barrier height of Schottky contact. As a result, it can serve as an equivalent gate voltage, playing a significant tuning role in the performance such as transconductance and carrier mobility of the proposed MESFET. Within the drain-source voltage (VDS) range of 0–2 V, the maximum carrier mobility of the fabricated MESFET under the combined action of traditional gate voltage (VGS) and tip force reach 470 cm−2/(V∙s) significantly higher than that under VGS alone. The study provides valuable insights into the application of flexoelectricity in MESFET devices based on two-dimensional materials.

Electrostatic Gating of Phosphorene Polymorphs.

The ability to directly monitor the states of electrons in modern field-effect transistors (FETs) could transform our understanding of the physics and improve the function of related devices. In particular, phosphorene allotropes present a fertile landscape for the development of high-performance FETs. Using density functional theory-based methods, we have systematically investigated the influence of electrostatic gating on the structures, stabilities, and fundamental electronic properties of pristine and carbon-doped monolayer (bilayer) phosphorene allotropes. The remarkable flexibility of phosphorene allotropes, arising from intra- and interlayer van der Waals interactions, causes a good resilience up to equivalent gate potential of two electrons per unit cell. The resilience depends on the stacking details in such a way that rotated bilayers show considerably higher thermodynamical stability than the unrotated ones, even at a high gate potential. In addition, a semiconductor to metal phase transition is observed in some of the rotated and carbon-doped structures with increased electronic transport relative to graphene in the context of real space Green's function formalism.

DRcipher: A pseudo-random dynamic round lightweight block cipher

The Internet of Things (IoT) has gained popularity in various fields, including components such as embedded devices and wireless sensors. However, ensuring the security of data transmission from these devices is of critical importance. In light of these challenges, a novel lightweight encryption method called DRcipher is proposed in this paper for resource-constrained IoT devices. DRcipher has a 64-bit block size and supports either 96-bit or 128-bit key sizes. In order to improve the security, DRcipher employs a pseudo-random number of encryption rounds determined by the primary key. DRcipher adopts the structure of Generalized Feistel Network (GFN) with 4 branches, and its round functions consist of F-function, FF-function and RP permutation components. In particular, there is a negative feedback mechanism between the FF-function and the overall round of encryption functions. In addition, DRcipher is synthesised using Synopsys Design Compiler version A-2007.12-SP1 and the UMCL18G212T3 standard cell library. DRcipher-96 has an area footprint of 1546 Gate Equivalents (GE), while DRcipher-128 has a slightly larger area footprint of 1646 GE. Moreover, a comprehensive security analysis shows that the proposed DRcipher ensures high-level security redundancy against differential cryptanalysis, linear cryptanalysis, and so on.

Variations of single event transient induced by line edge roughness (LER) and temperature in FinFET

The impacts of line edge roughness (LER) and temperature effect on single event transient (SET) in Silicon-On-Insulator (SOI) FinFET at 14 nm technology node are studied. Based on the calibrated model of the rectangle FinFET, all of possible fin structures induced by LER in the vertical direction are proposed by considering the correlation between the line edges. When an energetic particle hits, due to the corporate effects of the gate control capability from the equivalent gate width and the current density from the cross section, thin fin shape represents more immunity to SET with the relative decrement in current peak, collected charge, deposited charge, pulse width and bipolar amplification coefficient by 23.78 %, 31.61 %, 19.16 %, 23.77 % and 15.40 %, respectively. However, the SET responses of big bottom and fat fin structures indicate that they are more sensitive to SET. Because of the driven current increase induced by the inversion of the temperature effect in FinFET, as the environment temperature increases, the SET responses of all of fin shapes decrease and their relative decrements are close. When the temperature increases from 258K to 398K, the average relative decrements in current peak, and collected charge are 24.22 %, 20.90 %, respectively.

LELBC: A low energy lightweight block cipher for smart agriculture

The massive collection and transmission of various crop and livestock data in smart agriculture leads to serious security concerns. Furthermore, many Internet of Things (IoT) devices in smart agriculture are battery-powered, with limited energy resources. Therefore, a low energy lightweight block cipher (LELBC) is proposed to overcome the data leakage problem during sensor data transmission in smart agriculture. Firstly, a new permutation substitution permutation (PSP) structure is proposed, taking into account the energy resource constraints of unified encryption and decryption (ED) circuits. It has highly consistent encryption and decryption and a good diffusion effect. Secondly, a 4-bit low energy involutive S-box is obtained based on a genetic algorithm. The proposed S-box has lower area and latency compared to the existing S-boxes. The experimental data show that LELBC consumes 1864 gate equivalents (GE) in area and 6.99 μJ/bit in energy (encryption + decryption) under the UMC 0.18μm 1P6M process library. LELBC decreases energy and area consumption by 24.02% and 24.04%, respectively, compared to Midori. Finally, a temperature collection and encryption transmission platform is established. LELBC is deployed on the platform to encrypt the collected data, establishing the first line of defense for the secure transmission of smart agriculture sensor data.

HDLBC: A lightweight block cipher with high diffusion

Both the diffusion property and the area consumption are two important evaluation criteria in the design and implementation of symmetric encryption algorithms. Many AND-Rotation-XOR (AND-RX) block ciphers are usually designed by reducing the diffusion property to minimize the area consumption. On the other hand, these AND-RX block ciphers use multiple round function operations to achieve the enough diffusion property, which always induce more area consumption in their hardware implementation. How to trade off the diffusion property and the area consumption appears to be an interesting task in the design of block cipher. In this paper, HDLBC as a new family of lightweight block cipher (with 64-bit plaintext and 64-bit/128-bit key) for the Internet of Things (IoT) is proposed. More specifically, the HDLBC is designed by using only two F-functions (RA1 and RA2), where the non-linear layer of the F-functions is constructed by the NAND operation that consumes the least area among the non-linear logic operations. To the best of our knowledge, HDLBC cipher requires the minimum number of F-functions to provide the diffusion property, where the F-functions require fewer implementation resources than the F-functions of existing similar encryption algorithms. It illustrates the hardware implementation of HDLBC cipher on SMIC 0.18μm requires only 1248 Gate Equivalents (GEs), its throughput rate is 256 Kbps at 100 KHz. Compared with other encryption algorithms, the implementation performance of HDLBC cipher achieves well-balanced in both the area consumption and diffusion property. Moreover, the security analysis shows that HDLBC cipher has enough security margin against various known attacks, such as differential cryptanalysis, linear cryptanalysis, impossible differential cryptanalysis, zero correlation cryptanalysis, etc.

Multiple-Controlled Toffoli and Multiple-Controlled Fredkin Reversible Logic Gates-Based Reversible Synchronous Counter Design

The counters that change their transition using a clock signal are called synchronous counters. While designing a synchronous counter circuit, the power consumption and the delay are the major issues. Several synchronous counters were designed previously with the help of flip flops, but they did not provide good results. The existing synchronous counters increased power consumption and delay and decreased the speed. To overcome these issues, in this manuscript, a reversible synchronous counter is designed utilizing Multiple-Controlled Toffoli (MCT) and Multiple-Controlled Fredkin (MCF) reversible logic gates. Here, three JK flip-flop designs, such as JK1, JK2, and JK3 are designed for a reversible synchronous counter. Then JK1 and JK2 are structured by MCT. Whereas the JK3 flip-flop design is designed under MCF reversible logic gates. Coding is carried out Verilog, and then the proposed Reversible synchronous counter design (RSCD) is synthesized and implemented on FPGA using a Xilinx ISE 14.5 System generator. Here, performance metrics, such as delay, power, maximum counting rate, and total equivalent gate counts are examined. The efficiency of the proposed RSCD-MCT-MCF design attains gate counts of 23.45%, 28.94%, and 29.04% and is compared to the existing designs, such as Effective Designing of Reversible Synchronous Counters in Nanoscale (SCD-MTG), effective designing for reversible sequential circuits (SCD-3TG-4FG), designing of synchronous decimal counter utilizing reversible Toffoli–FredkinNetlist (SCD-TOF2).

Carbon Nanotube Transistor with Colloidal Quantum Dot Photosensitive Gate for Ultrahigh External Quantum Efficiency Photodetector

PbS colloidal quantum dots (CQDs) are promising building block for developing the next-generation high-performance near-infrared (NIR) photodetector. However, due to the surface ligand isolation and surface defects, PbS CQDs usually suffer from low carrier mobility, which limits further optimization of PbS CQDs-based optoelectronic devices. Here, the combination of PbS CQD photodiode and carbon nanotube (CNT) film field-effect transistor (FET) achieves a transistorized NIR photodetector with a photosensitive gate. The photogenerated electrons are drifted to the dielectric surface by a negative gate electric field and built-in electric field, serving as an equivalent gate voltage to turn on the CNT FET, thus realizing the conversion of optical signals to electrical signals. The photodetector exhibits high performance, with a responsivity and detectivity of 41.9 A/W and 3.04 × 1011 Jones under 950 nm illumination, respectively. More importantly, the photodetector achieves an ultrahigh external quantum efficiency (EQE) of 5470% due to the CNT FET amplification function. Besides, the photodetector demonstrates a versatile photoresponse that allows for regulation of responsivity, detectivity, and EQE over a wide range through gate voltage control. The photodetector shows immense potential in NIR photodetection applications, and the distinctive structure of the optical module and electrical module separation also provides fresh thinking for the research and development of the next generation of optoelectronic devices.

SPISE: A tiny, cost effective, speedy block cipher for low resourced devices

The Internet of Things has come up as a blessing in this fast paced technologically advanced world where it finds huge role in everyday life of people in the form of various sensors embedded in various systems which are connected with the Internet. Transmission and reception of data in digitized form is done by the IoT devices after collection of varied forms of data from various sources. In present times of IoT technology data safety is a blooming concern that hampers the confidentiality of valuable data greatly. A novel lightweight encryption strategy is devised by keeping the concern of data security by the name of SPISE which is aimed for general computing and IoT devices. SPISE enjoys both the architectural benefits of substitution permutation network and that of General Feistel structure to ensure better security. The new crafted method has achieved very low count of equivalent gates as low as 728 GE and is exceedingly swift with very low computational time of 1.364 ns with ultra-low power consumption of 32.16 µW when tested in Cadence Genus using 65 nm process technology and when synthesized on XC7VX330T Virtex 7 FPGA board in Xilinx ISE 14.7.

Low-area and high-speed hardware architectures of KLEIN lightweight block cipher for image encryption

Internet of Things (IoT) connects a wide range of small devices over a large network, allowing for a wide range of applications. With the advancement of open-source public networks (such as IoT), image transmission for resource-constrained devices is becoming more insecure. In this paper, two hardware implementations for KLEIN block cipher are proposed that can provide security to encrypt different sets of images under resource-constrained applications (such as wireless sensor network, radio frequency identification, IoT etc.). An improvement in maximum operating frequency of 32.72% and 75.66% in the proposed serial and pipelined architectures is observed compared with the state-of-the-art design, respectively. The implemented pipelined architecture yields high throughput of 1840.15 MHz, and the serialized architecture implies 108 numbers of slices implemented on field-programmable gate array (FPGA) xc5vlx50t-3ff1136 device. On application-specific integrated circuit (ASIC) platform, the proposed serialized KLEIN implementation consumed less area in terms of gate equivalent. The existing solution was also subjected to changing correlation coefficients, number of pixels changing rate, unified average changing intensity, and entropy values. The simulation results validate the effectiveness of the performance of the proposed encryption scheme.

Fully fixed-point integrated digital circuit design of discrete memristive systems

In this paper, the fully fixed-point digital integrated circuits of discrete memristive systems are designed with very low circuit area cost, where the two-stage pipeline and multi-cycle architecture is employed. Firstly, the mathematical models of the discrete memristor and a memristor chaotic map are presented and dynamics are analyzed. Secondly, data flow design is carried out and the feasibility of the fixed-point model is discussed, which provides a foundation for the further circuit design. Thirdly, different architectures are designed and we get the optimal results. As a result, gate area of the discrete memristor is 40288 μm2 and the equivalent gate counts are 4588, while gate area of the discrete memristor map is 40424 μm2 and the equivalent gate counts are 4604. Moreover, a chaotic pseudo random sequence generator is designed and the NIST test is passed. It provides the foundation for the further applications of the discrete memristor and discrete memristor chaotic systems.

A new idea in response to fast correlation attacks on small-state stream ciphers

In the conference “Fast Software Encryption 2015”, a new line of research was proposed by introducing the first small-state stream cipher (SSC). The goal was to design lightweight stream ciphers for hardware applications by going beyond the rule that the internal state size must be at least twice the intended security level. Fast correlation attack (FCA) was successfully applied to all proposed SSCs which can be implemented by less than 1000 gate equivalents in hardware. It is possible to increase the security of stream ciphers against FCA by exploiting more complicated functions for the nonlinear feedback shift register and the output function, but we use lightweight functions to design the lightest SSC in the world while providing more security against FCA. Our proposed cipher provides 80-bit security against all types of Time-memory-data trade-off (TMDTO) attacks, while Lizard and Plantlet provide only 60-bit and 58-bit security against TMDTO distinguishing attacks, respectively. Our main contribution is to propose a lightweight round key function with a very long period that increases the security of SSCs against FCA.

An Authentication Protocol for Next Generation of Constrained IoT Systems

With the exponential growth of connected Internet of Things (IoT) devices around the world, security protection and privacy preservation have risen to the forefront of design and development of innovative systems and services. For low-value IoT devices that identify and track billion of goods in various industries—such as radio-frequency identification (RFID) tags—this involves multiple challenges in very constrained environments. IoT devices aim to design low-cost, low-complexity infrastructure while enabling robust authentication protocols with reduced latency and energy consumption. Given these challenges, in this article, we present a new lightweight authentication protocol for IoT applications, employing an authenticated-encryption (AE) cryptosystem with associated data (AEAD). Since AEAD algorithms provide data confidentiality and message integrity simultaneously, security analysis [Real-or-Random (RoR) and Scyther] results prove the robustness of the proposed protocol against IoT threats. Furthermore, to measure the computation and communication cost, FPGA and ASIC simulations using four different AEAD candidates of National Institute of Standards and Technology (NIST) lightweight cryptography competition are executed. The implementation results [e.g., 4744 gate equivalent (GE) and 0.87-mw power] clearly show that our novel design can be applied to a wide range of constrained IoT devices complying with low-cost, lightweight, and high-speed requirements.

A comprehensive analysis of lightweight 8-bit sboxes from iterative structures

Massive data needs to be cryptographically handled in emerging IoT applications. Therefore the design and analysis of lightweight symmetric-key primitives become a research hotspot. Theoretically, symmetric-key cryptograms should be secure against differential, linear and other proposed structural cryptanalysis. In addition to these cryptographic properties, software and hardware costs are also pivotal for resource constrained devices. Traditionally, 4-bit sboxes are widely used in lightweight cryptography due to their efficiency. In this paper, we investigate the iterative constructions of lightweight 8-bit sboxes. Our proposals contain 8-bit sboxes constructed with the Feistel, Lai–Massey and SPN structures, which are iterated with the published lightweight 4-bit sboxes or non-bijective functions. Moreover, we propose 8-bit sboxes under the generalized Feistel network (GFN), which are suitable for software and hardware implementations. Based on the bitslicing method, software and hardware performances are analyzed with their CPU cycles and Gate Equivalent (GE). Compare to the published lightweight 8-bit sboxes with iterative structures, our proposals achieve similar software performance, whilst enjoying better algebraic degrees and less GE costs in hardware implementation.

High-Performance Hardware Implementation of the KATAN Lightweight Cryptographic Cipher

Lightweight cryptography has been proposed recently as an attractive solution to provide security for the ever-growing number of IoT resource-constrained devices. Many of the proposed lightweight cryptographic ciphers have been implemented in software. However, for practical embedded IoT applications, hardware implementations are preferred because they have small silicon area and low-power consumption. In this paper, we present a transistor-level hardware implementation of the well-known KATAN lightweight cipher. This cipher has been chosen due to its operational simplicity and high levels of security. Moreover, the structure of the KATAN cipher lends itself naturally for transistor-level hardware implementation. The design has been implemented at the transistor level using the advanced new 28-nm CMOS technology which facilitates optimized designs for the resource-constrained IoT devices. The proposed VLSI KATAN encryption and decryption circuits have been designed and simulated using the Synopsys Custom Designer Tool using 28-nm technology, 0.9 v supply voltage and a 1 GHz clock signal. The KATAN encryption circuit has 312 GE (Gate Equivalent) without key and irregular update registers, and 1081 GE for the overall design, and the decryption circuit has 390 GE without memory registers and 6867 GE for the overall design.

Conditions for Equivalent Noise Sensitivity of Geometric and Dynamical Quantum Gates

Geometric quantum gates are often expected to be more resilient than dynamical gates against certain types of error, which would make them ideal for robust quantum computing. However, this is still up for debate due to seemingly conflicting results in the literature. Here we use dynamical invariant theory in conjunction with filter functions in order to analytically characterize the noise sensitivity of an arbitrary quantum gate. For any control Hamiltonian that produces a geometric gate, we find that under certain common conditions one can construct another control Hamiltonian that produces an equivalent dynamical gate with identical noise sensitivity (as characterized by the filter function). Our result holds for a Hilbert space of arbitrary dimensions, but we illustrate our result by examining experimentally relevant single-qubit scenarios and providing explicit examples of equivalent geometric and dynamical gates.