Effective Gate Research Articles

Effective gate length determination of AlGaN/GaN HEMTs from direct measurements of thermal signatures

Determining junction temperature and two-dimensional temperature profile is critical for high-power GaN-based high electron mobility transistors to optimize performance, improve device reliability, and better thermal management. Here, we have demonstrated that resistance temperature detectors of the same material as the gate contact delineated between gate-to-source and gate-to-drain regions can accurately profile the temperature along the channel. The temperature profile is asymmetric and skewed toward the drain side, and the degree of asymmetry is used to determine the effective gate length experimentally. A two-dimensional thermodynamic model along with drift-diffusion transport matches well with the experimental data, validating the temperature profile and effective channel length extraction under bias. The vertical depth profiling of the temperature is also determined by identifying the isothermal profile through the resistance temperature detectors. The isothermal lines are largely circular in the GaN region from isotropic two-dimensional heat diffusion, with the pinch-off region acting as a heating filament. The isothermal circular profile turns elliptical in the SiC substrate due to its higher thermal conductivity.

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

Design and simulation of a nano biosensor based on amorphous indium gallium zinc oxide (a-IGZO) thin film transistor

In this study, a biosensor utilizing a dielectric-modulated amorphous indium gallium zinc oxide (a-IGZO) thin film transistor (TFT) is introduced. TFT biosensors have garnered significant attention due to their heightened sensitivity, scalable nature, low power consumption, rapid electrical detection capabilities, and cost-effective means of mass production. By embedding a nano-cavity within the gate insulator of the TFT, biomolecules can accumulate within. As each biomolecule possesses its own dielectric constant, it modulates the effective gate capacitance and, subsequently, changes the channel conductance. To assess the sensitivity of the biosensor, variation in saturation current after the absorption of biomolecules with respect to the drain current in the case of an air-filled cavity has been considered as a precise measure. The efficient operation of a biosensor is contingent upon the sensitivity being highly dependent on the dielectric constant of the biomolecules that are accumulated within the nano-cavity. Consequently, a comprehensive evaluation has been conducted to ascertain the impact of critical design parameters which have the potential to affect the sensitivity of the biosensor. Additionally, a statistical analysis based on coefficient of variation measure has been performed to evaluate the susceptibility of the biosensor’s sensitivity to variations in geometrical and physical design parameters. The utilization of label-free detection methodology in this device presents a notable advantage due to its compatibility with the fundamental CMOS processing technology and its cost-effective potential for macro production.

A Novel Enhancement-Mode Gallium Nitride p-Channel Metal Insulator Semiconductor Field-Effect Transistor with a Buried Back Gate for Gallium Nitride Single-Chip Complementary Logic Circuits

In this work, a novel enhancement-mode GaN p-MISFET with a buried back gate (BBG) is proposed to improve the gate-to-channel modulation capability of a high drain current. By using the p-GaN/AlN/AlGaN/AlN double heterostructure, the buried 2DEG channel is tailored and connected to the top metal gate, which acts as a local back gate. Benefiting from the dual-gate structure (i.e., top metal gate and 2DEG BBG), the drain current of the p-MISFET is significantly improved from −2.1 (in the conv. device) to −9.1 mA/mm (in the BBG device). Moreover, the dual-gate design also bodes well for the gate to p-channel control; the subthreshold slope (SS) is substantially reduced from 148 to ~60 mV/dec, and such a low SS can be sustained for more than 3 decades. The back gate effect and the inherent hole compensation mechanism of the dual-gate structure are thoroughly studied by TCAD simulation, revealing their profound impact on enhancing the subthreshold and on-state characteristics in the BBG p-MISFET. Furthermore, the decent device performance of the proposed BBG p-MISFET is projected to the complementary logic inverters by mixed-mode simulation, showcasing excellent voltage transfer characteristics (VTCs) and dynamic switching behavior. The proposed BBG p-MISFET is promising for developing GaN-on-Si monolithically integrated complementary logic and power devices for high efficiency and compact GaN power IC.

Mitigating WL-to-WL Disturbance in Dynamic Random-Access Memory (DRAM) through Adopted Spherical Shallow Trench Isolation with Silicon Nitride Layer in the Buried Channel Array Transistor (BCAT)

The Pass Gate Effect (PGE), often referred to as adjacent cell interference, presents a significant challenge in dynamic random-access memory (DRAM). In this study, we investigate the impact of PGE and propose innovative solutions to address this issue in DRAM technology, employing 10 nm node technology with buried channel array transistors. To evaluate the efficacy of our proposals, we utilized SILVACO for simulating various DRAM configurations. Our approach centers on two key structural optimizations: the introduction of a spherical Shallow Trench Isolation (STI) and the incorporation of a silicon nitride (Si3N4) layer within the spherical STI structure. These optimizations were meticulously designed to mitigate the PGE by considering several factors that are highly influential in its manifestation. To validate our approach, we conducted comprehensive simulations, comparing the PGE factors of typical DRAM structures with those of our proposed configurations. The results of our analysis strongly support the effectiveness of our proposed structural enhancements in alleviating the PGE when contrasted with conventional DRAM structures. Remarkably, our optimizations achieved a remarkable 82.4% reduction in the PGE, marking a significant breakthrough in the field of DRAM technology. By addressing the PGE challenge and substantially reducing its impact, our research contributes to the advancement of DRAM technology, offering practical solutions to enhance data integrity and reliability in the era of 10 nm node DRAM.

Effective Gating in Single-Molecule Junctions through Fano Resonances.

The successful incorporation of molecules as active circuit elements relies on the ability to tune their electronic properties through chemical design. A synthetic strategy that has been used to manipulate and gate circuit conductance involves attaching a pendant substituent along the molecular conduction pathway. However, such a chemical gate has not yet been shown to significantly modify conductance. Here, we report a novel series of triarylmethylium and triangulenium carbocations gated by different substituents coupled to the delocalized conducting orbitals on the molecular backbone through a Fano resonance. By changing the pendant substituents to modulate the position of the Fano resonance and its coupling to the conducting orbitals, we can regulate the junction conductance by a remarkable factor of 450. This work thus provides a new design principle to enable effective chemical gating of single-molecule devices toward effective molecular transistors.

Gate Capacitance Coupling of Double-Gate Carbon Nanotube Network Transistors.

Carbon nanotube (CNT) network channels constructed using a high-purity CNT solution for use in CNT thin-film transistors have the advantages of the possibility of requiring a low-temperature process and needing no special equipment. However, there are empty spaces between individual CNTs, resulting in unexpected effects. In this study, double-gate (DG) CNT network transistors were fabricated and measured in four different configurations to observe the capacitive coupling effects between the top gate (TG) and bottom gate (BG) in the DG structure. As a result, the electrical characteristics measured with the BG with a thicker gate oxide while floating the TG were similar to those measured with the TG with a thinner gate oxide. A comparison of the measured transfer curves showed that TG and BG were strongly coupled through the empty spaces in the channels. In addition, we evaluated the capacitance coupling effect due to changes in the CNT density, which is closely related to the empty space of the network channel. Finally, we proposed a method to determine the effective gate capacitance by considering the empty spaces between CNTs, which enabled the accurate evaluation of mobility. The effects of these materials were demonstrated by fabricating transistors using Al2O3, HfO2, and ZrO2 as TG oxide materials. By focusing on considerations based on the properties of CNT materials, our study provides valuable insights into accurate electrical modeling and potential advancements in CNT-based devices.

Active control of polariton-enabled long-range energy transfer.

Optical control is achieved on the excited state energy transfer between spatially separated donor and acceptor molecules, both coupled to the same optical mode of a cavity. The energy transfer occurs through the formed hybrid polaritons and can be switched on and off by means of ultraviolet and visible light. The control mechanism relies on a photochromic component used as donor, whose absorption and emission properties can be varied reversibly through light irradiation, whereas in-cavity hybridization with acceptors through polariton states enables a 6-fold enhancement of acceptor/donor contribution to the emission intensity with respect to a reference multilayer. These results pave the way for synthesizing effective gating systems for the transport of energy by light, relevant for light-harvesting and light-emitting devices, and for photovoltaic cells.

Single-Crystal Silicon Nanotubes, Hollow Nanocones, and Branched Nanotube Networks.

We report a general approach for the synthesis of single-crystal silicon nanotubes, involving epitaxial deposition of silicon shells on germanium nanowire templates followed by removal of the germanium template by selective wet etching. By exploiting advances in the synthesis of germanium nanowires, we were able to rationally tune the nanotube internal diameters (5-80 nm), wall thicknesses (3-12 nm), and taper angles (0-9°) and additionally demonstrated branched silicon nanotube networks. Field effect transistors fabricated from p-type nanotubes exhibited a strong gate effect, and fluid transport experiments demonstrated that small molecules could be electrophoretically driven through the nanotubes. These results demonstrate the suitability of silicon nanotubes for the design of nanoelectrofluidic devices.

Theoretical determination of the effect of a screening gate on plasmon-induced superconductivity in twisted bilayer graphene

Theoretical determination of the effect of a screening gate on plasmon-induced superconductivity in twisted bilayer graphene

The Effect of Gate Drive Resistance on the CM EMI Performance of the Balanced Inverter with Asymmetrical Parasitic Impedance Distribution

The Effect of Gate Drive Resistance on the CM EMI Performance of the Balanced Inverter with Asymmetrical Parasitic Impedance Distribution

Low-temperature crosslinked soluble polyimide as a dielectric for organic thin-film transistors: enhanced electrical stability and performance

We have prepared a low-temperature cross-linked soluble polyimide (SPI) as a dielectric material for organic thin-film transistors (OTFTs) to improve their electrical stability. Two types of SPIs (DOCDA/6FHAB and 6FDA/6FHAB) were synthesized by a one-step polymerization process using 5-(2,5-dioxytetrahydrofuryl)-3-methyl-3-cyclohexene-1,2-dicarboxylic anhydride (DOCDA) and hexafluoroisopropylidene diphthalic anhydride (6FDA) as the dianhydrides and 2,2-bis(3-amino-4-hydroxyphenyl)hexafluoropropane (6FHAB) as a diamine. To further enhance the electrical performance, the SPI thin films were crosslinked with methylated/ethylated (hydroxymethyl)benzoguanamine (HMBG) through a low temperature process at 160 °C. Crosslinking considerably improved the insulating properties, resulting in a substantial reduction in leakage current from 10−7 A cm−2 to 10−9 A cm−2 at 2.0 MV cm−1. When crosslinked SPIs were used as gate dielectrics in OTFTs, device stability and reliability, as measured by the off-current, threshold voltage, and hysteresis, improved significantly. Our results demonstrate the potential of crosslinked SPIs as effective gate dielectric materials for advanced organic thin-film transistors.

Plunger gate effects on magneto transport in double-top gate spin-orbit devices

A propagation matrix method is used to investigate the quantum conductance of an n-type double-top gate device under a strong Rashba-Zeeman coupling interaction. The effects of a plunger gate potential and the total top gate length on the magneto conduction properties are investigated. Transcendental equations and analytical formulas are derived to accurately predict the resonance state and hole-like bound state structures. Furthermore, the effect of the distance of the two top gates from the plunger gate is examined for both symmetric and asymmetric structures. The analytical technique employed in this study provides an accurate and reliable approach for calculating the conductance of the quantum transport and is therefore beneficial for the design of n-type semiconductor devices.

Ultrasensitive and selective detection of ciprofloxacin in milk based on organic photoelectrochemical transistor aptasensor enhanced by high capacitance Ti3C2/TiO2

Ciprofloxacin (CIP) in milk has a harmful effect on human health, it’s important to conduct ultra-sensitive selective detection of ciprofloxacin. Herein, an ultrasensitive and selective organic photoelectrochemical transistor (OPECT) CIP aptasensor was constructed using Ti3C2/TiO2 composites as gate photoactive materials. Compared with Ti3C2, TiO2, and Ti3C2/TiO2 mixed by physical, Ti3C2/TiO2 composites exhibits larger capacitance and the OPECT intensity is 3 times of Ti3C2, 2 times of Ti3C2/TiO2 mixed by physical and TiO2, which attributed to higher capacitance of Ti3C2/TiO2 composites provides high electrostatic charge storage capacity and leads to effective gating, induces more electronic charge in the channel and larger drain currents. Exemplified by CIP as target, the developed sensor achieves sensitive detection with linear range from 3 ng/L to 3 mg/L, detection limit is 1 ng/L. This work completed the detection in real samples, which lays a foundation for the construction of OPECT food safety analysis and detection platform.

Multi-Gate In-Plane Actuated NEMS Relays for Effective Complementary Logic Gate Designs

Multi-Gate In-Plane Actuated NEMS Relays for Effective Complementary Logic Gate Designs

Towards Conceptualization Of A Prototype For Quantum Database: A Complete Ecosystem

This study proposes a conceptualization of a prototype And a possibility to converge classical database and fully quantum database. This study mostly identifies the gap between this classical and quantum database and proposes a prototype that can be implemented in future products. It is a way that can be used in future industrial product development on hybrid quantum computers. The existing concept used to consider oracle as a black box in this study opens up the possibility for the quantum industry to develop the QASAM module so that we can create a fully quantum database instead of using a classical database as BlackBox.As the Toffoli gate is basically an effective NAND gate it is possible to run any algorithm theoretically in quantum computers. So we will propose a logical design for memory management for the quantum database, security enhancement model, Quantum Recovery Manager & automatic storage management model, and more for the quantum database which will ensure the quantum advantages. In this study, we will also explain the Quantum Vector Database as well as the possibility of improvement in duality quantum computing. It opens up a new scope, possibilities, and research areas in a new approach for quantum databases and duality quantum computing.

High-Efficiency Area-Emissive White Organic Light-Emitting Transistor for Full-Color Display.

The construction of high-performance white organic light-emitting transistor (OLET) with uniform area emission is crucial for smart display technologies but remains greatly challenging. Herein, high-efficiency uniform area-emissive OLETs based on a unique lateral-integrated device configuration which incorporates efficient energy transfer of phosphorescent and fluorescent guests, enabling color-tunable and white emission, are demonstrated. Through precisely regulating the energy transfer between host and guests, high external quantum efficiency of 13.9% for white-emission OLETs is achieved due to the improved high exciton utilization and light outcoupling efficiency which is the highest value reported so far for OLETs and prevents exciton-charge annihilation and electrode photon losses. Moreover, good loop stability is also achieved, along with effective gate tunability and ultralow driving voltage of below 5V. Finally, a 4 × 6 white-emission OLET array for full-color display is demonstrated for the first time, suggesting its great potential applications for advanced display technologies.

Synaptic devices based on organic ferroelectric memtransistor with arithmetic calculating and logic functions

The bionic features offered by memory device are being actively explored. However, two-terminal memristors exhibit variability and limited capacity due to their inherent single presynaptic input scheme. Compared with the two-terminal memristor, the memtransistor can realize the modulation of conductive channel through the synergistic effect of gate, which enables the multifunctional modulation. Here, based on Schottky barrier tuning at metal-semiconductor interfaces by means of ferroelectric domain switching, a programmable memtransistor with arithmetic calculating and logic function is realized. Memtransistor with drain and gate adjustable non-volatile memory function effectively simulates the plasticity of biological synapses. Moreover, four arithmetical operations: addition, subtraction, multiplication and division are carried out by using the synaptic device. At the same time, the logic gate functions of “XOR” and “XNOR” were implemented based on ferroelectric memtransistor. This result will be helpful to further promote the development of memory computing for synaptic devices.

Quality factor and digital inverter performance in gate underlap and overlap DMG FinFETs

This paper presents a comparative 3D simulation study of Quality factor among Gate Underlap and Overlap techniques in both Si and Ge Dual Material Gate (DMG) FinFETs using the Sentaurus TCAD tool. The results of both the techniques are carefully examined and compared with Conventional DMG FinFET to analyze the performances of these devices. The effect of gate overlap/underlap techniques on threshold voltage (Vth), ION/IOFF ratio, drain induced barrier lowering (DIBL), transconductance (gm), subthreshold swing (SS), and Quality factor (Q) are investigated. It is found that Ge DMG FinFETs have higher gm and quality factor values as compared to Si DMG FinFETs. The prospects of these techniques in low-power digital applications have been performed by implementing complementary Si DMG FinFET based inverter circuit. We have extracted the average delay and noise margin, where the overlap structure performs better such as high current gain and no overshoot/undershoot peaks in the transient characteristics.

Synergic Effect of Misaligned Gate and Temperature on Hetero‐Dielectric Double‐Gate Junctionless Metal–Oxide‐Semiconductor Field‐Effect Transistors for High‐Frequency Application

Junctionless metal–oxide‐semiconductor field‐effect transistors (MOSFETs) have emerged as a promising alternative to conventional MOSFETs, offering simplified fabrication and potential performance improvements. The novelty of this research lies in the selection of hetero‐dielectric material to optimize the performance of junctionless transistors under the misaligned gate and high‐temperature conditions, and the aim is to explore its capability for low‐power high‐frequency application. The results reveal that the proposed junctionless field effect transistor exhibits increased transconductance (17 mS), which enables higher gain (311 dB) and diminishes capacitive effects, leading to a broader range of cutoff frequencies (154 GHz) with gain frequency product and gain transconductance frequency product are 31 and 95.9 THz, respectively. Moreover, this research article investigates critical reliability issues related to junctionless MOSFET, focusing on gate misalignment and thermal stability. The study reveals that gate misalignment reduces on‐current and degrades device performance. Additionally, the study examines thermal stability over a wide temperature range (300 to 500 K), exploring the impact of temperature on performance. These valuable findings provide crucial insights to overcome fabrication challenges and drive the practical adoption of junctionless MOSFETs in future integrated circuits. To assess device performance in high‐frequency applications, Silvaco ATLAS TCAD tools are employed.