Gate Edge Region Research Articles

Investigation on the Thermal Characteristics of Enhancement-Mode p-GaN HEMT Device on Si Substrate Using Thermoreflectance Microscopy.

In this paper, thermoreflectance microscopy was used to measure the high spatial resolution temperature distribution of the p-GaN HEMT under high power density. The maximum temperature along the GaN channel was located at the drain-side gate edge region. It was found that the thermal resistance (Rth) of the p-GaN HEMT device increased with the increase of channel temperature. The Rth dependence on the temperature was well approximated by a function of Rth~Ta (a = 0.2). The three phonon Umklapp scattering, point mass defects and dislocations scattering mechanisms are suggested contributors to the heat transfer process for the p-GaN HEMT. The impact of bias conditions and gate length on the thermal characteristics of the device was investigated. The behaviour of temperature increasing in the time domain with 50 µs pulse width and different drain bias voltage was analysed. Finally, a field plate structure was demonstrated for improving the device thermal performance.

Analysis of MIS-HEMT Device Edge Behavior for GaN Technology Using New Differential Method

A new differential method for accurate extraction of electrical parameters of high-electron mobility transistor (HEMT) devices for gallium nitride (GaN) technology is proposed. This method, presented here for the first time, is used to study the mobility degradation with gate length, allowing an analysis of the contribution of the gate edge region to the total metal-insulator semiconductor (MIS)-HEMT device conductance. First, an analytical model is proposed to account for the relative conduction of the edges and the main flat part of the channel HEMTs. Second, the differential method allows the split-CV mobility extraction of each part, allowing a precise analysis of the resistive contribution of each region of the HEMT devices. This study has been performed over a large range of channel lengths for two normally OFF HEMT GaN wafers having different recess depths.

Investigation of Negative Bias Temperature Instability Effect in Partially Depleted SOI pMOSFET

The negative bias temperature instability (NBTI) mechanisms for Core and input/output (I/O) devices from a 130 nm partially-depleted silicon on insulator (PDSOI) technology are investigated. The I/O device degrades more than the Core device under the same stress electric field due to the different gate oxide processes in these two types of devices. Both the oxide trap charge and interface trap lead to the transfer characteristics degradations of the device after NBTI. While the near interfacial traps result in the increase of low frequency noise (LFN). The trap densities near the silicon/gate oxide interface introduced by stress are extracted using the LFN method. NBTI-induced gate current increase is observed for Core device, but not for I/O device. It is result from the enhanced tunneling process, which is induced by the increase of electric field in the gate oxide after charge trapping at or near the channel interface. The gate width and length dependences of NBTI are observed. The enhanced NBTI degradation observed in short channel and narrow channel device is result from the enhanced NBTI effect at channel edge regions. The larger hole concentration is a main cause of the more serious NBTI degradation at the channel edge regions, including the nearby region of STI sidewall along the channel width direction and the gate edge region along the channel length direction. This conclusion is also verified by the TCAD simulations.

Channel-length dependence of mechanical stress effect by hybrid shallow trench isolation on NBTI degradation of HfSiON/SiO2p-channel MOSFETs with strained Si/SiGe channel

This paper quantifies how mechanical stress induced by the hybrid shallow trench isolation affects negative bias temperature instability (NBTI) degradation of p-type channel MOSFETs (pMOSFETs) that have a strained Si/SiGe channel. As the channel length L decreased, the NBTI degradation decreased and electrical characteristics degraded. Experimental results indicate that tensile stress σt applied to the channel region decreased the energy band-gap by increasing the intrinsic carrier concentration. NBTI degradation was not affected by application of an oxide electric field to compensate for the charge that is induced differently in the Si channel during strong inversion. The distribution of the shift ΔVth of threshold voltage before and after NBTI stress in the channel region was also examined. As L decreased, the decrease of ΔVth was greater in the gate edge region than in the center region. These results show that the observed L-dependence of NBTI degradation characteristics were caused by σt in the channel region, and affected the gate edge region dominantly. Therefore, to achieve reliable high-k pMOSFETs with the strained Si/SiGe channel as L is scaled down, methods should be developed to control mechanical stress in the gate edge region.

A new erase method for scaled NAND flash memory device

A suitable bird-beak thickness is crucial to the cell reliability. However, the process control for bird-beak thickness in the edge region is very difficult. A new erase method is proposed in this work to modulate the electron tunneling region of 40nm floating gate NAND flash memory device. The erasing electron can move to gate center from gate edge under back bias at 0.3V/−0.8V. The Fowler-Nordheim (FN) current of erase operation distributes on the whole channel region, not located at the gate edge region. Results show that the proposed method can improve cell reliability about 33%. TCAD analysis is employed to explain and prove the mechanism. This new erase method is promising for scaled NAND flash memory.

Profiling of Channel-Hot-Carrier Stress-Induced Trap Distributions Along Channel and Gate Dielectric in High-$k$ Gated MOSFETs by a Modified Charge Pumping Technique

To better understand the channel-hot-carrier (CHC)-induced reliability problems, a modified charge-pumping (CP) technique is proposed to characterize the distribution profiles of trap generation in MOSFETs with high- k gate-stack. The effects of gate leakage current on CP measurements were minimized to ensure the correct CP data. While applying dynamic drain bias, the gate-induced drain leakage current is also considered to get correct CP data. Through the CP with dynamic drain bias and various gate pulse frequencies, the profiling of CHC stress-induced interface- and border-traps can be achieved. The CHC stress-induced interface trap generation appears along whole the channel but that-induced border trap generation is mainly located above the pinchoff region near the drain and decreases dramatically toward the center of the channel. Thus, the CHC stress causes quite localized border trap generation at the gate-edge region inside the high- k dielectric. The reliability data measured by CP with different gate voltage swings confirm that CHC stress causes interface trap generation through whole the channel and significant border trap generation at gate-edge region.

The Field Modulation Effect of a Fluoride Plasma Treatment on the Blocking Characteristics of AlGaN/GaN High Electron Mobility Transistors

We designed and fabricated aluminium gallium nitride (AlGaN)/GaN high electron mobility transistors (HEMTs) with stable reverse blocking characteristics established by employing a selective fluoride plasma treatment on the drainside gate edge region where the electric field is concentrated. Implanted fluoride ions caused a depolarization in the AlGaN layer and introduced an extra depletion region. The overall contour of the depletion region was expanded along the drift region. The expanded depletion region distributed the field more uniformly and reduced the field intensity peak. Through this field modulation, the leakage current was reduced to 9.3 nA and the breakdown voltage (<TEX>$V_{BR}$</TEX>) improved from 900 V to 1,400 V.

Investigation of Gate Etch Damage at Metal/High-$k$ Gate Dielectric Stack Through Random Telegraph Noise in Gate Edge Direct Tunneling Current

Plasma damage on a high-k/SiO2 dielectric at a gate edge during a dry etch process is investigated. The damage was observed to generate slow oxide traps, causing a random telegraph noise (RTN) in a gate edge direct tunneling current. Through the analysis of the RTN, the distribution of the oxide traps in the high-k/SiO2 dielectric was obtained, and the plasma-damage-induced oxide traps were found to be distributed over a wide area of the high-k/SiO2 sidewall at the gate edge region.

High breakdown voltage AlGaN/GaN HEMT by employing selective fluoride plasma treatment

AbstractFluoride‐based plasma treatment was employed to improve reverse characteristics. The fluoride‐based plasma treatment using CF4 gas was performed on drain‐side gate edge region, where field plate metal is deposited, at an RF power of 30W for 120 sec. Experimental results showed that fluoride based plasma treated AlGaN/GaN HEMT had stable reverse blocking capability by successfully suppressing leakage current as well as increasing off‐state breakdown voltage (VBR) with minimized degradation in forward characteristics. Leakage current of untreated sample was increased in proportional to reverse bias voltage while that of fluoride plasma treated sample was remained at nano level. Fluoride plasma treatment improved breakdown voltage of device from 900 V to 1400 V with 16% decrease in output current (© 2011 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Hot-Carrier Degradation in Low-Temperature Polycrystalline Silicon n-Channel Lightly Doped Drain Thin-Film Transistors

The hot-carrier degradation mechanism in low-temperature polycrystalline silicon (poly-Si) n-channel lightly doped drain (LDD) thin-film transistors (TFTs) is investigated. The degradation is characterized by transconductance degradation (ΔGm) at low drain voltage (Vd) and decreases in substrate current (Isub) and kink current at high Vd. It is assumed that the trapped negative charges (acceptor-type trap states) in the gate edge region, mostly outside and partly inside the gate, contribute to hot-carrier degradation after stress under current saturation bias. The degradation presumably first occurs outside the gate in the LDD region and, with increasing stress time, the electron-trapped region expands toward the channel under the gate owing to the saturation of electrons in the trap states. At high-Vd bias, a decrease in the lateral electric field in the gate-edge region due to the presence of negative charges reduces Isub and the drain current Id, thereby reducing the kink current. At low-Vd bias, the current flow near the upper interface in the gate-edge region decreases after the stress owing to the generated negative charges. The negative charges lead to the decrease in Id in the deep-gate voltage Vg region in Vg–Id characteristics.

Features and mechanisms of the saturating hot-carrier degradation in LDD NMOSFETs

Propagation of defects from the sub-spacer region to the gate-overlapped LDD region in NMOSFETs is modeled using measurements and 2-D device simulation. It is argued that the saturation of degradation is caused by the saturating nature of this degradation length, as opposed to decreasing lateral electric field maxima (E/sub m/) or increasing barrier height (/spl phi//sub it/) to defect creation. Two stage hot-carrier degradation was observed in our LDD NMOSFETs. The early mode (1000-3000 s) of the degradation is characterized by a sharp rate of degradation of the linear transconductance (g/sub m/), and a reduction in the substrate current (I/sub B/). In order to locate and quantify defects produced in this early mode degradation phase, we use the results of a combination of the floating gate technique and simultaneous measurements of the reverse (source and drain interchanged) saturation g/sub m/'s. These results help us build a 2-D simulation framework involving trapped negative charges in the oxide in the drain-side gate-edge region, partly under the gate and partly in the spacer region. We then use 2-D simulation and other measurements such as linear and saturation current degradation, I/sub B/ degradation, and charge pumping to confirm the location of the defects and help estimate their quantity. Simulation results also help us build an analytical model for defect propagation from the early mode to the late mode. The analytical model is seen to explain many features of the saturating nature of hot-carrier degradation.

Deep cryogenic noise and electrical characterization of the complementary heterojunction field-effect transistor (CHFET)

This paper discusses a characterization at 4 K of the complementary heterojunction field-effect transistor (CHFET), to examine its suitability for deep cryogenic (<10 K) readout electronics applications. The CHFET is a GaAs-based transistor analogous in structure and operation to silicon CMOS. The electrical properties including the gate leakage current, subthreshold transconductance, and input-referred noise voltage were examined. It is shown that both n-channel and p-channel CHFET's are fully functional at 4 K, with no anomalous behavior, such as hysteresis or kinks. Complementary circuit designs are possible, and a simple CHFET-based multiplexed op-amp is presented and characterized at 4 K. The noise and gate leakage current of the CHFET are presently several orders of magnitude too large for readout applications, however. The input-referred noise is on the order of 1 /spl mu/V//spl radic/(Hz) at 100 Hz for a 50/spl times/50 /spl mu/m n-channel CHFET. The gate current is strongly dependent on the doping at the gate edge, and is on the order of 10/sup -14/ A for a 10/spl times/10 /spl mu/m/sup 2/ n-channel CHFET with light gate-edge region doping.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Simulation of tunneling current from gate edges of metal-oxide-silicon structures

A numerical model has been developed to calculate the electron tunneling current component from gate edges of metal-oxide-silicon capacitor/transistor structures, which had been neglected in previous studies. Tunneling probability from the gate edge is obtained by direct solution of the time-independent Schrödinger equation, using Schwarz–Christoffel transformation to map the nonplanar gate edge region to a rectangular domain, and solving the transformed Schrödinger equation by finite element methods.

Simulation of time-dependent tunneling characteristics of MOS structures

A detailed model has been developed to simulate the Fowler-Nordheim tunneling and degradation characteristics of thermal oxides on silicon incorporating geometry effects, trapping at pre-stress and post-stress trap sites, and field dependent charge to breakdown. For the first time, the effect of gate edge on the time-dependent tunneling characteristics has been quantitatively analyzed, using the Schwarz-Christoffel transformation method. It is found that gate edge region can enhance the tunneling current significantly and also accelerate oxide degradation and breakdown. One application of this model is to remove geometry effects in the oxide parameters extracted using ramp-stress measurements. Another application is to use the asymmetry in gate and substrate injections to electrically characterize the gate geometry and obtain an effective edge curvature.