Gate Driver IC Research Articles

Compact RF transmission unit for nuclear quadrupole resonance spectroscopy

Nuclear quadrupole resonance (NQR) spectroscopy is a non-destructive measurement technique that enables to detect materials of interest very accurately. This technique works by sending high power electromagnetic waves with radio frequency (RF) very specific to the molecular structure to excite the sample and detecting the respond signal with the same frequency. Portable NQR detectors can be potentially developed to detect explosives with non-metallic containers in the fields. However, commercial RF high power amplifiers are large and heavy, so they are not practical for field usage. In this work, we demonstrate a compact NQR transmission part which composed of an active input signal conditioner, a class-D amplifier, and an NQR coil. The active input signal conditioner circuit will convert a single rf pulse with low amplitude (<0.5Vp) to two pulses (with 180° phase difference) and they are subsequently amplified to TTL level. In the class-D amplifier, the pre-amplified pulses are further amplified by a high voltage gate driver IC to 24V amplitude. These high voltage pulses are converted to a single 24V pulse by MOSFETs connected in a half bridge configuration. Finally, the amplified pulse is fed to the NQR coil, i.e., a low impedance LC series resonance circuit. The voltage across the coil at resonance frequency is about 1kVpp.

A Load Adaptive Digital Gate Driver IC With Integrated 500 ksps ADC for Drive Pattern Selection and Functional Safety Targeting Dependable SiC Application

A fully integrated load adaptive digital gate driver is proposed for high-speed and dependable SiC applications. It breaks the trade-off between surge/ringing and switching loss over a wide load range of 3∼15 A by selecting the gate patterns stored in 8 channel 1.5 kb Look Up Table (LUT). The principle of voltage ringing during turn-off of power devices is analyzed, and a method of temporarily controlling the gate current in the opposite direction is found to be effective. A proposed time resolution expansion technique allows the output of optimal waveforms based on theory without increasing the memory size, achieves the surge/ringing suppression of 51% and reduce the LUT size by 1/12. The integrated 500 ksps Successive Approximation Register (SAR) ADC with steady sampling and automatic VDD selection schemes senses not only the load current, but also the surge and the short circuit for functional safety.

Gate Driver ICs with Closed-Loop Current Balancing Control for Parallel Connected IGBTs

Gate Driver ICs with Closed-Loop Current Balancing Control for Parallel Connected IGBTs

Design of High Step-Down Ratio Isolated Three-Level Half-Bridge DC–DC Converter With Balanced Voltage on Flying Capacitor

A high step-down ratio three-level half-bridge (TLHB) dc–dc converter with a current-doubler rectifier is presented for power conversion from a 48-to-60-V input to a 0.5-to-1-V output. The proposed TLHB topology and operation employed on the primary side improve the power-conversion efficiency by reducing the switching loss while minimizing the turn ratio of the transformer by converting the input voltage down to one quarter on the primary side. Moreover, it reduces the voltage stress on switches by half, thereby enabling the converter to be implemented with Si transistors with low breakdown voltage. The designed TLHB gate-driver IC minimizes the delay mismatches in gate drivers and mitigates the effect of the leakage inductance of the transformer, reducing the voltage imbalance on the flying capacitor without any balancing scheme in the controller. The proposed dc–dc converter implemented with 40-V Si transistors for the primary-side switches achieves 92.8% peak efficiency while supporting the maximum load current of 60 A and the maximum input voltage of 60 V. The converter with the proposed TLHB gate driver IC shows less than 0.8% voltage imbalance on the flying capacitor.

1 kW MHz Wideband Class E Power Amplifier

Class E power amplifiers are widely used in high-frequency applications due to their simplicity and use of only one ground-referenced switch. However, Class E power amplifiers are usually tuned to operate at a fixed frequency due to their resonant nature. Extending the bandwidth of these switch-mode power amplifiers is beneficial in many applications, such as plasma generators and wireless power transfer systems. In this paper, we present a 1 kW wideband Class E power amplifier using Silicon Carbide (SiC) MOSFETs that achieves 93% efficiency at 13.56 MHz with a bandwidth of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\pm$</tex-math></inline-formula> 1 MHz. We incorporate a reactance compensation network in the output loading stage to achieve wideband operation; design a custom gate drive circuit to reduce the gate power loss and improve thermal performance compared to using a gate driver IC. The total gate power of one SiC MOSFET is measured to be 1.55 W at 13.56 MHz.

New Driving Structure to Increase Pixel Charging Ratio for UHD TFT-LCDs With High Frame Rate

This paper proposes a new driving structure of the thin-film transistor liquid crystal display (TFT-LCD) for use in notebook displays with ultra-high definition (UHD) and a high frame rate. The proposed pixel circuit improves the pixel charging ratio by reducing the RC loadings of the data lines and extending the available row-line time for pixel charging. A new gate driver circuit that generates two output waveforms in a single stage is presented to reduce the cost and occupied layout area of gate driver ICs, enabling the realization of high-resolution displays with a narrow bezel. To verify the feasibility of the proposed driving structure, a 12.3-inch panel with UHD (3840 &#x00D7; 2160) and a frame rate of 120 Hz is fabricated. Experimental results demonstrate that the proposed driving structure yields a measured pixel charging ratio of more than 97.09% for a heavy loading pattern with a gray level of 255. Following an accelerated lifetime test, the measured waveforms of the proposed gate driver circuit are stable without any malfunction, demonstrating its high reliability. Therefore, the proposed driving structure and the gate driver circuit are highly suitable for use in UHD TFT-LCD notebook applications.

A Smart Gate Driver IC for GaN Power HEMTs With Dynamic Ringing Suppression

Conventional di/dt and dv/dt control and gate protection techniques for gallium nitride (GaN) power transistors usually employ external controllers, isolation circuits, discrete pull-up, and pull-down resistors. With large number of components, power modules become more complex and may introduce additional parasitic. Gate driver ICs with segmented output stages and dynamic gate driving have been reported previously to be effective in simultaneously suppressing gate ringing and overshoot voltage while maintaining fast switching speed. However, the programming for dynamic gate driving is rather complicated, requiring the user to load a sequence of driving patterns obtained from trial and error ahead of time. This article presents a gate driver IC for E-mode GaN power transistors with seven segmented output stages. More importantly, it offers a simplified programming method for the dynamic gate driving pattern. The optimal gate drive pattern can be defined by simply adjusting one external bias resistor. The proposed method eliminates the complex trial and error digital control, and can potentially promoting the wider acceptance of dynamic gate driving by the industry. The timing resolution for the gate drive pattern can be varied in steps from 0.5 to 5 ns. It can also be used to drive many commercially available GaN power transistors.

A High Current High Power Density Motor Drive for a 48-Volt Belt-Driven Starter Generator (BSG) System

A 48 V Belt-Driven Starter Generator (BSG) System is featured with high output current, high starting torque, and highly efficient thermal management. This paper firstly elaborates hardware design considerations of a high power density three-phase BSG inverter to address the challenges of even current distribution among paralleled MOSFETs, small drain-source voltage spike and good thermal dissipation. In order to satisfy the high-current requirement, a careful selection of MOSFET device with high-current rating and low on-resistance has been presented. In order to suppress circulating current among paralleled devices, individual gate resistors have been placed in the gate loop of each MOSFET. In order to provide good thermal dissipation, an Insulated Metal Substrate (IMS) board and single-layer layout technique have been implemented. Multiple low-profile electrolytic capacitors are used to increase the power density of the prototype. Moreover, the use of automotive gate driver IC TLE9180 and microcontroller TC1782 makes the prototype more readily accepted by industry. An improved Interior Permanent Magnet (IPM) motor control strategy and a pump-back system based on a virtual machine concept have been implemented to facilitate the validation of the prototype under rated condition without using a real motor. The control algorithm automatically adjusts the onset of field-weakening by using an additional inverter voltage loop and takes into account the nonlinearity of the stator flux linkage by using curve fitting technique, which makes the motor drive adaptive to machine parameter changes as well as DC bus voltage fluctuation. A three-phase BSG inverter prototype with a peak power of 12 kW has been built and tested. The prototype power density has reached 20.3 kW/L. Both PLECS simulations and hardware experiments show a continuous and stable operation with up to 200 A phase current and up to 600 Hz output frequency.

A self-adaptive pulse generator to realize extremely low power consumption and high reliability of high voltage gate driver IC

A self-adaptive pulse generator featuring with short pulse width to realize lower power consumption and higher reliability of high voltage gate driver IC is proposed. Under the control of the feedback signal from the output of the high voltage level shifter, the pulse width of the input narrow pulse can be decreased adaptively without affecting the normal operating function. The proposed self-adaptive pulse generator is implemented in 100 V BCD process. Measured results show that the pulse width reduced from 211.6 to 108.3 ns, the high side operating current decreased from 175.54 to 120.53 µA at 25 °C when operations at 100 kHz, and the pulse width tend to be stable as temperature changes.

Study and Implementation of 600-V High-Voltage Gate Driver IC With the Common-Mode Dual-Interlock Technique for GaN Devices

Gallium nitride (GaN) power device is well known as a favorable alternative of silicon power device for the power management system. However, it is difficult to meet the demand of higher operating frequency when using the traditional high-voltage gate driver IC (HVIC) to control the GaN devices. In this article, we illustrated that the propagation delay of the high-voltage level-shifter structure is the primary factor in limiting the operating frequency of the HVIC, and a new high-voltage level-shifter structure named common-mode dual-interlock (CMDI) level-shifter structure is proposed, which can eliminate both the common-mode transient noise and differential-mode transient noise effectively without adopting resistance-capacitance noise filter. A better tradeoff between the dVS/dt noise immunity capability and the propagation delay can be achieved, which is verified by the numerous theoretical analysis and experimental results. Due to all, the GaN integration technology is not suitable for complicated circuits at present, a 600 V HVIC for GaN device adopting the proposed CMDI level-shifter structure is implemented with normal silicon-based bipolar-CMOS- double-diffused MOSFET (DMOS) technology finally. The experimental results show that it can achieve high dVS/dt noise immunity larger than 100 V/ns, low propagation delay less than 32 ns, and the allowable negative VS swing to -4 V at 5 V supply voltage.

Gate driver IC for enhancement mode GaN power transistors with senseFET reverse conduction detection circuit

Dead-times are necessary in switching output stage to avoid shoot-through current between the high side (HS) and the low side (LS) power transistors. However, excessively long dead-times can lead to unwanted reverse conduction and power loss. Sensing the duration of reverse conductions are especially difficult for high-voltage enhancement mode (e-mode) gallium nitride (GaN) HEMTs due to their fast switching speed. High-precision sensing circuits are required for dead-time correction as the load current changes and to withstand large voltage swings. Traditional CMOS-based sensing circuits (e.g. standard logic gates) are not suitable for GaN-based converters as they can only handle limited voltage ranges. In addition, severe undershoots (up to −4 V) may damage the sensing circuit. Here, a gate driver IC for e-mode GaN power output stages capable of detecting the presence of reverse conduction with a best resolution of 0.66 ns, a dead-time adjustment resolution of 0.33 ns, and with on-chip closed-loop control is presented. In addition, a novel reverse conduction sensing circuit that can accommodate the large voltage swings at the switching node (SW) is also described.

A 600 V high voltage gate driver IC with excellent allowable negative VS bias capability for E-mode GaN power devices

In this paper, a 600 V high voltage gate driver IC with excellent allowable negative VS bias capability is proposed. In order to prevent the bootstrap capacitor from overcharging, a voltage signal from negative voltage sensor is utilized to control the charging path of it when the negative voltage in VS is detected. A bilevel isolated bootstrap circuit is utilized for the level shifter and the subsequent circuit, respectively. It guarantees the normally functions even when VS is lower than − VCC. The proposed 600 V gate driver IC is fabricated in 0.5 μm 600 V Bipolar–CMOS–DMOS process. Measured results show that its basic function is normal even when Vs = − 6 V at 5 V power supply voltage. The quiescent current when Vs = − 6 V is 40.63 μA, which is approximately same with it when VS = 0 V.

Optimization Platform to Find a Switching Pattern of Digital Active Gate Drive for Reducing Both Switching Loss and Surge Voltage

A gate driving for power devices is a key technology to further improve switching characteristics. With the help of digital gate driver IC, the switching behavior of power devices can be enhanced even under high-speed switching. In this paper, an evaluation platform for determining the optimal switching pattern of an active gate drive control is proposed for an inverter circuit. A high speed optimization system is built up to search for an advantageous switching pattern that reduces total switching loss of two power devices in an inverter circuit and constrains surge voltage simultaneously. The proposed online optimization demonstrates its feasibility for the full-bridge inverter circuit, which is rated at 500 V with digital active gate drive control. Experimental results show that the proposed optimization system is able to obtain optimal switching pattern from $64^{60}$ possible combinations of switching patterns within 15 min, which is 6 times faster than the previous study. Optimizations can also conducted under different load current conditions. Eventually, the obtained optimal pattern yields up to 42% reduction in the total switching loss when it constrains surge voltage to minimum compared with the conventional driving pattern.

Three-phase photovoltaic grid inverter system design based on PIC24FJ256GB110 for distributed generation

&lt;span lang="EN-US"&gt;In recent years, the demand for energy generated by photovoltaics has increased because of the cheapness of this energy, especially in the Middle East. This study focuses on the design and implementation of a three-phase photovoltaic inverter system for distribution of generator applications. The three-phase inverter used in this study was designed using GWM 100-01X1 as a three-phase full bridge MOSFET package. The MOSFET full bridge of the three-phase inverter is driven using IR2104 gate driver IC, and the Hall sensors of the voltage and current are used to measure the AC and DC voltage and current. The SPWM signal is generated using a PIC24FJ256GB110 as a microcontroller and interfaced to the full bridge package. Simulation and experimental results are presented to validate the three-phase inverter design.&lt;/span&gt;

A simple and versatile overcurrent protection circuit for power MOSFETs

ABSTRACTThis paper proposes an overcurrent protection (OCP) circuit for power MOSFETs employed in low voltage power converters. The proposed configuration requires only discrete components with a gate driver IC and uses the voltage drop across the device for overcurrent detection. It can operate independently in cycle-by-cycle shutdown and multiple cycle shutdown modes. In coordination with a micro-controller based driver IC input signal generator and controller, the proposed OCP circuit can also operate in a single cycle latch-up and hiccup OCP modes. The performance of the proposed scheme is evaluated experimentally at both, hard and soft fault conditions. By experimentation, it is shown that the proposed circuit can operate in various protection modes and capable of protecting a MOSFET in both, hard and soft fault conditions.

A Smart IGBT Gate Driver IC With Temperature Compensated Collector Current Sensing

Conventional insulated gate bipolar transistor (IGBT) current sensing and protection techniques usually employ discrete sensors, such as lossy shunt resistors, and may involve accessing the high-voltage collector load of the IGBT. This would normally present difficulties for integration. This paper presents an IGBT gate driver IC with a collector current sensing circuit and an on-chip CPU for local data processing. This IC is prototyped using a TSMC 0.18 μm 40 V BCD Gen-2 process. The collector current sensing technique is based on the unique Miller plateau relationship between the gate current and collector current ( $I_{C}$ and $I_{G}$ ) for a particular gate resistance ( $R_{G}$ ). It allows a cycle-by-cycle measurement of IC during both turn- on and turn- off transients without any extra discrete components. The temperature variation is compensated internally by the on-chip CPU using polynomial curve fitting. This technique only monitors the low-voltage signal at the gate terminal, without the need to handle any high-voltage signal on the collector/load side. Measurements using a double pulse test setup show an accuracy of ±0.5 A over the current ranges of 1–30 A for turn- on and 1–50 A for turn- off from 25 to 75 °C.

Bi-Direction Transmissible Gate Driver on Array

In recent years, gate driver using amorphous silicon (a-Si) technology for the TFT-LCD has become the main stream due to the mature manufacturing, low-cost processing, and elimination of the gate driver ICs. However, it’s still three challenges of design the integrated gate driver by a-Si encounters which are the low field-effect mobility, low reliability issue under high voltage stress, and the lack of P-type transistor.

A Simple SR Gate Driving Circuit With Reduced Gate Driving Loss for Phase-Shifted Full-Bridge Converter

The phase-shifted full-bridge (PSFB) converter with synchronous rectifier (SR) is one of the most attractive dc–dc converters for the server power supply due to its high power capability and small secondary ripple current with the output inductor. Moreover, it can more reduce the secondary conduction loss by using parallel-connected mosfet s in SR. However, due to large input capacitance of the parallel-connected mosfet s in SR, the PSFB converter has large SR gate driving loss, which particularly degrades the light load efficiency. Thus, in this paper, one additional resistor is added to the conventional SR gate driving circuit to recycle the gate driving energy. As a result, the proposed circuit can improve the light load efficiency of the PSFB converter without operation mode change, additional controls, and complex circuits. The most advantage of the proposed circuit is that it is very simple and available to any other SR gate driver IC. The validity of the proposed circuit is confirmed by experimental results from a prototype with 340–400 V input and 12 V/66.66 A output.

Active Gate Control in Half-Bridge Inverters Using Programmable Gate Driver ICs to Improve Both Surge Voltage and Converter Efficiency

The requirements for peripheral circuits of power converters are becoming more restrictive due to the enhancement of Si-based power devices and due to practical use of SiC device. In the design of modern high-speed switching converters, the stray inductances and capacitances both in the device package and in the gate drive circuit in addition to those in the main circuit of the power converter must be considered. In these situations, the gate driving technique represents the key technology for enhancement of high-speed switching ability of power devices, as there are design limitations to reduce the stray inductances and capacitances. So far, several active gate control methods have been proposed. Most conventional active gate drivers are configured using analog circuits such as transistors and diodes. Thus, it is difficult to reconfigure their control parameters to fit the stray inductances and capacitances after the implementation of power converter and gate circuits. As a solution to these problems, the authors have proposed a programmable gate driver IC, which is a digitally controlled circuit. This gate driver IC can control the gate current at 63 separate levels, operated by programmable fully digital 12-bit and clock signals. In this paper, an active gate current control based on the load current in a half-bridge inverter with two programmable gate driver ICs is demonstrated. This developed gate control is different to the general current feedback control followed the reference value. It is verified that the proposed active gate control can effectively improve the tradeoff relationship between the surge voltage and switching loss of the pulsewidth modulation half-bridge inverter circuit.

Development of 55” 4K UHD OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs

AbstractWe investigated oxide TFT backplane technology to employ the internal gate driver IC (GIP circuit) on 55” 4K OLED TV panel. For the GIP circuit, we developed the high reliability oxide TFTs, especially only ∆0.4 V Vth degradation under 100‐h long‐term PBTS stress and the short channel length TFTs (L = 4.5um) for narrow bezel. Consequently, we demonstrated the 55‐in 4K OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs.