Gate Drain Research Articles

Enhancement of capacitance benefit by drain offset structure in tunnel field-effect transistor circuit speed associated with tunneling probability increase

The effect of a drain offset structure on the operation speed of a tunnel field-effect transistor (TFET) ring oscillator is investigated by technology computer-aided design (TCAD) simulation. We demonstrate that the reduction of gate–drain capacitance by the drain offset structure dramatically increases the operation speed of the ring oscillators. Interestingly, we find that this capacitance benefit to operation speed is enhanced by the increase in band-to-band tunneling probability. The “synergistic” speed enhancement by the drain offset structure and the tunneling rate increase will have promising application to the significant improvement of the operation speed of TFET circuits.

Organic Phototransistors With Chemically Doped Conjugated Polymer Interlayers for Visible and Near Infrared Light Detection

Organic phototransistors were fabricated by inserting the patterned layers of a chemically doped conjugated polymer, poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS), between the gate electrodes and the gate-insulating layers in order to enable detection of both visible and near infrared (NIR) light. The transistor performance in the dark was slightly improved by the presence of the PEDOT:PSS interlayers. The present organic phototransistors exhibited a gradual increase in drain current (both output and transfer modes) and a noticeable shift in threshold voltage (transfer mode) upon illumination with both visible (550 nm) and NIR (800 and 1000 nm) light. In addition, the net photocurrent could be amplified by increasing either gate voltage or drain voltage. The corrected responsivity was initially improved by increasing the gate voltage but strongly dependent on the combination of gate and drain voltages. Finally, the present organic phototransistors with the PEDOT:PSS interlayers delivered comparable responsivity in both visible and NIR ranges.

Analysis of Reduction in Lag Phenomena and Current Collapse in Field-Plate AlGaN/GaN HEMTs With High Acceptor Density in a Buffer Layer

We make a 2-D transient analysis of field-plate AlGaN/GaN HEMTs with a semi-insulating buffer layer, where only a deep acceptor above the midgap is considered. The deep-acceptor density is varied between 1017 cm−3and $8 {\times 10}^{{17}}$ cm−3. It is studied how the deep-acceptor density and the field plate affect the buffer-related drain lag and gate lag, and current collapse. It is shown that the lags and current collapse are reduced by introducing a field plate. This reduction occurs because electron trapping by the deep acceptors is weakened by the field plate. It is also shown that without a field plate, the drain lag and current collapse increase with increasing the deep-acceptor density as expected, although the gate lag decreases when the deep-acceptor density becomes high in the region between $2{\times 10}^{{17}}$ cm−3and $8 {\times 10}^{{17}}$ cm−3. On the other hand, with a field plate, surprisingly, the lags and current collapse decrease when the deep-acceptor density becomes high. This is attributed to the fact that the reduction in drain lag and current collapse by introducing a field plate becomes more significant when the deep-acceptor density becomes higher.

Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration

An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS. SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the replacement of the diode, the efficiency of the full-wave bridge rectifier is increased up to 11% compared to p-n junction diode based full wave bridge rectifier. The proposed full wave bridge rectifier is a comparably low power circuit. The proposed CMOS based full-wave bridge rectifier is optimized at 45-nm CMOS technology. Cadence experimental simulation and implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.

TCAD Simulation of Breakdown-Enhanced AlGaN-/GaN-Based MISFET With Electrode-Connected p-i-n Diode in Buffer Layer

This paper presents an optimized normally off GaN-based metal–insulator–semiconductor field-effect transistor (MISFET) with an electrode-connected p-i-n diode inserted in the buffer layer, i.e., EC-PIN MISFET, and in which the substrate is removed for the suppression of the vertical leakage current. We provide the simulation results of the proposed MISFET. The EC-PIN MISFET with $\text{L}_{\textsf {gd}}= \textsf {6} ~\mu \text{m}$ presents an excellent breakdown voltage of 1400 V, which attributes to the improvement of electric field distribution in the gate–drain region and the suppression of leakage current by EC-PIN. In addition, the specific on resistance of 0.64 $\text{m}\Omega \cdot \textsf {cm}^{\textsf {2}}$ and Baliga’s figure of merit of 3.08 GW $\,\cdot \,\textsf {cm}^{-\textsf {2}}$ are achieved in the optimized EC-PIN MISFET, indicating a good tradeoff between the specific on resistance and breakdown voltage.

Correlation of AlGaN/GaN high-electron-mobility transistors electroluminescence characteristics with current collapse

We report on the correlation between the electroluminescence and current collapse of AlGaN/GaN high-electron-mobility transistors (HEMTs). Standard passivated devices suffering from severe current collapse exhibited high-intensity whitish electroluminescence confined near the drain contact. In contrast, devices with reduced current collapse resulting from oxygen plasma treatment or GaN capping showed low-intensity reddish emission across the entire gate–drain access region. A qualitative explanation of this observed correlation between the current collapse and electroluminescence is presented. Our results demonstrate that electroluminescence analysis is a powerful tool not only for identifying high-field regions but also for assessing the degree of current collapse in AlGaN/GaN HEMTs.

Mobility Engineering in Vertical Field Effect Transistors Based on Van der Waals Heterostructures.

Vertical integration of 2D layered materials to form van der Waals heterostructures (vdWHs) offers new functional electronic and optoelectronic devices. However, the mobility in vertical carrier transport in vdWHs of vertical field-effect transistor (VFET) is not yet investigated in spite of the importance of mobility for the successful application of VFETs in integrated circuits. Here, the mobility in VFET of vdWHs under different drain biases, gate biases, and metal work functions is first investigated and engineered. The traps in WSe2 are the main source of scattering, which influences the vertical mobility and three distinct transport mechanisms: Ohmic transport, trap-limited transport, and space-charge-limited transport. The vertical mobility in VFET can be improved by suppressing the trap states by raising the Fermi level of WSe2 . This is achieved by increasing the injected carrier density by applying a high drain voltage, or decreasing the Schottky barrier at the graphene/WSe2 and metal/WSe2 junctions by applying a gate bias and reducing the metal work function, respectively. Consequently, the mobility in Mn vdWH at +50 V gate voltage is about 76 times higher than the initial mobility of Au vdWH. This work enables further improvements in the VFET for successful application in integrated circuits.

Radiation hardness of β-Ga2O3 metal-oxide-semiconductor field-effect transistors against gamma-ray irradiation

The effects of ionizing radiation on β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated. A gamma-ray tolerance as high as 1.6 MGy(SiO2) was demonstrated for the bulk Ga2O3 channel by virtue of weak radiation effects on the MOSFETs' output current and threshold voltage. The MOSFETs remained functional with insignificant hysteresis in their transfer characteristics after exposure to the maximum cumulative dose. Despite the intrinsic radiation hardness of Ga2O3, radiation-induced gate leakage and drain current dispersion ascribed respectively to dielectric damage and interface charge trapping were found to limit the overall radiation hardness of these devices.

Gated body-biased full adder

As technology advances into the lower nanometer values, power and delay becomes important parameters to increase the efficiency of the circuit. To reduce the sub-threshold leakage power dissipation in standby mode several low power techniques for CMOS circuits namely drain gating, power gating, drain-header and power-footer gating (DHPF), drain-footer and power- header gating (DFPH) are studied and high speed techniques are achieved by modifying drain gating technique and its variant circuits by adding an additional NMOS sleep transistor at the output node which helps in improvement of switching time are studied. The speed of operation of the circuit is improved by applying Gate Level Body Biasing (GLBB) to the design. Implementation of GLBB technique to the existing design proves to be very efficient in terms of speed. Performance parameters such as average power and average propagation delay are compared using existing and proposed techniques for a full adder circuit. The full adder circuit with various low power techniques are tools in 180nm technology. The circuit is simulated using Cadence Spectre tool. The circuit operates with more speediness after applying biasing and found increase in speed by 15%.

Analysis and Simulation of Low-Frequency Noise in Indium-Zinc-Oxide Thin-Film Transistors

Low-frequency noise (LFN) is investigated in a set of indium-zinc-oxide thin-film transistors (IZO TFTs) with fixed channel width ( $W$ = $10~\mu \text{m}$ ) and different channel lengths ( $L\,\,=10$ , 20, 30, and $40~\mu \text{m}$ ) from sub-threshold, linear to saturation regions. The drain current noise power spectral density is measured as a function of effective gate voltage and drain current. The variation slopes of normalized noise with effective gate voltage are in the range of −1.27 and −1.48, which are close to the prediction of the mobility fluctuation mechanism. According to the $\Delta N-\Delta \mu $ model, the flat-band voltage noise spectral density and Coulomb scattering coefficient are extracted. Subsequently, variations of noise with the drain current in the above threshold region are analyzed by considering the band-gap distribution of the tail states. Finally, the BSIM model is also used to model 1/ $f$ noise in the IZO TFTs. The noise parameter $NOIB$ is extracted which is inversely proportional to the effective gate voltage. Good agreements are achieved between the simulated and measured results in the linear region.

Comparison of bulk FinFET and SOI FinFET

In this study, we compare the differences and advantages between Bulk FinFET and SOI FinFET. The results are simulated by using the ISE TCAD software. By changing the parameters of the gate voltage, drain voltage and gate length to analysis which characteristic is better. Through the experiment results, we demonstrate that the SOI FinFET have the better characteristics than bulk FinFET[1].

A Charge-Based Capacitance Model for Double-Gate Tunnel FETs With Closed-Form Solution

Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field-effect transistors (TFETs) is developed. Good agreements between the proposed model and the numerical simulations have been achieved, which reveal that the tunneling carriers from source have negligible contribution to the channel charges and the gate capacitance can be almost acted as the gate–drain capacitance, which is quite different from that of MOSFETs. This model without involving any iterative process is more SPICE friendly for circuit simulations compared with the table-lookup approach and would be helpful for developing the transient performance of TFET-based circuits.

Gate Drain Underlapping: A Performance Enhancer For HD-GAA-TFET

In this paper, the influence of gate-drain underlapping (GDU) and hetero gate dielectric (HD) has been studied on the switching performance, and parasitic capacitance of gate all around tunnel FET i.e. GAA-TFET. Results thus obtained reveals that via GDU the major impediments of TFET i.e. ambipolar conduction can be suppressed. However, the asymmetric dielectric as gate oxide or HD engineering enhances the ON-state current of TFET. Consequently, by amalgamating both GDU and HD engineering schemes onto GAA-TFET have collectively resulted into suppressed IAMB along with high ION. A comparative analysis of GDU-GAA-TFET, HD-GAA-TFET, and GDU-HD-GAA-TFET with GAA-TFET has been done in terms of switching parameters, bias dependent parasitic capacitance and RF FOMs. Results indicate that GDU-HD-GAA-TFET shows better device performance in terms of the threshold voltage, subthreshold swing SS, and ION/IOFF ratio in comparison to its conventional counterparts. However, an affordable degradation in parasitic capacitance is obtained for GDU-HD-GAA-TFET due to the high-k material near source side that is used to enhance the ION and ION/IOFF ratio. It is found that GDU-HD-GAA-TFET offers an ION/IOFF ratio in the order of 1013 at a SS of 25 mV/decade making it suitable for low power digital applications

Heteroepitaxial Diamond Field-Effect Transistor for High Voltage Applications

The exceptional performance of diamond-based field-effect transistor technology is not restricted to devices that use single crystalline diamond alone. This letter explores the full potential of the heteroepitaxial diamond field-effect transistor (HED-FET). HED-FET devices were fabricated with a long gate–drain length ( ${L}_{\textsf {GD}}$ ) configuration using C–H bonded channels, and a high maximum current density of 80 mA/mm and a high ${I}_ \mathrm{\scriptstyle ON}/{I}_ \mathrm{\scriptstyle OFF}$ ratio of 109 were achieved. Additionally, the HED-FETs showed an average breakdown voltage of ≥500 V and comparatively high breakdown voltage of more than 1 kV. This letter represents a significant step toward the realization of the potential of widely available heteroepitaxial diamond for use in FET applications.

Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective

This paper highlights the output current saturation in a line tunneling-based tunnel FET (LT-TFET). Thereafter, a novel method to extract the onset of saturation voltage ( ${V}_{\textsf {DSAT}}$ ) for LT-TFET is proposed for the first time. A soft saturation state is attained when the electron density in the epitaxial layer over the source region saturates with the drain bias ( ${V}_{\textsf {DS}}$ ) and the conduction band energy ( ${E}_{\textsf {C}}$ ) gets pinned. In addition, at the onset of deep saturation, the electron density in the epitaxial layer over the channel region drops below its doping level and ${E}_{\textsf {C}}$ becomes invariant for any further increase in ${V}_{\textsf {DS}}$ . The difference between gate–drain bias ( ${V}_{\textsf {GD}}$ ) is found to be a constant at the onset of saturation and remains independent of the gate–source overlap lengths ( ${L}_{\textsf {OV}}$ ). A shift in ${V}_{\textsf {DSAT}}$ and ${V}_{\textsf {GD}}$ is also observed with change in the thickness and doping of the epitaxial layer. The transconductance and output resistance are reasonably good in the soft saturation regime. Furthermore, a nominal change of ~5% in the voltage gain ( ${A}_{\textsf {V}}$ ) of a common source amplifier is observed when the n-device is biased in the either soft or deep saturation regime, without any tradeoff in the bandwidth.

SURFACE POTENTIAL DISTRIBUTION MODEL BASED ON ANALYTICAL CHANNEL POTENTIAL APPROXIMATION FOR ULTRA-THIN BODY POLY-SI THIN FILM TRANSISTORS IN LINEAR REGION

For ultra-thin body polycrystalline silicon thin film transistors, the surface potential distribution model, in the linear region, based on the analytical channel potential (CP) approximation is presented without or with the interface charge, respectively. For the purpose of simplifying the process of the solution and with the merit of the clear physical picture, both the surface potential distribution models in the linear region are developed, attributed to the deduction of the analytical CP approximation, by solving one-dimensional Poisson’s equation and applying the Gauss’s law at the poly-Si/oxide interface. Furthermore, the quantitative conditions for the model validity are also developed for both surface potential distribution models. Under these proposed quantitative conditions, both models are verified by the two-dimensional-device simulation on the normalized channel distance under various gate voltages, drain voltages, channel lengths and various areal interface charge densities for the consideration of the interface charge.

Millimeter-Wave Power AlGaN/GaN HEMT Using Surface Plasma Treatment of Access Region

Recess gate AlGaN/GaN millimeter-wave power high-electron-mobility transistors (HEMTs) with N2O plasma treatment on access region have been fabricated. A thin oxide layer formed on the gate region leads to the gate leakage current at least three orders of magnitude lower than that of conventional recess gate HEMT, which results a ultralow off-state current of $9.4 \times 10^{-7}$ mA/mm accompanied by an on/off ratio of over 108, and a suppressed current collapse of about 4% due to a simultaneous plasma treatment on the gate–source and the gate–drain regions. The forward and the reverse gate-bias stress measurements show that the increment in gate current is within an order of magnitude, indicating an excellent stability of the thin oxide layer. The large signal measurement shows that the HEMT with SiN passivation can yield an output power density of 6 W/mm associated with a peak power-added efficiency (PAE) of 46.8% and a gain of 6.8 dB ( ${V}_{\rm \textsf {ds}}= 25$ V), and an output power density of 4.3 W/mm with a PAE of 59.4% and a gain of 6.6 dB ( ${V}_{\rm \textsf {ds}}= 15$ V), respectively, at 30 GHz. The small signal measurement shows that the HEMT without SiN passivation can yield $f_{T}$ and ${f}_{\rm \textsf {max}}$ of 85 and 274 GHz, respectively.

Compact Model for Double-Gate Tunnel FETs With Gate–Drain Underlap

A compact model for double-gate tunnel FETs (TFETs) with gate-drain underlap (DG u-TFET) is proposed which accounts for the alleviation of ambipolar current and Miller capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dg</sub> ) compared with double-gate tunnel FETs (DG TFET). The ON-state current degradation caused by the underlap is reproduced by extending the ideal DG TFET model with an effective resistance between the channel and the drain. Based on the device surface potential, the terminal charge model is developedwhich enables the possibility of circuit simulation and the terminal capacitance is further derived from the definition. This model captures the electrical characteristics of DG u-TFET explicitly and good agreement is achieved compared with TCAD simulation. After the model is implemented into HSPICE, an inverter is established and successfully simulated without convergence problem.

Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis

In this paper, we investigate the impact of a drain-pocket (DP) adjacent to the drain region in Tunnel Field-Effect Transistors (TFETs) to effectively suppress the ambipolar current. Using calibrated two-dimensional device simulation, we examine the impact of DP in Double Gate TFET (DGTFET). We demonstrate the superiority of the DP technique over the existing techniques in controlling the ambipolar current. In particular, the addition of DP to a TFET is able to fully suppress the ambipolar current even when TFET is biased at high negative gate voltages and drain doping is kept as high as the source doping. Moreover, adding DP is complementary to the well-known technique of employ-ing source-pocket (SP) in a TFET since both need similar doping type and doping concentration.

4H-SiC Trench MOSFET With Floating/Grounded Junction Barrier-controlled Gate Structure

A novel silicon carbide (SiC) trench MOSFET with floating/grounded junction barrier-controlled gate structure (FJB-MOS/GJB-MOS) is presented and investigated utilizing Sentaurus TCAD simulations. The split P+ region introduced beneath the trench could better shield the gate oxide from the high electric field in the blocking mode, leading to an enhancement in the breakdown voltage while without significant degradation of other characteristics. As a result, the FJB-MOS with floating P+ shielding exhibits a higher figure of merit related to the breakdown voltage and the specific on-resistance ( ${V}_{\textsf {BR}}^{{\,\textsf {2}}}/{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ ), which is improved by 15% and 49%, respectively, with comparison to those of the state-of-the-art double-trench MOSFET and L-shaped gate trench MOSFET. In terms of the GJB-MOS with grounded P+ shielding, it shows great advantage in reducing the switching losses thanks to the lower specific gate–drain charge ${Q}_{{\:\textsf {gd,sp}}}$ and is more conductive to high frequency applications. Additionally, the formation of the P+ region is aided by the Sentaurus Process and the processing implementation of the proposed structure is discussed.