Gated body-biased full adder

Abstract

As technology advances into the lower nanometer values, power and delay becomes important parameters to increase the efficiency of the circuit. To reduce the sub-threshold leakage power dissipation in standby mode several low power techniques for CMOS circuits namely drain gating, power gating, drain-header and power-footer gating (DHPF), drain-footer and power- header gating (DFPH) are studied and high speed techniques are achieved by modifying drain gating technique and its variant circuits by adding an additional NMOS sleep transistor at the output node which helps in improvement of switching time are studied. The speed of operation of the circuit is improved by applying Gate Level Body Biasing (GLBB) to the design. Implementation of GLBB technique to the existing design proves to be very efficient in terms of speed. Performance parameters such as average power and average propagation delay are compared using existing and proposed techniques for a full adder circuit. The full adder circuit with various low power techniques are tools in 180nm technology. The circuit is simulated using Cadence Spectre tool. The circuit operates with more speediness after applying biasing and found increase in speed by 15%.