Gate-drain Capacitance Research Articles

A Novel 4H-SiC SGT MOSFET with Improved P+ Shielding Region and Integrated Schottky Barrier Diode.

A silicon carbide (SiC) SGT MOSFET featuring a ""-shaped P+ shielding region (PSR), named SPDT-MOS, is proposed in this article. The improved PSR is introduced as a replacement for the source trench to enhance the forward performance of the device. Its improvement consists of two parts. One is to optimize the electric field distribution of the device, and the other is to expand the current conduction path. Based on the improved PSR and grounded split gate (SG), the device remarkably improves the conduction characteristics, gate oxide reliability, and frequency response. Moreover, the integrated sidewall Schottky barrier diode (SBD) prevents the inherent body diode from being activated and improves the reverse recovery characteristics. As a result, the gate-drain capacitance, gate charge, and reverse recovery charge (Qrr) of the SPDT-MOS are 81.2%, 41.2%, and 90.71% lower than those of the DTMOS, respectively. Compared to the double shielding (DS-MOS), the SPDT-MOS exhibits a 20% reduction in on-resistance and an 8.1% increase in breakdown voltage.

Designing process and analysis of a new SOI-MESFET structure with enhanced DC and RF characteristics for high-frequency and high-power applications.

This research introduces a new designing process and analysis of an innovative Silicon-on-Insulator Metal-Semiconductor Field-Effect (SOI MESFET) structure that demonstrates improved DC and RF characteristics. The design incorporates several modifications to control and reduce the electric field concentration within the channel. These modifications include relocating the transistor channel to sub-regions near the source and drain, adjusting the position of the gate electrode closer to the source, introducing an aluminum layer beneath the channel, and integrating an oxide layer adjacent to the gate. The results show that the AlOx-MESFET configuration exhibits a remarkable increase of 128% in breakdown voltage and 156% in peak power. Furthermore, due to enhanced conductivity and a significant reduction in gate-drain capacitance, there is a notable improvement of 53% in the cut-off frequency and a 28% increase in the maximum oscillation frequency. Additionally, the current gain experiences a boost of 15%. The improved breakdown voltage and peak power make it suitable for applications requiring robust performance under high voltage and power conditions. The increased maximum oscillation frequency and cut-off frequency make it ideal for high-frequency applications where fast signal processing is crucial. Moreover, the enhanced current gain ensures efficient amplification of signals. The introduced SOI MESFET structure with its modifications offers significant improvements in various performance metrics. It provides high oscillation frequency, better breakdown voltage and good cut-off frequency, and current gain compared to the traditional designs. These enhancements make it a highly desirable choice for applications that demand high-frequency and high-power capabilities.

Effects of parasitic gate capacitance and gate resistance on radiofrequency performance in LG = 0.15 μm GaN high‐electron‐mobility transistors for X‐band applications

AbstractThe effects of the parasitic gate capacitance and gate resistance (Rg) on the radiofrequency (RF) performance are investigated in LG = 0.15 μm GaN high‐electron‐mobility transistors with T‐gate head size ranging from 0.83 to 1.08 μm. When the device characteristics are compared, the difference in DC characteristics is negligible. The RF performance in terms of the current‐gain cut‐off frequency (fT) and maximum oscillation frequency (fmax) substantially depend on the T‐gate head size. For clarifying the T‐gate head size dependence, small‐signal modeling is conducted to extract the parasitic gate capacitance and Rg. When the T‐gate head size is reduced from 1.08 to 0.83 μm, Rg increases by 82%, while fT and fmax improve by 27% and 26%, respectively, because the parasitic gate–source and gate–drain capacitances reduce by 19% and 43%, respectively. Therefore, minimizing the parasitic gate capacitance is more effective that reducing Rg in our transistor design and fabrication, leading to improved RF performance when reducing the T‐gate head size.

Rapid detection of capture and emission processes in surface and buffer traps: Understanding dynamic degradation in GaN power devices

This study utilized a rapid detection technique, Isothermal Capture Transient Spectroscopy (ICTS), to identify and evaluate defects related to GaN device surface and buffer traps, and investigated the mechanisms by which they affect the dynamic performance of GaN based devices. Interface states and dielectric bulk traps were analyzed, unveiling distinctive device behavior under positive gate pulse-biased ICTS. The observed S-shaped threshold voltage (VTH) instability and dynamic gate-drain capacitance (CGD) issues were directly associated with these interface states and bulk traps. Negative gate pulse-biased ICTS revealed the presence of logarithmic electron trapping originating from extended electron traps, and spatial wide distributed hole traps within the GaN buffer layer, significantly impacting the dynamic on-resistance (RON) during off-state stress of the devices. The rapid assessment capabilities of this method provide a valuable tool for optimizing GaN epitaxy and manufacturing processes.

Improvement of AlGaN/ GaN based HEMT with high performance rate for integrated circuit design for wide range of applications

In the current research work, we focused on the design and analysis of a semiconductor device called High-Elec-tron-Mobility Transistor (HEMT) based on the AlGaN/GaN material system. An Aluminum Nitride spacer,Layer of Nucle-ation along with cap as a AlGaN and barrier of GaN with the channel of AlGaN are incorporated to enhance HEMT device performance.The electrical characteristics of the proposed HEMT are an-alyzed. The Drain Current is found to be 0.18A/mm, indicating the device's ability to handle high current levels. The Electron Concentration is observed to have a maximum value of -96.12electrons/cm3 and varying based on the position in the channel for GaN Barrier thickness is 0.15mm. In the analysis of AC such as Gain of the Maximum Unilateral Power is deter-mined to be 83.41dB, indicating the ability of the device to am-plify signals. The Y-parameters, which characterize the de-vice's behavior at various frequencies of operation, are also de-termined. The capacitance between the electrode region Gate-Source (CGSMIN) is found to be 1.70×10^-11 F/mm, and alike The Capacitance between the electrode region the Gate-Drain Ca-pacitance (CGDMIN) is determined to be 4.7×10^-12 F/mm. Fur-thermore, an Electric Field of 96.51×10^3 V/mm is observed, in-dicating the strength of the electric field across the device. For HEMT device the simulation,The TCAD Silvaco software is be-ing practiced.

Novel SiC Trench MOSFET with Improved Third-Quadrant Performance and Switching Speed.

A SiC double-trench MOSFET embedded with a lower-barrier diode and an L-shaped gate-source in the gate trench, showing improved reverse conduction and an improved switching performance, was proposed and studied with 2-D simulations. Compared with a double-trench MOSFET (DT-MOS) and a DT-MOS with a channel-MOS diode (DTC-MOS), the proposed MOS showed a lower voltage drop (VF) at IS = 100 A/cm2, which can prevent bipolar degradation at the same blocking voltage (BV) and decrease the maximum oxide electric field (Emox). Additionally, the gate-drain capacitance (Cgd) and gate-drain charge (Qgd) of the proposed MOSFET decreased significantly because the source extended to the bottom of the gate, and the overlap between the gate electrode and drain electrode decreased. Although the proposed MOS had a greater Ron,sp than the DT-MOS and DTC-MOS, it had a lower switching loss and greater advantages for high-frequency applications.

Impact of Gaussian Traps on the Characteristics of L-shaped Tunnel Field-effect Transistor

Background: Internet of Things (IoT) applications require high-performance TFET devices that can be efficiently integrated with the cyber world and physical world. Objectives: The impact of introducing Gaussian traps in hetero-junction tunneling-field-effecttransistors (TFET) with an L-shaped gate is presented. Methods: The 2-D TCAD study of different characteristics, like input, output characteristics, and noise spectral density with trap and without trap, has been performed. Results: The simulation results showed that in L-shaped TFET (L_TFET), the high on-current of 1.93×10-5 A/μm, low off-current/leakage current of 1.09×10-13 A/μm, and steep sub-threshold slope (SS) of 24 mV/dec without traps and on-current of 8.46×10-6 A/μm, off-current of 2.86×10- 11 A/μm, and degraded SS with traps are observed. They also indicated that the presence of traps reduces gate-drain capacitance (Cgd), while gate-source capacitance (Cgs) remains unaffected. In addition, in L_TFET, the drain current noise spectral density (SID) of 7.63 E-21 (A2/Hz) at LF and 2.69 E-26 (A2/Hz) at HF while the noise voltage spectral density (SVG) of 7.33 E-4 (V2/Hz) at LF and 2.59 E-15 (V2/Hz) at HF without traps have been investigated in this study. The inverse dependence of drain current noise spectral density on frequency has been observed to lower the effect of noise at HF. Conclusion: It can be concluded that the proposed L_TFET device is free from ambipolarity conduction and can be well-suited for low-power applications.

A Novel Super-Junction DT-MOS with Floating p Regions to Improve Short-Circuit Ruggedness.

A novel super-junction (SJ) double-trench metal oxide semiconductor field effect transistor (DT-MOS) is proposed and studied using Synopsys Sentaurus TCAD in this article. The simulation results show that the proposed MOSFET has good static performance and a longer short-circuit withstand time (tsc). The super-junction structure enables the device to possess an excellent compromise of breakdown voltage (BV) and specific on-resistance (Ron,sp). Under short-circuit conditions, the depletion of p-pillar, p-shield, and floating p regions can effectively reduce saturation current and improve short-circuit capability. The proposed device has minimum gate-drain charge (Qgd) and gate-drain capacitance (Cgd) compared with other devices. Moreover, the formation of floating p regions will not lead to an increase in process complexity. Therefore, the proposed MOSFET can maintain good dynamic and static performance and short-circuit ability together without increasing the difficulty of the process.

Novel Frequency Dependent OFET Attenuator Using ClInPc with Al2O3 Embedded Nanoparticles in Nylon 11 for Flexible Electronics

The Organic field-effect transistors (OFETs) have been largely investigated due to their low-cost manufacturing, flexibility, and lightweight, as well as their optical and electrical characteristics. That allow its application in sensors, amplifiers, attenuators signal filtering, and high-frequency response devices, like biosensing, wearable electronics, optoelectronics, telecommunications, and other potential applications. Throughout this investigation, a ClInPc flexible OFET with Al2O3 embedded particles in nylon 11, was manufactured and characterized to evaluate the optoelectronic and morphological properties. For the manufacturing, a high-vacuum thermal evaporation deposition technique was used, and UV-vis spectroscopy analysis and scanning electron microscopy were conducted to evaluate the optoelectronic and morphological properties. Also, a study regarding the electrical characteristics for different time-dependent wavefunction input signals, changing the input voltage and frequency, has been conducted. The latter was driven to determine the time-response characteristics, gains, phase shift and to determine whether the device function as an attenuator or an amplifier with the selected configuration. The device has been modelled to obtain the OFET operation parameters. A resulting capacitance of 567 pF was calculated. Uniform and continuous films where obtained, which guarantees an efficient charge transport. For all signals the output voltage is lower than that of the input voltage. Also, for the higher frequency the output voltage is decreased compared to lower frequencies. Gains decreasing variation of up to 0.05 indicate the operating application as an attenuator. Phase variation of up to 100 °, resulted while varying the input frequency. The model resulted on a gate capacitance value between 500 and 1180 pF, and gate-drain capacitance value between 50 and 500 pF. All of this could give evidence that state of the art ClInPc flexible OFET device with Al2O3 embedded nanoparticles in nylon 11 could be used toward current high-performance frequency-dependent flexible applications.

Design of a Nonlinear Model of a Pseudomorphic 0.15 μm рHEMT AlGaAs/InGaAs/GaAs Transistor

This paper studies the design of a nonlinear model of AlGaAs/InGaAs/GaAs рHEMT microwave-frequency range transistors with a gate length of 0.15 µm using parametric analysis methods. In the calculations, not only nonlinear current sources but also the dependences of the nonlinear gate-source and gate-drain capacitances on voltages are studied. It is shown that the proposed model makes it possible to describe the IV characteristics of the studied device adequately in the range of drain currents from 0 to 100 mA and the frequency range from 5 to 45 GHz. The error of the model does not exceed 3%.

Design and Analysis of a Wideband K/Ka-Band CMOS LNA Using Coupled-TL Feedback

We demonstrate a low power (PD) 22-33 GHz CMOS low-noise amplifier (LNA) with low noise-figure (NF) and small group-delay (GD) variation for 28 GHz 5G system. Body-selfforward-bias (BSFB) technique, i.e., connection of transistor’s body to drain via body resistance, is used for threshold and supply voltage reduction, and substrate leakage suppression. Gain and NF enhancement at the same PD is achieved because lower VDD and higher transconductance (due to larger bias current) are used. Current-reused topology is used for low PD. Coupled transmission -line (TL) feedback neutralization technique is proposed for further gain and NF enhancement. The feedback from output (drain) to input (gate) via gate-drain capacitance (Cgd) can be cancelled by the feedback from drain (through source) to gate via the coupled TL and gate-source capacitance (Cgs). The LNA consumes 12.2 mW and achieves S21 of 16 dB, 3 dB bandwidth (f3dB) of 11 GHz (22-33 GHz), minimum NF (NFmin) of 2.5 dB, average NF (NFavg) of 3.1 dB, and GD variation of ±6 ps for 22-33 GHz, and figure-of-merit (FOM) of 91.7 GHz. Moreover, the LNA achieves input third-order intercept point (IIP3) of -3 dBm. The NF and FOM are one of the best results ever reported for LNAs with f3dB greater than 7 GHz and PD lower than 15 mW.

A New Analytical Large-Signal Model for Quasi-Ballistic Transport in InGaAs HEMTs Accommodating Dislocation Scattering

A surface-potential-based analytical large-signal model, which is applicable to both ballistic and quasi-ballistic transport in InGaAs high electron mobility transistors, is developed. Based on the one-flux method and a new transmission coefficient, a new two-dimensional electron gas charge density is derived, while the dislocation scattering is novelly taken into account. Then, a unified expression for Ef valid in all the regions of gate voltages is determined, which is utilized to directly calculate the surface potential. The flux is used to derive the drain current model incorporating important physical effects. Moreover, the gate-source capacitance Cgs and gate-drain capacitance Cgd are obtained analytically. The model is extensively validated with the numerical simulations and measured data of the InGaAs HEMT device with the gate length of 100 nm. The model is in excellent agreement with the measurements under I-V, C-V, small-signal conditions, and large-signal conditions.

Analysis of Doherty Power Amplifier Matching Assisted by Physics-Based Device Modelling

The Doherty Power Amplifier represents one of the most promising solutions for the design of high-efficiency power stages. In the widely adopted ABC scheme, the Doherty Amplifier design critically depends on the accuracy of the device model in different operating conditions, ranging from class AB to class C. For the class C case, library models are often inaccurate, while experimental characterization is difficult since it must be carried out in large signal conditions and with varying gate bias. In this paper, we propose an alternative approach, based on physics-based Technological CAD (TCAD) simulations of the complete Doherty amplifier along with the analysis of its individual MAIN (class AB) and AUXILIARY (class C) stages. TCAD simulations seamlessly provide an accurate modelling of the device behavior in all operation classes, including the device turn-on and the nonlinear capacitances, and easily account for the cross-loading effects of the MAIN and AUXILIARY devices through the output network and the effect of the device feedback (gate-drain) capacitance on the input matching. Analyzing a GaAs Doherty stage at 12 GHz, we show that the input phase of the auxiliary stage can be exploited for the Doherty power amplifier optimization in terms of gain, linearity and efficiency, showing a 9 dB gain with less than 1 dB gain variation from back-off to peak power with a power-added efficiency exceeding 45% over a Doherty region extending to a more than 6 dB output power back-off.

Design of a Nonlinear Model of a Pseudomorphic 0.15 μm рHEMT AlGaAs/InGaAs/GaAs Transistor

This paper studies the design of a nonlinear model of AlGaAs/InGaAs/GaAs рHEMT micro-wave-frequency range transistors with a gate length of 0.15 μm using parametric analysis methods. In the cal-culations, not only nonlinear current sources but also the dependences of the nonlinear gate-source and gate-drain capacitances on voltages are studied. It is shown that the proposed model makes it possible to describe the IV characteristics of the studied device adequately in the range of drain currents from 0 to 100 mA and the frequency range from 5 to 45 GHz. The error of the model does not exceed 3%

An Accurate Analytical Model of SiC MOSFETs for Switching Speed and Switching Loss Calculation in High-Voltage Pulsed Power Supplies

Nanosecond output pulse and high efficiency are achieved in high-voltage pulsed power supplies (HVPPSs) by applying silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s), whose switching speed and switching loss are two vital characteristic parameters. However, the existing research on switching characteristics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s is mainly based on the double pulse test circuits with inductive loads, which is not suitable for assessing the devices in HVPPSs with resistive loads. Besides, some simplified analytical methods in HVPPSs lead to poor precision. To accurately predict the switching behavior of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s in HVPPSs for guiding the design of gate driving circuits and power loops, this article proposes an accurate analytical model considering parasitic inductances, nonlinear parasitic capacitances, transfer characteristic, and output characteristics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s. High-precision fitting of transfer characteristic is realized by using the Gaussian function. Besides, the dynamic parasitic gate-drain capacitance is measured by experiment, and three-dimensional curve fitting is performed on the output characteristics to exactly represent <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -resistance. Furthermore, switching speed and switching loss can be directly calculated according to the solved state variables. Finally, the analytical model is verified by experiment, and the effects of gate driving circuits and power loops on switching characteristics are researched in detail.

A SiC asymmetric cell trench MOSFET with a split gate and integrated p+-poly Si/SiC heterojunction freewheeling diode

A new SiC asymmetric cell trench metal–oxide–semiconductor field effect transistor (MOSFET) with a split gate (SG) and integrated p+-poly Si/SiC heterojunction freewheeling diode (SGHJD-TMOS) is investigated in this article. The SG structure of the SGHJD-TMOS structure can effectively reduce the gate-drain capacitance and reduce the high gate-oxide electric field. The integrated p+-poly Si/SiC heterojunction freewheeling diode substantially improves body diode characteristics and reduces switching losses without degrading the static characteristics of the device. Numerical analysis results show that, compared with the conventional asymmetric cell trench MOSFET (CA-TMOS), the high-frequency figure of merit (HF-FOM, R on,sp × Q gd,sp) is reduced by 92.5%, and the gate-oxide electric field is reduced by 75%. In addition, the forward conduction voltage drop (V F) and gate-drain charge (Q gd) are reduced from 2.90 V and 63.5 μC/cm2 in the CA-TMOS to 1.80 V and 26.1 μC/cm2 in the SGHJD-TMOS, respectively. Compared with the CA-TMOS, the turn-on loss (E on) and turn-off loss (E off) of the SGHJD-TMOS are reduced by 21.1% and 12.2%, respectively.

Analysis of Dead-Time Energy Loss in GaN-Based TCM Converters With an Improved GaN HEMT Model

For gallium nitride (GaN) based triangular current mode (TCM) applications, the dead-time has a significant effect on the switching loss. However, previous GaN high electron mobility transistor (HEMT) models focus on the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on/off</small> process without fully considering the effect of the dead-time. Hence, this article analyzes the switching transients under the superfluous and insufficient dead-time and evaluates the dead-time loss with an improved GaN HEMT model. The proposed model improves an existing GaN HEMT model by adding the voltage rising/falling time of the gate driver, the dynamic threshold voltage of Schottky-type GaN HEMTs, and an equivalent gate-drain capacitance obtained from the datasheet. Verified by a GaN-based double-pulse test, the proposed model can more accurately calculate the gate-source voltage and the self-commutated reverse conduction voltage. Verified by a GaN-based TCM Buck converter, the proposed model can predict the dead-time loss well and has higher simulation accuracy for the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> process induced by the inappropriate dead-time.

Analytically modeling electric field of shielded gate trench metal-oxide-semiconductor field effect transistor

Shielded gate trench metal-oxide-semiconductor field effect transistor (SGT-MOSFET) introduces a longitudinal shielding gate connected to the source inside the body, which can assist in depleting the drift region. Its principle of withstanding voltage is different from that of the vertical U-groove MOSFET (VUMOSFET). The SGT-MOSFET will generate two electric field peaks inside the body, which will further optimize the electric field strength distribution of the device and increase the breakdown voltage of the device. Therefore, SGT-MOSFET has not only the advantages of low conduction loss of CCMOSFET, but also lower switching loss. The effects of structural parameters such as the width of the mesa, the thickness of the field oxygen, the depth of the trench and the doping concentration on the electric field strength distribution of SGT-MOSFET are not independent of each other. The more the parameters, the more complex the correlation of their effects on the electric field strength distribution is. In this paper, we take 110V SGT-MOSFET as a research object. Through numerical simulation, theoretical analysis and analytical modeling, the principle of withstanding voltage for different structures and the correlation between structural parameters and electric field strength distribution are studied. The analytical model of the electric field related to various structural parameters of the device is established, which provides a theoretical basis for the design of the device structure. The analytical model of electric field under low current is modified by introducing avalanche carriers, so that the modified analytical results can better match the simulation results. Through the modified electric field analysis model, the field oxygen thicknessin an optimal electric field is 0.68 µm . Comparing with the product of SGTMOSFET with 0.58 µm field oxygen thickness, at the optimal field oxygen thickness of 0.68 µm, the on-resistance of the device is reduced because the on-area of the device is increased; the electric field distribution is more uniform, so the device breakdown voltage increases; the gate-source capacitance decreases and the gate-drain capacitance is almost no change, so the gate-source charge decreases and the gate-drain charge is almost no change, while the total gate charge decreases. As a result, the optimal value parameter FOM&lt;sub&gt;1&lt;/sub&gt; of the device is increased by 18.9%, and the optimal value parameter FOM&lt;sub&gt;2&lt;/sub&gt; is reduced by 8.5%. Therefore, the static and dynamic characteristics of the device are significantly promoted, and the performance of the corresponding products is greatly improved.

A Novel 4H-SiC Double Trench MOSFET with Built-In MOS Channel Diode for Improved Switching Performance

This study proposed a novel 4H-SiC double trench metal-oxide-semiconductor field-effect-transistor (DTMCD-MOSFET) structure with a built-in MOS channel diode. Further, its characteristics were analyzed using TCAD simulation. The DTMCD-MOSFET comprised active and dummy gates that were divided horizontally; the channel diode operated through the dummy gate and the p-base and N+ source regions at the bottom of the dummy gate. Because the bult-in channel diode was positioned at the bottom, the DTMCD-MOSEFT minimized static deterioration. Despite having a 5.2% higher specific on-resistance (Ron-sp) than a double-trench MOSFET (DT-MOSFET), the DTMCD-MOSFET exhibited a significantly superior body diode and switching properties. In comparison to the DT-MOSFET, its turn-on voltage (VF) and reverse recovery charge (Qrr) were decreased by 27.2 and 30.2%, respectively, and the parasitic gate-drain capacitance (Crss) was improved by 89.4%. Thus, compared with the DT-MOSFET, the total switching energy loss (Etot) was reduced by 41.4%.

A compact circuit-level model for single-event burnout in SiC power MOSFET devices

This paper presents a compact circuit-level model for single-event burnout (SEB) in silicon carbide (SiC) metal-oxide field-effect transistors (MOSFETs). Key parameters of the equivalent circuit model of the MOSFET are analyzed and determined in detail, including nonlinear parasitic drain-source capacitance and nonlinear parasitic gate-drain capacitance. The effect of the parasitic bipolar junction transistor is considered and an iteratively optimized double-exponential current source is used to simulate the transient power current generated by incident heavy ions. The equivalent circuit model of the MOSFET is verified by comparing the SPICE simulation curves, TCAD simulation curves, and the curves in the SiC power double trench MOSFET’s datasheet (SCT3080KL). Then, the SEB is caused by heavy ions at various incident positions, linear energy transfer values, drain-source voltage (V ds), and gate-source voltage (V gs) using the TCAD and HSPICE simulations. Simulation results on the SPICE model coincide with the TCAD simulation results. Moreover, this compact model is used to predict the SEB threshold for devices with higher breakdown voltage ratings.