Gate Diffusion Input Technique Research Articles

Low Power Wallace Multiplier Using Gate Diffusion Input Based Full Adders

Now a days, in CMOS circuits leakage power is becoming more and more remarkable in power dissipation. Digital signal processing performs many functions including multiplication which is the prominent one. In the design of energy efficient processor multipliers play a key role in which it determines the DSP processor efficiency. A 4*4Wallace tree multiplier employs gate diffusion input technique to minimize leakage power. It is designed by adopting one bit full adder. In the proposed method, full addersare replaced by4*4 Wallace tree multiplier. Power dissipation majorly occurs in full adders. Hence, minimizing power dissipation in full adders will shrink dissipation of power in multipliers. Here, the proposed work diminishes the leakage power in comparison with the existing method. 

High-efficient reversible full adder realized by dynamic threshold-based gate diffusion input logics

A new 12-transistor reversible full adder (FA) is designed based on carbon-nanotube-field effect transistors (CNTFETs) with 32 nm channel length and an area of 0.2204 μm2, 1 constant input (CI), and 3 garbage outputs (GO). The FA has 3 reversible logic gates in two of its stages that are realized by the gate diffusion input (GDI) technique. In the FA, 2 Toffoli gates with 1 CI and 1 new GDI-reversible-multiplexer are used to generate Sum and Cout, respectively. The multiplexer is 3*3, with two GOs, and a significant area reduction by only two transistors. The inputs of the circuit prevent the excessive increase of GOs and CIs. The Monte Carlo analysis using the HSPICE simulator indicates a better sensitivity of the FA versus fabrication with 6.45%, 1.86%, and 8.01% improvements of maximum values of power, delay, and power-delay-product (PDP). The FA is implemented in a 4-bit, 8-bit, 16-bit, and 32-bit ripple carry adder (RCA), and its superior results are seen. Under 32-bit RCA, the proposed circuit with 4956.30 fJ shows more energy savings compared to most competitors. The extracted results, the different figure of merits (FoMs), and reversibility features represent the proposed circuit as a desirable procedure for future works.

High-efficient and error-resilient gate diffusion input-based approximate full adders for complex multistage rapid structures

Two new approximate full adders (FAs) are proposed by the multiplexers (MUXs) and OR gates with the gate diffusion input (GDI) technique. The cells are named GDI-based MUX approximate FAs (GMAFAs), GMAFA1, and GMAFA2. The threshold voltage drop of the GDI-based circuits is solved by carbon nanotube field-effect transistors (CNTFETs) technology and the dynamic threshold (DT) technique. The FAs have accurate Cout, approximate Sum, and a low number of transistors. They are low-power, high-speed, and energy-efficient for ripple-carry adders (RCAs). The GMAFA1 and GMAFA2 have a total area of 0.068 µm2 and 0.119 µm2, respectively, which demonstrate 27.8% and 54.55% improvement in power-delay-area-product (PDAP) in comparison with the best references. The results of error distance (ED), normalized mean error distance (NMED), power signal-to-noise ratio (PSNR), and energy-saving confirm the accuracy of the presented cells for image processing applications.

Imprecise Subtractor Using a New Efficient Approximate-Based Gate Diffusion Input Full Adder for Bioimages Processing.

Approximate circuits are used in fault-tolerance applications, where carbon nanotube field-effect transistor (CNTFET) technology assists to achieve high performance. In this study, a new 8-transistor approximate full adder (FA) is designed and implemented using CNTFETs based on the gate diffusion input (GDI) technique. The FA is implemented in a ripple carry adder (RCA) and a 4-bit inexact subtractor for bioimages difference detection and finally stroke recognition. The non-full-swing outputs of the presented GDI cells are obviated by the dynamic threshold (DT) technique. The presented FA consumes a power of 2.0446 µW, while its power-delay-product (PDP) is 6.4536 fJ. Also, the superior results of peak signal-to-noise ratio (PSNR), power consumption, and PDP of the proposed subtractor are 30.866 dB, 9.642 µW, and 314.907 fJ, respectively. The FA has an area of 0.161 µm2 while the 4-bit subtractor occupies 2.18 µm2. The presented circuits show efficient performance for bioelectronics integrated circuits (ICs).

A Study on the VLSI Implementation of Fingerprint Thinning Processors Using Hybrid GDI Technique

Although the gate-diffusion input (GDI) technique supports low power and small area compared to conventional CMOS standard cell, it is limited to design larger integrated circuits for several reasons. It is difficult to apply the general RTL design flow of building a GDI standard cell library and designing a chip through logic circuit synthesis. In this paper, we proposed the hybrid GDI technique with new structure. We analyzed the problems of the GDI technique, and the analysis extracted the circuit characteristics of previous CMOS and GDI cells and found the cause of the problems. We proposed the synthesis algorithm for the hybrid GDI design. The performance of hybrid GDI was compared and analyzed using synthesized thinning image processor on 1.8 V, 180n CMOS process. The proposed hybrid GDI technique proved that it could be applied to system-on-a-chip (SoC) design with low power and small cell area.

Efficient GDI-based approximate subtractors for change detection in bio-image processing applications

Three new approximate subtractors are presented based on the gate diffusion input (GDI) technique which benefits from the dynamic threshold (DT) technique using carbon nanotube field-effect transistors (CNTFETs) technology. Proposed-1, Proposed-2, and Proposed-3 subtractors have 10, 8, and 6 transistors with a total area of 0.289 μm2, 0.123 μm2, and 0.065 μm2, respectively. In Proposed-1 and Proposed-2, only XOR and F1 gates are used, which respectively have 2 and 4 errors. To solve the non-full-swing defects of these two circuits, only three F2-GDI gates are used in the Proposed-3, which has 4 errors. The Proposed-1 gives 0.25 as error distance (ED) while two other circuits with a lower area have an ED of 0.5. The Proposed-3 has a simple, low-power, and ground-free structure. The subtractors are implemented in an 8 to 4 non-restoring divider in four different configurations including vertical, horizontal, square, and triangular. The drivers based on Proposed-2 and Proposed-3 are the best circuits with average power-delay-product (PDP) savings of 68.16% and 57.43%, respectively. Finally, the dividers are used in the change detection of medical images, where, the proposed circuits show better circuitry performance and image quality production.

Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters

A new low-power and high-speed multiplier is presented based on the voltage over scaling (VOS) technique and new 5:3 and 7:3 counter cells. The VOS reduces power consumption in digital circuits, but different voltage levels of the VOS increase the delay in different stages of a multiplier. Hence, the proposed counters are implemented by the gate-diffusion input technique to solve the speed limitation of the VOS-based circuits. The proposed GDI-based 5:3 and 7:3 counters save power and reduce the area by 2x and 2.5x, respectively. To prevent the threshold voltage (Vth) drop in the suggested GDI-based circuits, carbon nanotube field-effect transistor (CNTFET) technology is used. In the counters, the chirality vector and tubes of the CNTFETs are properly adjusted to attain full-swing outputs with high driving capability. Also, their validation against heat distribution under different time intervals, as a major issue in the CNTFET technology is investigated, and their very low sensitivity is confirmed. The low complexity, high stability and efficient performance of the presented counter cells introduce the proposed VOS-CNTFET-GDI-based multiplier as an alternative to the previous designs.

A New Low Power, Area Efficient 4-bit Carry Look Ahead Adder in CNFET Technology

In this paper, a new hybrid low-power and area efficient Carry Look-Ahead Adder in CNFET technology based on the full-swing Gate Diffusion Input (GDI) technique is proposed. The proposed CLA design in GDI logic style, not only decreases the circuit area effectively but also decreases the power consumption and delay parameters as well. The proposed design is simulated in HSPICE using the CNFET model parameters. Finally, the simulation results justify a good improvement in the circuit performance parameters such as power consumption, delay, chip size area and power-delay product (PDP) for the proposed CLA circuit.

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

SummaryThe performance of the programmable integrated circuits (ICs) like digital signal processors (DSPs), central processing units (CPUs), and microcontrollers is highly dependent on the magnitude comparators. This article presents a new reliable and efficient 1‐bit comparator based on carbon nanotube field‐effect transistors (CNTFETs) technology. The gate diffusion input (GDI) technique is used to reduce the number of transistors. Also, single swing restoration (SR) transistors and transmission gate (TG) techniques are combined to attain full‐swing outputs with high driving capability. The low internal capacitances and the fewer number of internal nodes of the proposed comparator make it low‐power both in single‐bit and multibit (2‐bit, 4‐bit, 8‐bit, and 16‐bit) implementations. Variations analyses of the circuit and technology parameters are performed that show the cell efficiency. From the layout results, the 1‐bit and 16‐bit comparators occupy 0.1944 μm2 and 37.485 μm2 as the total die area, respectively. The proposed circuit is implemented in image processing in which the best performance compared with state‐of‐the‐art designs regarding hardware complexity, circuitry performance, and image quality assessments are confirmed, by at least 50% improvements of different critical parameters. The resulted figure of merits nominates the cell for future ICs.

Transistor Count Reduction Technique for Clockfree Null-convention Arithmetic Logic Circuits

Null Convention Logic (NCL) is a robust clock-less technique for designing asynchronous delay-insensitive circuits. The traditional complementary metal oxide semiconductor (CMOS) approach is often used for designing NCL circuits, which tends to occupy a large area. To address this issue, a low power design technique Gate Diffusion Input (GDI) is introduced for designing the NCL circuits. This GDI design methodology is the promising alternative for the static CMOS designs, which allows the reduction in area and power consumption while maintaining the low complexity of the logic design. In this paper, a novel GDI based NCL designs are proposed and designed. However, the voltage swings in the GDI approach leads to the considerable amount of voltage drop at the output. This limitation is addressed by using low threshold transistors where a voltage drop is expected, and high threshold transistors are used for the regenerative inverters at the output. The proposed approach has been verified by designing the NCL Ripple Carry Adder (RCA), Unpipelined multiplier, pipelined multiplier and Unpipelined ALU by using the GDI technique. These models are designed and simulated using Cadence Virtuoso and an average of 13.5 % reduction in the transistor count is observed for these GDI based NCL models when compared to the CMOS models.

Design of Low Power and Area Efficient 8 Bit USR Using mGDI Technology

Technology is growing at a faster rate after the evolution of VLSI, which mainly focuses on three major criteria-speed, area and power. All these criteria determine the compactness of a product in order to produce an efficient output at a higher rate by consuming less power. To achieve the above-mentioned factors, an efficient 8-bit Universal Shift Register (USR) has been designed using modified Gate Diffusion Input (mGDI) technique. The results have been simulated using the TANNER EDA tool and found to contribute for low power and area.

Design of High-Speed Low Power Computational Blocks for DSP Processors

In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.

An approximate CNTFET 4:2 compressor based on gate diffusion input and dynamic threshold

Here, a new 4:2 approximate compressor is presented by the gate diffusion input (GDI) technique. Although GDI cells suffer from threshold voltage drop, the dynamic threshold approach and carbon nanotube field-effect transistors are merged to overcome the mentioned problem. The proposed cell has full-swing outputs, while its error and power delay product are at low rates. Therefore, low voltage multipliers that are used in image processing can benefit from the proposed compressor.

New Carry Maskable Adder using Modified Full Swing GDI

Addition is an essential arithmetic operation that is used extensively in processing of digital information. Now a days approximate computing is emerging methodology in area of low power VLSI design that trades off accuracy for faster and power efficient designs. Accuracy Configurable Approximate Adders is an attractive option that provides a flexibility to user to configure adder as accurate or approximate. This paper presents a new Carry Maskable Adder realization based on Full Swing-Modified Gate Diffusion Input (GDI) technique. Proposed design is functionally verified through simulations in LTspice XVII. The performance comparison of proposed design with CMOS based counterpart show that the percentage reduction in delay is 32% while power consumption is reduced by 45%.

Design and Optimization of Reversible Logic Based Magnitude Comparator Using Gate Diffusion Input Technique

The power optimization is one of the biggest challenging issues for designing of VLSI circuits within the advanced technology. The reversible logic is one among the best approaches for low power application. This logic has wide applications in the communication, nanotechnology, digital signal processing, computer graphics, optical computing, etc. In this paper, some proposed reversible magnitude comparator has been designed using the prevailing reversible gates and implemented using gate diffusion input (GDI) technique. The design methodologies are also proposed for the designing of N-bit comparator. The main objective of this paper is to design and implementation of reversible magnitude comparator using some proposed methods and compares them with the existing circuits in terms of constant input, garbage output, number of reversible gates, and quantum cost. The transistor implementations of the proposed comparators are done by the combination of CMOS and GDI technique in EDA Tanner tools. After the design and analysis of proposed comparators it has been found that the proposed-2 logic based 4-bit comparator has lowest quantum cost which is equal to 38 and the proposed-3 logic based 4-bit comparator has lowest constant input and garbage output which is equal to 8 and 13.

A novel ultra-low power 7T full adder design using mixed logic

The key point is to design and implementation of the full adder which provides high-speed, Power efficiency and leas area with good voltage swing”.Where the term ‘Novel’ indicates that If something is so new, genuine and original that it had never been seen, used or even thought of before, call it is considered as ‘novel’ and ‘Ultra low power’ indicates that with the minimal amount of system power is enough for performing the respective operation of its own. In this article, a new High Performance and low power full adder utilizing a distinctive design "Mixed Logic Design" is recommended in implementation. The mixed - logic design combines Modified Gate diffusion input (MGDI) Transmission Gate Logic (TGL), Static CMOS logic, Pass transistor logic(PTL )and various logics which requires the recommended circuit. Full adder is a digital circuit which performs the sum of bits. In many PC’s and various kinds of microprocessors, adders are utilized in the ALU. The traditional Complementary Metal Oxide Semiconductor (CMOS) Full adder consisting of 28-Transistors and is built on a traditional Complementary Metal Oxide Semiconductor structure. GDI technique is low power and high-speed design technique where it takes 10 T.Gate Diffusion Input is one of the circuit design logics which occupies less area, simulates with high speed and power-efficient technique. It entails less count of transistors as correlated to traditional Complementary Metal Oxide Semiconductor technology. But the disadvantage with Gate Diffusion Input technique is that it provides an output having poor logic swing after simulation. The Modified-Gate diffusion input (MGDI ) technique rectifies this issue by implementing FA with 8T.But we are implementing another alternative “Mixed logic design” (combining the GDI, CMOS, TGL, etc logics ) and designing the Circuit with least count of transistors and compare with other unique logics which helps them to simulate the circuit in a power-efficient way and time delay.

WITHDRAWN: High performance IIR filter design with MOD-GDI based array multiplier

Abstract Due to an upsurge in technology, there is a need for development resemblance in portable devices besides its high speed and low power capability. The most critical factors are area, total power dissipation, and propagation delay to estimate a device's performance. Signal processing modules viz. Finite Impulse Response (FIR) or Infinite Impulse Response (IIR) filters are fundamental elementary logics in DSP systems. Performance optimization of a digital IIR filter is always trendy for VLSI DESIGN Engineers. We can also achieve by improving sub-modules' efficiency (like. adder, multiplier, and delay elements) required to realize the filter architecture. This paper aims to extract a layout of the IIR filter implemented using a high-speed 4-bit Array Multiplier. The multiplier for this IIR designed with Modified Gate Diffusion Input (MOD-GDI) technique reduces the additional circuitry, which reduces the area and average power dissipation of overall filter logic. Extracted the layout by using Mentor Graphics EDA tools (with 130 nm technology). Compared to the performance characteristics like area, delay, the power consumption of the proposed and conventional IIR filters. The proposed IIR filter is space-efficient and consumes less power than the traditional IIR filters.

Comparative Study of CMOS Logic and Modified GDI Technique for Basic Logic Gates and Code Convertor

For designing low power digital circuits with better reliability and performance along with less propagation delay, Gate Diffusion Input (GDI) is one such technique. It also significantly reduces the area and delay of a circuit. It is a low power technique which requires a smaller number of transistors to achieve desired outputs with lower design complexity as compared to CMOS logic or Pass Transistor Logic. In a basic GDI cell, 3 terminals namely Gate, Source and Drain are treated as inputs. In this work, circuits like logic gates, and Binary to Gray code convertor have been designed using CMOS logic and a Modified GDI technique. Also, the power dissipation of all these circuits have been calculated and compared for CMOS and Modified GDI. The designing and simulations have been done on Cadence Virtuoso tool in 90 nm technology and power supply voltage has been taken as 1 V.

A New Systematic GDI Circuit Synthesis Using MUX Based Decomposition Algorithm and Binary Decision Diagram for Low Power ASIC Circuit Design

The advances in the new process technology characteristically come with a multitude of new design variables and hence a new set of challenges for the designers to understand the impact of circuit design. During the last decade, widespread deliberations have been specified to the usage of Gate Diffusion Input (GDI) networks in the design of digital core systems; however the logic design has been constructed using transistor-level. Till now there is no specific approach is available for synthesizing GDI circuit that incorporated the impact of signal arrangement and circuit technology. Creation of standard cell library for GDI technique becomes an utmost imperative. In this research work, a regimented synthesis algorithm have been proposed to minimize power and augment performance of the digital circuits through two approaches MUX based decomposition algorithm and Binary Decision Diagram (BDD). The primitive nodes are implemented by GDI logic and CMOS logic for level restoration circuit. This research work is targeted to design sub-micron GDI library which is suitable for the 180 ​nm and 90 ​nm 6-metal layer CMOS n-well process which is offered by MOSIS. The principal focus is to engender a comprehensive library including the core number of essential primitive cells, depicting the detailed layout and transistor-level schematic views of every cell in 180nm and 90 ​nm process, in order to use them as a completely synthesizable library. The signal connectivity models for GDI are presented using MUX and BDD approach. The synthesis of ISCAS Combinational bench mark circuit in CMOS, PTL and GDI technique is also examined in this work along with buffer inclusion procedure for GDI technique.

Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique

For computational arithmetic, a full adder is the primary logic units in VLSI applications. A new full adder circuit design has been presented in this article which is based on input switching activity pattern and gate diffusion input (GDI) technique. The adder has been designed in two stages. The first stage is an XOR–XNOR module, whereas, the final stage is for the required outputs. By using the switching activity pattern of inputs and GDI techniques at each stage, the switching activities of the transistors have been minimized. This improves delay, power consumption and computational complexity. The adder has been designed and evaluated by using the synopsis tool and compared with different existing adder cells found in the literature. It is found that the presented adder shows an improvement at least 72.86% and 66.67% in terms of speed and energy consumption, respectively. Extensive performance analyses of the full adder have also been evaluated at 32 nm CMOS and 32 nm CNFET technology node which shows promising performances in both the technology nodes.