Gate Diffusion Input Technique Research Articles

Design and Analysis of 8-bit Vedic Multiplier in 90nm Technology using GDI Technique

Vedic mathematics is an old mathematics which is more effective than other mathematic procedures. Vedic maths is utilized as a part of numerous applications, for example, hypothesis of numbers, compound duplications, squaring, cubing, square root and solid shape root and so on. Absolutely there are 16 sutras and 14 sub-sutras in Vedic maths. Among those sutras, just 3 sutras and 2 sub-sutras are utilized for augmentation. Multiplier is a very important part of a microprocessor as multiplication is performed continuously in all calculative procedures. This paper is in importance of a 8-bit multiplier designed in 90 nm technology. Urdhva-Tiryakbyham is the sutra that is used for multiplication in Vedic mathematics. Actualizing the different scientific operations utilizing Vedic Mathematics causes us accomplish better speed, bring down unpredictability and higher execution.[2] The technique used is Gate Diffusion Input (GDI) which is a more refined way to design a circuit which less complex than circuits designed by other techniques.

Gate diffusion input based 4‐bit Vedic multiplier design

A multiplier is one of the key hardware blocks in most of the processors. Multiplication is a lengthy, time-consuming task. Vedic multiplication in field programmable gate array implementation has been proven effective in reducing the number of steps and circuit delay. Conventionally at the circuit level, complementary metal oxide semiconductor (CMOS) logic is used to design a multiplier. In CMOS circuits, the area is always an issue. Gate diffusion input (GDI)-based logic has been explored in the literature to reduce the number of transistors for various logic functions. Thus, Vedic mathematics, on the one hand, simplifies the multiplication process and reduces the delay; while on the other hand, GDI technique helps in minimising the transistor count (TC) and reduction in power. Therefore, this study puts forth a GDI logic-based 4-bit Vedic multiplier. To study the effectiveness of the GDI logic, the transient response of a 2-bit Vedic multiplier using CMOS and GDI is compared. For the 4-bit Vedic multiplier, two design approaches are taken into consideration. The performance of these circuits is analysed in terms of average power dissipation, delay, and TC. The effect of supply voltage scaling is also studied. The circuit simulations are carried out at 130 nm for bulk metal oxide semiconductor field effect transistor predictive technology model-based device parameters.

Low Power, Low Area Digital Modulators using Gate Diffusion Input Technique

Audio playback devices like IPODs and MP3 players use Sigma Delta Digital to Analog Converters (DACs) where the size and power consumption is of prime importance. Digital modulator is the most important part of Sigma Delta DACs. This paper presents a new approach for the implementation of a sample digital MASH 1-1 and MOD 2 modulator using Gate Diffusion Input (GDI) technique. The same modulators are also implemented in standard CMOS technology and are compared for the tone frequencies of the audio frequency range. The proposed modulators using GDI method provide a significant improvement in the area, power, and power delay product as compared to CMOS. The gate level simulation using WinSpice with 0.18µm technology confirms the usefulness of the presented structures.

MGDI based parallel adder for low power applications

The paper discusses a unique method to design low power circuits, which is called Gate Diffusion Input (GDI) method. Complex functions can be implemented using only two transistors by using this method. GDI technique allows for reduced power consumption, lower delay, lesser transistor count and decreased area of circuits. It also makes the system design less complex. Full adders and parallel adders, are major building blocks of different digital components like ALUs, DSPs etc. Hence, reducing power consumption of adders is very important. This work aims at building a parallel adder that consumes less power. A GDI based XOR gate is designed using which, a 10T full adder is designed which involves lesser number of devices compared to CMOS Full adder. The threshold loss in full adder is a major pitfall. A standard CMOS process compatible version of GDI cell, modified GDI, mGDI cell is proposed, using which a full adder is built. A 4-bit parallel adder is designed. The proposed technique consumes lesser area and has low power dissipation compared to CMOS design. Power consumption is reduced by 15% compared to CMOS design. Cadence tool at 180 nm is used to implement the designs.

A 0.5 V, 112 nW CMOS Temperature Sensor for RFID Food Monitoring Application

In this paper, a low-power on-chip temperature sensor, which is appropriate for food monitoring in ultra-high frequency radio frequency identification (UHF RFID) passive tag is proposed. For designing sensor core, MOSFET is used as a temperature sensing element and for decreasing the power consumption, and transistors are biased in sub-threshold region. In this sensor for converting the temperature to the digital code, the delay generator and the 10-bit binary counter are utilized. In the design of binary counter, the low-power and high-speed T Flip Flop (T-FF) is used in the digital part of sensor, based on gate diffusion input (GDI) technique. The proposed temperature sensor has 38 nW power consumption, 0.5 V supply voltage and −0.1/0.3 °C error due to the Monte Carlo analysis in the temperature range of −10 to 20 °C. The simulation is done with Cadence software in 180 nm CMOS TSMC Technology, while the chip area is 0.0125 mm2.

Design of high speed and low power 4-bit comparator using FGMOS

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13μm technology with the supply voltage of 1V.

Gate Diffusion Input Technique-Applications and Modifications: An Overview

This paper primarily focuses on Gate Diffusion Input (GDI) technique used for the implementation of digital logic circuits. It also discusses in detail the limitations and modifications of the basic GDI technique. Initially, GDI was a new technique used for low power digital combinational circuit design. This approach provides a reduction in power consumption, propagation delay, and area of digital circuits while the logic design complexity is small. GDI methodology allows implementation of a wide range of complex logic functions using only two transistors. GDI is a new technique for digital circuits implementation with a lot of advantages over existing ones. This paper also analyzes the recent applications of GDI technique which are the implementation of MASH 1-1 and MOD 2 modulator for Sigma Delta DACs and development of full adders for efficient arithmetic operations.

A novel design of low power and high read stability Ternary SRAM (T-SRAM), memory based on the modified Gate Diffusion Input (m-GDI) method in nanotechnology

The conventional complementary metal-oxide semiconductor (CMOS) design techniques confront to the limitation of designing the integrated circuits (ICs), especially memories, with multiple-valued logic (MVL) in nanotechnology. Gate diffusion input (GDI) technique, provides the possibility to design low power logic gates with small chip area and interconnection capacitors while the number of transistors is diminished. In this paper first ternary GDI (t-GDI) cell based on the proposed binary (two-valued) modified GDI (m-GDI) method, which is appropriate for designing circuits using MVL, is designed. Then, by using the standard ternary inverter (STI) gate implemented based on the proposed t-GDI cell with better noise margins and also small standard deviation of results, first novel design of a ternary SRAM (T-SRAM) cell is presented for nano process, which has smaller standby power dissipation and standard deviation for delay of writing and reading cycles, better read static noise margin (RSNM) and lower signal control complexity. The design of specific structure of 4-words×4-bits, ternary SRAM (4×4 T-SRAM) shows that the number of connections, chip area is decreased and power-delay product (PDP) criterion is improved for writing and reading cycles with significant small standard deviation in compare with the other similar T-SRAMs designed.The effects of different process variations such as density, number of CNTs and temperature variations are extensively evaluated by Monte-Carlo simulation, with respect to performance metrics such as delay, power dissipation and PDP of writing and reading cycles, also RSNM parameter for SRAM cells. The comparison exhibits that in all cases the proposed T-SRAM cell showing a substantial small standard deviation and considerable lower variability percentage than state-of-the art SRAM cells. So, the proposed T-SRAM cell design has the lowest sensitivity variations, thus it is an attractive choice for nano technology application in the presence of impact process and temperature variations. The simulation is done with Synopsys H-SPICE simulator in 32nm technology under the condition of variations.

Area and Power Efficient VLSI Architecture for Two Dimensional 16-point Modified Gate Diffusion Input Discrete Cosine Transform

The two-dimensional (2D) Discrete Cosine Transform (DCT) is used widely in image and video processing systems. The perception of human visualization permits us to design approximate rather than exact DCT. In this paper, we propose a digital implementation of 16-point approximate 2D DCT architecture based on one-dimensional (1D) DCT and Modified Gate Diffusion Input (MGDI) technique. The 8-point 1D Approximate DCT architecture requires only 12 additions for realization in digital VLSI. Additions can be performed using the proposed 8 transistor (8T) MGDI Full Adder which reduces 2 transistors than the existing 10 transistor (10T) MGDI Full Adder. The Approximate MGDI 2D DCT using 8T MGDI Full adders is simulated in Tanner SPICE for 0.18㎛ CMOS process technology at 100MHZ.The simulation result shows that 13.9% of area and 15.08 % of power is reduced in the 8-point approximate 2D DCT, 10.63 % of area and 15.48% of power is reduced in case of 16-point approximate 2D DCT using 8 Transistor MGDI Full Adder than 10 Transistor MGDI Full Adder. The proposed architecture enhances results in terms of hardware complexity, regularity and modularity with a little compromise in accuracy.

A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique

Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry-strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence, this paper we are concentrating on the area level &we are reducing the power using modified GDI logic.

Design of low power and high read stability 8T-SRAM memory based on the modified Gate Diffusion Input (m-GDI) in 32 nm CNTFET technology

SRAM designing with greater storage capacity and lower power dissipation with desired stability by employing conventional CMOS technology seems to be impossible due to enhancement of short channel effect and leakage current due to increasing the number of the transistors. Up to now a lot of methods have been proposed in order to improve the performance of the logical circuits based on the CMOS technology, among of them the Gate-Diffusion Input (GDI) technique is an efficient method. In this paper the modified GDI cell (m-GDI) based on the basic GDI cell is proposed and then SRAM cell memory with 8 transistors (8T-SRAM) which uses the proposed GDI cell is presented.Due to the achieved results the stability-power dissipation ratio (SPR), the evaluation parameter in SRAM memories, is improved about 7 for 8T-SRAM which is implemented with a stack forcing method in similar carbon nanotube field-effect transistor (CNTFET) technology.Finally the 4×4 SRAM memory is proposed based on 1×1 SRAM with the help of 8T-SRAM. This memory is presented with array structures for reading and writing blocks.The simulation results reveal that the Power-Delay Product (PDP) term decreases 18% and 36% in the reading and writing cycles respectively for the stack forcing SRAM with the same array.The simulation is done with H-SPICE software in 32nm technology under the condition of 0.9V supply voltage, 500MHz frequency and room temperature.

New low power adders in Self Resetting Logic with Gate Diffusion Input Technique

The objective vividly defines a new low-power and high-speed logic family; named Self Resetting Logic with Gate Diffusion Input (SRLGDI). This logic family resolves the issues in dynamic circuits like charge sharing, charge leakage, short circuit power dissipation, monotonicity requirement and low output voltage. In the proposed design structure of SRLGDI, the pull down tree is implemented with Gate Diffusion Input (GDI) with level restoration which apparently eliminated the conductance overlap between nMOS and pMOS devices, thereby reducing the short circuit power dissipation and providing High Output Voltage VoH. The output stage of SRLGDI has been incorporated with an inverter to produce both true and complementary output function. The Resistance Capacitance (RC) delay model has been proposed to obtain the total delay of the circuit during precharge and evaluation phases. Using SRLGDI, the primitive cells and 3 different full adder circuits were designed and simulated in a 0.250μm Complementary Metal Oxide Semiconductor (CMOS) process technology. The simulated result demonstrates that the proposed SRLGDI logic family is superior in terms of speed and power consumption with respect to other logic families like Dynamic logic (DY), CMOS, Self Resetting CMOS (SRCMOS) and GDI.

Low Power Circuits using Modified Gate Diffusion Input (GDI)

Gate Diffusion Input (GDI) is a technique for designing low power circuits. This technique allows usage of less number of transistors as compared to CMOS logic. The basic GDI cell consists of only two transistors which are used to implement the basic logic functions. Because of less number of transistors, the switching is reduced and hence there will be a less power, delay and also reduced area. Complex functions can also be implemented using this technique. In this paper basic GDI cell is modified to get a “good” logic 0 and it is compared with the CMOS logic. The low power full adder is designed using GDI technique and is modified to get the strong logic zero. Using this modified GDI full adder, 4 bit Ripple Carry Adder and 4*4 Array Multiplier are designed and simulated. The simulation is done using CADENCE VIRTUOSO based on 45nm technology with the supply voltage of 1.2V.

Analysis of GDI Technique for Digital Circuit Design

Power Dissipation of Digital circuits can be reduced by 15% 25% by using appropriate logic restructuring and also it can be reduced by 40% - 60% by lowering switching activity. Here, Gate Diffusion Input Technique which is based on a Shannon expansion is analyzed for minimizing the power consumption and delay of static digital circuits. This technique as compare to other currently used logic design style, allows less power consumption and reduced propagation delay for low-power design of combinatorial digital circuits with minimum number of transistors. In this paper, basic building blocks of digital system and few combinational circuits are analyzed using GDI and other CMOS techniques. All circuits are designed at 180nm technology in CADENCE and simulate using VIRTUOSO SPECTRE simulator at 100 MHz frequency. Comparative analysis has been done among GDI and other parallel design styles for designing ripple adder, CLA adder and bit magnitude comparator. Simulation result shows GDI technique saves 53.3%, 55.6% and 75.6% power in ripple adder, CLA adder and bit magnitude comparator respectively as compare to CMOS. Also delay is reduced with 25.2%, 3.4% and 6.9% as compare to CMOS. Analysis conclude that GDI is revolutionary high speed and low power consumption technique.

Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style

Full adder is one of the most important digital components for which many improvements have been made to improve its architecture. In this paper, we present two new symmetric designs for Low-Power full adder cells featuring GDI (Gate-Diffusion Input) structure and hybrid CMOS logic style. The main design objectives for these adder modules are not only providing Low-Power dissipation and high speed but also full-voltage swing.In the first design, hybrid logic style is employed. The hybrid logic style utilizes different logic styles in order to create new full adders with desired performance. This provides the designer with a higher degree of design freedom to target a wide range of applications, hence reducing design efforts. The second design is based on a different new approach which eliminates the need of XOR/XNOR gates for designing full adder cell and also by utilizing GDI (Gate-Diffusion-Input) technique in its structure, it provides Ultra Low-Power and high speed digital component as well as a full voltage swing circuit.Many of the previously reported adders in literature suffered from the problems of low-swing and high noise when operated at low supply voltages. These two new designs successfully operate at low voltages with tremendous signal integrity and driving capability. In order to evaluate the performance of the two new full adders in a real environment, we incorporated two 16-bit ripple carry adders (RCA). The studied circuits are optimized for energy efficiency at 0.13µm and 90nm PD SOI CMOS process technology. The comparison between these two novel circuits with standard full adder cells shows excessive improvement in terms of Power, Area, Delay and Power-Delay-Product (PDP).

Design of Two High Performance 1-Bit CMOS Full Adder Cells

bit full adder is a very great part in the design of application particular integrated circuits. Power consumption is one of the most significant parameters of full adders. Therefore reducing power consumption in full adders is very important in low power circuits. In this paper, we propose two new structures of hybrid full adders. The first full adder implemented by combining the Swing Restored Lass-transistor Logic and Branch-Based Logic that called, SRPL-BBL cell and the second full adder implemented by combining the Gate-Diffusion Input technique and Majority function that called, GDI-Majority cell. All of the capacitors in this paper replaced with MOSCAP. Simulation results performed by HSPICE in TSMC 0.13 μm CMOS process. The results indicate the superiority the proposed full adders against several low power 1-bit full adder cells in terms of delay, power consumption, and power delay product (PDP).

Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).

Modified Gate Diffusion Input Technique: A New Technique for Enhancing Performance in Full Adder Circuits

Addition is an indispensable operation for any high speed digital system, digital signal processing or control system. The primary issues in the design of adder cell are area, delay and power dissipation. Optimization of several devices for speed and power is a significant issue in low-voltage and low-power applications. These issues can be overcome by incorporating Gated Diffusion Input (GDI) technique. This paper mainly presents the design of 5 different full adder topologies using Modified Gate Diffusion Input Technique. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design. This paper focuses two main design approaches. The former presents the implementation of modified primitive logic cells and its performance issues were compared with GDI and CMOS logic. The latter presents the implementation of 5 different modified GDI full adders and its performance issues. The simulation results reveal better delay and power performance for the proposed modified GDI full adders when compared with the existing GDI technique, CMOS and pass transistor logic at 0.250μm CMOS technologies. Delay and power has been evaluated by Tanner simulator using TSMC BSIM 0.250μm technologies.

A NOVEL CMOS RIPPLE COMPARATOR CELL USING THE GATE- DIFFUSION INPUT TECHNIQUE

In this paper a new implementation of CMOS ripple comparator cell using the Gate-Diffusion Input (GDI) technique is presented. The proposed design using this technique allows for the reduction of power consumption, propagation delay, and the area of digital circuits while maintaining low complexity of logical design. The performance comparison with standard CMOS and GDI logic design techniques is presented. These methods are compared with respect to the number of devices, PDP, and power dissipation. Simulation results confirm that the proposed cell can work at low supply voltage and dissipates low power.