Gate Dielectric Interface Research Articles

High photoresponsivity MoS2 phototransistor through enhanced hole trapping HfO2 gate dielectric

Phototransistor using 2D semiconductor as the channel material has shown promising potential for high sensitivity photo detection. The high photoresponsivity is often attributed to the photogating effect, where photo excited holes are trapped at the gate dielectric interface that provides additional gate electric field to enhance channel charge carrier density. Gate dielectric material and its deposition processing conditions can have great effect on the interface states. Here, we use HfO2 gate dielectric with proper thermal annealing to demonstrate a high photoresponsivity MoS2 phototransistor. When HfO2 is annealed in H2 atmosphere, the photoresponsivity is enhanced by an order of magnitude as compared with that of a phototransistor using HfO2 without annealing or annealed in Ar atmosphere. The enhancement is attributed to the hole trapping states introduced at HfO2 interface through H2 annealing process, which greatly enhances photogating effect. The phototransistor exhibits a very large photoresponsivity of 1.1 × 107 A W−1 and photogain of 3.3 × 107 under low light illumination intensity. This study provides a processing technique to fabricate highly sensitive phototransistor for low optical power detection.

Biological UV Photoreceptors‐Inspired Sn‐Doped Polycrystalline β‐Ga2O3 Optoelectronic Synaptic Phototransistor for Neuromorphic Computing

AbstractIn this study, the authors fabricate Sn‐doped 100‐nm thick polycrystalline β‐Ga2O3 synaptic field‐effect transistors (FETs) emulating optical and electrical spike stimulation. When stimulated by deep ultraviolet (UV) optical spikes or electric voltage spikes at the gate, the devices exhibit several essential synaptic functions of excitatory‐postsynaptic currents (EPSCs), inhibitory‐postsynaptic currents (IPSCs), paired‐pulse facilitation (PPF), spike‐number‐dependent plasticity (SNDP), and spike‐timing‐dependent plasticity (STDP). Following UV optical stimulation, the devices mimic synaptic plasticity with a photogate effect, and the gate voltage stimulation emulates the synaptic weights according to the state of the gate dielectric interface. The β‐Ga2O3 synaptic FET demonstrates synergistic functions in various optoelectronic stimulation modes and successfully mimics the visual memory formation in bees with UV photoreceptors. Moreover, to verify the translation of optoelectrical‐derived synaptic behaviors of β‐Ga2O3 synaptic FETs into artificial neuromorphic computing, handwritten digit image recognition of the Modified National Institute of Standards and Technology dataset is performed using a convolutional neural network, and a learning accuracy of 96.92% is achieved. The realization of these fundamental functions of biological synapses suggests the utility of Ga2O3‐based optoelectronic devices for next‐generation neuromorphic computing.

(Invited) ALD HfO2/β-Ga2O3 Reliability for Future Power Devices

The ultra-wide bandgap (UWBG) semiconductor, β-gallium oxide, has shown great potential in power devices due to its excellent electrical properties and availability of high-quality single-crystalline substrates. Significant progress has been made in the development of β-Ga2O3 metal-oxide-semiconductor (MOS) devices, but further progress will require optimization of the gate-dielectric interface. In this talk, I will describe the investigation of HfO2 dielectric reliability on β-Ga2O3 for future power devices. I fabricated β-Ga2O3 (010) MOS capacitors with atomic layer deposited (ALD) HfO2 and used capacitance-voltage (C-V) and current density-voltage (J-V) techniques to analyze the electrical reliability of ALD HfO2/β-Ga2O3 MOSCAPs. Positive bias stress measurements indicated that HfO2/β-Ga2O3 MOSCAPs are more susceptible to charge trapping at lower electric stress fields compared to HfO2/Si MOSCAPs, likely due to the smaller conduction band offset between HfO2 and β-Ga2O3. Initial flatband voltage shifts were observed for C-V sweeps of HfO2/β-Ga2O3 MOSCAPs, showing the significance of border traps within the dielectric. The lack of mobile holes in the β-Ga2O3 impedes the recombination of these trapped charges in the dielectric while the MOSCAP is in depletion. We observed full recovery from stress-induced charge trapping in the HfO2/β-Ga2O3 MOSCAPs upon deep ultra-violet illumination. The negative valence band offset between the dielectric and semiconductor allows the recombination of photo-generated holes with the trapped dielectric charges [1]. Because many fabrication steps require high temperature processing, we also investigated the thermal reliability of the ALD HfO2/β-Ga2O3 (010) interface. Negligible Ga atom diffusion was observed in secondary ion mass spectrometry (SIMS) depth profiles for anneals at temperatures up to 850°C in N2 environment for 10 minutes. Significant Ga diffusion into the HfO2 layer was observed upon annealing at 900°C, resulting in a severely degraded MOS structure. Additional analysis was performed to investigate the impact of high temperature processing on the MOS electrical characteristics [2].H.N.M was supported by a National Science Foundation Graduate Research Fellowship under Grant No. DGE 1256260. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation. Portions of this work were performed at the Lurie Nanofabrication Facility and J. D. Hanawalt X-Ray MicroAnalysis Laboratory, which are supported by the College of Engineering at the University of Michigan.[1] H. N. Masten, J. D. Phillips, and R. L. Peterson, “Charge trapping and recovery in ALD HfO2/β-Ga2O3 (010) MOS capacitors,” Semicond. Sci. Technol., vol. 36, no. 4, p. 04LT01, Mar. 2021, doi:10.1088/1361-6641/abe880.[2] H. N. Masten, J. D. Phillips, and R. L. Peterson, “Effects of High Temperature Annealing on the Atomic Layer Deposited HfO2 /β-Ga2O3 (010) interface,” Journal of Applied Physics, Accepted.

Top gate engineering of field-effect transistors based on wafer-scale two-dimensional semiconductors

l The threshold voltage of the MoS 2 field-effect transistor was controlled by the work function of top gate metal (Au, Cu, Ag, and Al). l The oxidation of the Al gate produced surplus oxygen vacancy (positive charge) and the dipole effect in the HfO 2 dielectric layer. l Transmission electron microscope was employed to explore the thin Al 2 O 3 interlayer in the Al/HfO 2 interface. l The proposed MoS 2 inverter has an optimized inverter switching threshold voltage and DC voltage gain, which possesses significant potential for integrated multistage logic circuits. The investigation of two-dimensional (2D) materials has advanced into practical device applications, such as cascaded logic stages. However, incompatible electrical properties and inappropriate logic levels remain enormous challenges. In this work, a doping-free strategy is investigated by top gated (TG) MoS 2 field-effect transistors (FETs) using various metal gates (Au, Cu, Ag, and Al). These metals with different work functions provide a convenient tuning knob for controlling threshold voltage ( V th ) for MoS 2 FETs. For instance, the Al electrode can create an extra electron doping (n-doping) behavior in the MoS 2 TG-FETs due to a dipole effect at the gate-dielectric interface. In this work, by achieving matched electrical properties for the load transistor and the driver transistor in an inverter circuit, we successfully demonstrate wafer-scale MoS 2 inverter arrays with an optimized inverter switching threshold voltage ( V M ) of 1.5 V and a DC voltage gain of 27 at a supply voltage ( V DD ) of 3 V. This work offers a novel scheme for the fabrication of fully integrated multistage logic circuits based on wafer-scale MoS 2 film.

Metal–Insulator Transition Driven by Traps in 2D WSe2 Field‐Effect Transistor

AbstractLocalized trap density (Dt) at the 2D channel–gate dielectric interface and its relative strength to carrier–carrier interactions depending on the thickness of the 2D channel can determine the nature of a metal–insulator transition (MIT) in 2D materials. Here, the MIT occurring in WSe2 devices is systematically analyzed by varying the WSe2 thickness from ≈20 nm to monolayer to explore the effects of Dt on MIT. The corresponding critical carrier density increases from ≈8.30 × 1011 to 9.45 × 1012 cm–2 and Dt from ≈6.02 × 1011 to 1.13 × 1013 cm–2 eV–1 as WSe2 thickness decreases from ≈20 nm to monolayer. These large increments in Dt with decreasing thickness of WSe2 induce a strong potential fluctuation in the band of WSe2, causing charge density inhomogeneity in the system, which attributed to tuning the MIT. The critical percolation exponent is strongly dependent on WSe2 thickness with an excellent agreement between the transport data and percolation theory achieved from thinner WSe2 devices, while the transport data measured from multilayer WSe2 devices does not obey the percolation theory. These results suggest that the nature of MIT strongly depends on the WSe2 channel thickness and corresponding unscreened charge impurity and strength of Dt at the interface.

Role of gate electrode in influencing interface trap sensitivity in SOI tunnel FETs

This article reports the response of a silicon-on-insulator tunnel field-effect transistor (TFET) to the presence of semiconductor/ gate dielectric interface traps. A systematic strategy is designed keeping in view different parameters which are related to the gate of the device. Acceptor-like traps, and donor-like traps with Gaussian distribution are considered at the said interface for the entire analysis. Sensitivity % is taken as a figure of merit which measures the deviation of the drain current in presence of traps from the cases with no traps. The effect of temperature on interface traps, and the effect of interface traps on gate leakage current are analyzed. The acceptor-like traps are found to affect the on-state regime, and the donor-like traps are found to affect the ambipolar regime. Analyses on gate–drain underlap, gate–source overlap, shift of entire gate over the device, and gate work-function suggest that the gate electrode plays an important role in determining the sensitivity of the TFETs. Furthermore, noise spectral densities in presence of flicker, diffusion, and monopolar generation-recombination noise sources, and interface traps are reported.

Channel Mobility Boosting in a Poly-Si Channel Using Ge Diffusion Engineering and Hydrogen Plasma Treatment

We demonstrated that channel mobility and cell current could be increased through Ge diffusion engineering and H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma treatment in a poly-Si channel. Even though the Ge channel has a higher intrinsic mobility than the Si channel, a typical poly-SiGe channel has inferior channel characteristics due to high interface trap density (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) and bulk trap density caused by Ge. We propose a novel technique to control the Ge profile along the depth direction of the channel to realize lower Ge concentration at the gate dielectric interface and higher Ge concentration at the channel bulk. This Ge profile could achieve reduced D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> and enhanced channel mobility. Furthermore, the bulk traps caused by Ge are effectively reduced by H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma treatment. These techniques increased the channel mobility to 32%, which can help increase the channel mobility of devices where poly-Si channels are used.

Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si.

Sb-based semiconductors are critical p-channel materials for III–V complementary metal oxide semiconductor (CMOS) technology, while the performance of Sb-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is typically inhibited by the low quality of the channel to gate dielectric interface, which leads to poor gate modulation. In this study, we achieve improved electrostatics of vertical GaSb nanowire p-channel MOSFETs by employing robust digital etch (DE) schemes, prior to high-κ deposition. Two different processes, based on buffer-oxide etcher (BOE) 30:1 and HCl:IPA 1:10, are compared. We demonstrate that water-based BOE 30:1, which is a common etchant in Si-based CMOS process, gives an equally controllable etching for GaSb nanowires compared to alcohol-based HCl:IPA, thereby realizing III–V on Si with the same etchant selection. Both DE chemicals show good interface quality of GaSb with a substantial reduction in Sb oxides for both etchants while the HCl:IPA resulted in a stronger reduction in the Ga oxides, as determined by X-ray photoelectron spectroscopy and in agreement with the electrical characterization. By implementing these DE schemes into vertical GaSb nanowire MOSFETs, a subthreshold swing of 107 mV/dec is obtained in the HCl:IPA pretreated sample, which is state of the art compared to reported Sb-based MOSFETs, suggesting a potential of Sb-based p-type devices for all-III–V CMOS technologies.

(Invited) UV and Gate Stress Induced Defects in Amorphous Indium Gallium Zinc Oxide Thin Film Transistors and Self-Repair

In spite of its high field effect mobility, the a-IGZO TFT’s instability induced by the light illumination and the gate voltage (Vg ) stress is a crucial concern in many electrical and optical applications [1-4]. The wavelength of the illumination light affects the subthreshold swing (S) and threshold voltage (Vth ) [5,6]. In this paper, authors study the defects generation and self-repair phenomena in the a-IGZO TFT under the UV illumination and gate bias stress condition.The inverted, staggered, tri-layer a-IGZO TFT was fabricated on a glass substrate, as shown in Figure 1. The SiOx gate dielectric layer was deposited by PECVD. The 50 nm-thick a-IGZO semiconductor layer was sputtered deposited from an In2O3:Ga2O3:ZnO (1:1:1 mole ratio) target at room temperature. The etch stopper (ES) layer was composed of SiOx (200 nm-thick)/AlOx (20 nm-thick). The source and drain electrodes were made of the Ti/Al/Ti stack. The passivation layer was made of PECVD SiOx (100 nm-thick)/SiNx (100 nm-thick).The a-IGZO TFT was stressed under UV (λ = 395 nm, 0.3 mW cm−2) for 30 min, i.e., UVS (no Vg bias), PBUVS (Vg = 20V, Vd = 0V), or NBUVS (Vg = -20V, Vd = 0V) for 30 minutes at room temperature. Then, the TFT was stored in dark at room temperature or heated to 200°C, followed by measurement of transfer characteristics at V DS = 0.1 V periodically. Figure 2 shows curves of DS vs. relaxation time, i.e., time after releasing the stress condition, at room temperature. Without gate bias, the DS drop was large at the beginning and small later on, i.e., 92% vs. 4%. For the PBUVS stressed TFT, the DS vs. time curve overlaps with that of the UVS stressed TFT. Therefore, defects on the gate dielectric interface were of two types, i.e., quickly or slowly self-repaired. For the NBUVS stressed TFT, defects were recovered in three stages. In the first 5 minutes, they were reduced by 59%. In the next 330 minutes, they were slightly reduced. After 200 hr, they were completely removed. Although at the beginning, the DS of the NBUVS TFT was smaller than that of the UVS or PBUVS TFT, the defect recovery rate of the former was much slower than that of the latter. Separately, the DS vs. relaxation time curve was measured at 200°C. For the UVS or PBUVS stressed TFTs, the S was restored to the original, unstressed value in less than 5 minutes. However, for the NBUVS stressed TFT, the restoring of S progressed in two stages from different mechanisms.The UV illumination caused the negative shift of the V th and increase of S. Defects were created and saturated at the gate dielectric interface as well as in the bulk a-IGZO layer within a short period of UV exposure. The addition of the positive Vg did not affect the mechanism of the defect-generation. Majority of these defects were loosely trapped and could be self-repaired after being stored shortly in dark at room temperature. Defects generated by the NBUVS were difficult to self-repair. At 200°C, all defects were removed in a short period of time.In summary, under the UV illumination condition, the polarity of the bias Vg determines the type of defects generated in the TFT. More detailed discussions on mechanisms of defects generation and repair will be presented. This study provides important information on the reliability the a-IGZO TFT, which is critical to real world applications. Authors acknowledge Prof. Ting-chang Chang, Department of Physics of National Sun Yat-sen University, Kaohsiung, for providing samples. Jingxin Jiang thanks the Doctoral Scientific Research Foundation of Liaoning Province (project No. 201601156), National Natural Science Foundation of China (project No. 6187011861), and China Scholarship Council for proving financial support for her visit to Thin Film Nano and Microelectronics Laboratory, Texas A&M University through the Postdoctoral Research Program.[1] H. Oh, et al., Appl. Phys. Lett. 97, 183502 (2010).[2] J. Jiang, et al., Appl. Phys. Express 7, 114103 (2014).[3] H. Lu, et al., IEEE J. Electron Devices Soc. 5, 504 (2017).[4] T. C. Fung, et al., J. Inf. Display 9, 21 (2008).[5] X. Huang, et al., Appl. Phys. Lett. 100, 243505 (2012).[6] T. Chen, et al., J. Phys. D: Appl. Phys. 50, 42LT02 (2017). Figure 1

(Invited) UV and Gate Stress Induced Defects in Amorphous Indium Gallium Zinc Oxide Thin Film Transistors and Self-Repair

Defects were generated in the amorphous indium gallium zinc oxide thin film transistor under combined ultraviolet light illumination and gate bias stress conditions, which showed as the positive shift of the threshold voltage and the increase of the threshold swing. When exposed to the ultraviolent light without or with the positive gate voltage bias, positively charged defects were quickly generated and saturated at the gate dielectric interface. Majority of these defects were self-repaired at room temperature under air exposure within 5 minutes. On the other hand, under the ultraviolent exposure and negative gate voltage bias condition, two types of defects were generated, i.e., those loosely trapped at the interface and those deeply trapped in the bulk of the gate dielectric layer. At room temperature, the former were quickly self-repaired and the latter were slowly self-repaired. All defects were removed when annealed at 200°C. The understanding of the defect generation and removal mechanism is important for practical applications of this type of oxide thin film transistor.

The effects of carbon on the bidirectional threshold voltage instabilities induced by negative gate bias stress in GaN MIS-HEMTs

In this paper, numerical device simulations are used to point out the possible contributions of carbon doping to the threshold voltage instabilities induced by negative gate bias stress in AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistors. It is suggested that carbon can have a role in both negative and positive threshold voltage shifts, as a result of (1) the changes in the total negative charge stored in the carbon-related acceptor traps in the GaN buffer, and (2) the attraction of carbon-related free holes to the device surface and their capture into interface traps or recombination with gate-injected electrons. For a proper device optimization of carbon-doped MIS-HEMTs, it is therefore important to take these mechanisms into account, in addition to those related to defects in the gate dielectric volume and interface which are conventionally held responsible for threshold voltage instabilities.

Ultralow-Noise Organic Transistors Based on Polymeric Gate Dielectrics with Self-Assembled Modifiers.

In this study, ultralow 1/f noise organic thin-film transistors (OTFTs) based on parylene gate dielectrics modified with triptycene (Trip) modifiers were fabricated. The fabricated OTFTs showed the lowest 1/f noise level among those of previously reported OTFTs. It is well known that 1/f noise causes degradation of signal integrity in analog and digital circuits. However, conventional OTFTs still possess high 1/f noise levels, and the factors that strongly affect 1/f noise are still ambiguous. In this work, the effect of gate dielectric surface on 1/f noise was investigated. First, by comparing OTFTs composed of various channel lengths, we revealed that contact resistance did not affect 1/f noise. Second, we compared parylene OTFTs with and without a self-assembled Trip modifier layer in terms of 1/f noise and trap density of states (Trap DOS). The experiments revealed that a specific Trip modifier layer suppresses the shallow Trap DOS in the OTFTs, leading to a low 1/f noise. Moreover, the 1/f noise level and Trap DOS of various kinds of OTFTs were comprehensively compared, which highlighted that the 1/f noise of OTFTs strongly depends on the gate dielectric surface. Finally, detailed analysis of the gate dielectric interface led us to conclude that the disorder of gate dielectrics and the crystalline quality of semiconductor films are related to shallow Trap DOS, which correlates with 1/f noise.

1/f noise analysis in high mobility polymer-based OTFTs with non-fluorinated dielectric

In this paper, Low Frequency Noise (LFN) characterization of SP500 polymer-based Organic Thin Film Transistors with a nonfluorinated dielectric material is presented. The work aimed at identifying the mechanism of 1/f noise as well as inspecting the quality of the gate dielectric interface. Analysis of the LFN experimental data reveals that the 1/f noise power spectral density (PSD) follows 1/f γ frequency dependence over 1 Hz–10 kHz range. The normalized current noise PSD is found to vary similar to the squared-transconductance drain current ratio with respect to drain current, and is inversely related to the gate-area. Furthermore, the high carrier mobility (on the order of 2–3 cm2/Vs) obtained in these devices indicates that low density of traps exists in the semiconducting organic thin film. Such results ascribed the origin of 1/f noise to the dynamic exchange of charge carriers between the gate-dielectric traps and the channel. In addition, Nst values extracted from the 1/f noise experimental data reflect the enhanced quality of the gate dielectric and the interface it forms with the channel material.

Enhanced n-type β-Ga2O3 (2¯01) gate stack performance using Al2O3/SiO2 bi-layer dielectric

High performance gate stacks are critically needed for the development of β-Ga2O3 power transistors. Significant improvement in the performance of β-Ga2O3 gate stacks is demonstrated in this work by using SiO2 as an interlayer dielectric between Al2O3 and β-Ga2O3. The presence of SiO2 results in an 800× reduction in gate leakage current along with a 1.7× increase in the electric breakdown field. Additionally, the capacitance-voltage characteristics show an increase in flat band voltage (from 0.74 V to 3.25 V) that can enable normally off power transistors. The lowest interface trap density (Dit) of 5.1 × 1010 cm−2 eV−1 for the SiO2/β-Ga2O3 interface has been demonstrated through the use of a piranha clean before SiO2 deposition on β-Ga2O3 for the first time. Reduction (8×) in Dit, hysteresis (from 0.17 V to 0.05 V), and border trap density indicate substantial improvement in the quality of the β-Ga2O3/gate dielectric interface for the Al2O3/SiO2 bilayer stack as compared to only Al2O3.

Research on Threshold Voltage Instability in SiC MOSFET Devices with Precision Measurement

The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

Hybrid bilayer gate dielectric-based organic thin film transistors

Organic thin film transistors (OTFTs) are key building blocks for flexible, low cost electronics systems. They provide a viable alternative for silicon-based electronics with added advantages of low cost and flexibility. However, few issues like high-operating voltage, low-switching speed, high-leakage current and reliability are still a challenge. The overall performance of an OTFT depends on organic semiconductors and gate dielectric interface. In this paper, we review the current status and trends in the choice of dielectric layer for OTFTs. As a starting point, the performance parameters of an OTFT and their dependence on the dielectric layer are briefly discussed. A variety of dielectric materials which includes high-k inorganic, organic, surface coated inorganics and nanocomposites are also presented. The advantages and drawbacks of each of these materials are discussed in detail. We reviewed the latest developments in the dielectric materials especially, self-assembled monolayers (SAMs), hybrid bilayers and nanocomposites. SAM-based OTFTs offer several advantages but shift in the threshold voltage remains a concern. Nanocomposites are a latest addition to the dielectric materials, which offer advantages like solution processing and improved dielectric constant but have a rough surface. A hybrid bilayer that incorporates the inorganic dielectric as a base layer and a thin polymer layer over it to improve the surface properties offers several desirable characteristics over the other choices. Hence, we propose that hybrid bilayer gate dielectrics shall play a pivotal role in improving the OTFT performance.

Bias temperature instability and condition monitoring in SiC power MOSFETs

Threshold voltage shift due to bias temperature instability (BTI) is a major concern in SiC power MOSFETs. The SiC/SiO2 gate dielectric interface is typically characterized by a higher density of interface traps compared to the conventional Si/SiO2 interface. The threshold voltage shift that arises from BTI has significant implications on the reliability of SiC power MOSFETs, hence, techniques for detecting the change in electrical parameters due to gate oxide degradation are desirable. Using accelerated high temperature gate bias stress tests on SiC MOSFETs, it has been shown that the output and transfer characteristics are affected by BTI. This paper presents the impact BTI induced threshold voltage shift on the forward voltage of the SiC MOSFET body diode during third quadrant operation. Using the forward voltage of the body diode during reverse conduction of low currents, threshold voltage shift can be detected, hence, the impact of BTI can be evaluated. The implications of the body diode forward voltage shift on junction temperature measurements are also studied in the context of TSEPs. The findings in this paper are important for engineers seeking to implement condition and health monitoring techniques on SiC power devices.

Mechanism of leakage of ion-implantation isolated AlGaN/GaN MIS-high electron mobility transistors on Si substrate

In this paper, we systematically investigated the leakage mechanism of the ion-implantation isolated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) on Si substrate. By means of combined DC tests at different temperatures and electric field dependence, we demonstrated the following original results: (1) It is proved that gate leakage is the main contribution to OFF-state leakage of ion-implantation isolated AlGaN/GaN MIS-HEMTs, and the gate leakage path is a series connection of the gate dielectric Si3N4 and Si3N4-GaN interface. (2) The dominant mechanisms of the leakage current through LPCVD-Si3N4 gate dielectric and Si3N4-GaN interface are identified to be Frenkel–Poole emission and two-dimensional variable range hopping (2D-VRH), respectively. (3) A certain temperature annealing could reduce the density of the interface state that produced by ion implantation, and consequently suppress the interface leakage transport, which results in a decrease in OFF-state leakage current of ion-implantation isolated AlGaN/GaN MIS-HEMTs.

P‐15: Prediction Method of Device Instability in a‐InGaZnO TFTs under Positive Gate Biases and Thermal Stresses using TCAD Simulation

The experimental and modeling study of bias and thermal stresses induced threshold voltage shift (ΔVTH) in amorphous indium‐gallium‐zinc oxide (a‐IGZO) thin film transistors (TFTs) has been investigated. The evolution of ΔVTH under positive biases and thermal stresses is dominated by charge trapping effect at channel and gate dielectric interface. We can predict the ƊVTH under different bias and thermal stresses using technology computer aided design (TCAD) device simulation if one measures once the device degradation at particular bias and temperature. Using this method, one can optimize the supply bias voltage and extend to predict the device lifetime.

MgZnO High Voltage Thin Film Transistors on Glass for Inverters in Building Integrated Photovoltaics.

Building integrated photovoltaics (BIPV) have attracted considerable interests because of its aesthetically attractive appearance and overall low cost. In BIPV, system integration on a glass substrate like windows is essential to cover a large area of a building with low cost. However, the conventional high voltage devices in inverters have to be built on the specially selected single crystal substrates, limiting its application for large area electronic systems, such as the BIPV. We demonstrate a Magnesium Zinc Oxide (MZO) based high voltage thin film transistor (HVTFT) built on a transparent glass substrate. The devices are designed with unique ring-type structures and use modulated Mg doping in the channel - gate dielectric interface, resulting in a blocking voltage of over 600 V. In addition to BIPV, the MZO HVTFT based inverter technology also creates new opportunities for emerging self-powered smart glass.