Gate Complementary Metal Oxide Semiconductor Research Articles

A Comprehensive Review of Power Consumption in Digital Logic Circuits at Ultra-Low Subthreshold CMOS Levels

In the anticipated spectrum, a lot of work has gone into managing the trade-offs between power, location, and efficiency in the moderate efficiency, moderate power region. However, research into the extremities of this spectrum remains restricted. In particular, there hasn't been enough research done on the extremes of extraordinarily low power consumption with appropriate efficiency and extraordinary efficiency with energy that is within realistic bounds. In this work, very low subthreshold power levels are used to study the power consumption characteristics of digital logic circuits in static Complementary Metal-Oxide-Semiconductor (CMOS) devices. The study shows that operating transistors below their threshold voltage might result in significant energy savings. This research emphasises the significance of subthreshold design strategies for contemporary electronic circuits that aspire for low-power operation without sacrificing efficiency. The results highlight the potential for significant progress in energy-efficient circuit design and highlight the delicate balance between preserving performance and cutting power usage. As a result, this research adds to our understanding of low-power electronics and provides information that may lead to the development of future technologies that are more efficient and sustainable. Keywords— Power consumption analysis, Digital logic circuits, Ultra-low power, Subthreshold operation, Static CMOS gates

Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array

This letter reports a linear multiply-accumulate (MAC) operation conducted on a crossbar memory array based on 28nm high-k metal gate (HKMG) Complementary Metal Oxide Semiconductor (CMOS) and ferroelectric field effect transistor (FeFET). The fabrication is conducted at GlobalFoundries with their standard 28nm technology. The crossbar arrays show a 100% yield in MAC operation on a 300mm wafer. The arrays were divided into <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${8}\times {8}$ </tex-math></inline-formula> segments. The FeFET crossbar arrays were fabricated with access transistors, current-limiter transistors and a current-mode analog-to-digital converter (ADC) on the same wafer. Finally, the data retention characteristics reveal excellent data retention characteristics up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${5}\times {10} ^{{4}}$ </tex-math></inline-formula> seconds, which makes this memory array suitable for carrying out MAC operations in inference engine applications.

DESIGN AND SIMULATION OF LOGIC CIRCUITS AT NANO SCALE BEYOND 32 NANO METERS (FINFET)

With advancement in electronic circuitry, efforts are made to minimize chip size and to attain the desired performance so on changing one parameter the other parameters are effected like variables of field effect transistor like length and width are key variables available to the circuit designer to optimize circuit performance .When in FET’s like CMOS (complementary metal oxide semiconductor) the dimensions are decreased, the short channel effect arises and creates a problem of concern. With this effect an exponential increase in the leakage current happens. In order to reduce the SCE and hence leakage current, a new technology came into being in recent years in which a 3D multiple gate CMOS like FinFet (Fin Field Effect Transistor) has been developed which possess advantages over conventional FET’s and has attracted many engineers and designers to make it more sophisticated. This technology works in the nano meter range to minimize short channel effects. Many companies like Intel, advanced micro device, global foundries have started using FinFet technology. I have carried out my work on the basis of current researches on FinFet technology and how FinFet technology can be used in future to design new logic and memory devices like Inverter, MUX etc. Various parameters of FinFet like reduced short channel effects, less leakage current, low power consumption, less propagation delay and less time delay are discussed. Various mathematical models and software were used to simulate power, delay, power delay product, average power dissipation and energy delay products, this technology was designed to eliminate the problem of SCE by permitting transistors to be scaled down into sub 20nm range. Use of PMT model to design different logic devices at 16nm technology and analyzed output of each circuit. Parameters like Power dissipation, time delay and PDP were compared between MOSFET (CMOS) technology and FinFet technology for each circuit.

The Mixed Logic Style based Low Power and High Speed One-bit Binary adder for SOI designs AT 32NM Technology

Binary adders are the fundamental building blocks to construct Data Processing arithmetic units. A novel one-bit full adder is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the one-bit full adder like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual Voltage Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity and by improving the driving capability. This Mixed logic style provides 83.53% average power consumption and Propagation Delay of 14.02% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of the Full adder logic at different voltages. The 32nm model file is used for MOS transistors.

The Mixed Logic Style based Low Power and High Speed 3-2 Compressor for ASIC designs at 32nm Technology

Compressors are the fundamental building blocks to construct Data Processing arithmetic units. A novel 3-2 Compressor is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the 3-2 compressor like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual value Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity, improving the driving capability and reduced input capacitance with skew gates. Especially the Mixed logic style-3 provides 92.39% average power consumption and Propagation Delay of 99.59% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of compressor logic at different voltages. 32nm model file is used for MOS transistors

Development of a current mirror-integrated pressure sensor using CMOS-MEMS cofabrication techniques

PurposeThis paper aims to describe the fabrication and characterization of current mirror-integrated microelectromechanical systems (MEMS)-based pressure sensor.Design/methodology/approachThe integrated pressure-sensing structure consists of three identical 100-µm long and 500-µm wide n-channel MOSFETs connected in a resistive loaded current mirror configuration. The input transistor of the mirror acts as a constant current source MOSFET and the output transistors are the stress sensing MOSFETs embedded near the fixed edge and at the center of a square silicon diaphragm to sense tensile and compressive stresses, respectively, developed under applied pressure. The current mirror circuit was fabricated using standard polysilicon gate complementary metal oxide semiconductor (CMOS) technology on the front side of the silicon wafer and the flexible pressure sensing square silicon diaphragm, with a length of 1,050 µm and width of 88 µm, was formed by bulk micromachining process using tetramethylammonium hydroxide solution on the backside of the wafer. The pressure is monitored by the acquisition of drain voltages of the pressure sensing MOSFETs placed near the fixed edge and at the center of the diaphragm.FindingsThe current mirror-integrated pressure sensor was successfully fabricated and tested using in-house developed pressure measurement system. The pressure sensitivity of the tested sensor was found to be approximately 0.3 mV/psi (or 44.6 mV/MPa) for pressure range of 0 to 100 psi. In addition, the pressure sensor was also simulated using Intellisuite MEMS Software and simulated pressure sensitivity of the sensor was found to be approximately 53.6 mV/MPa. The simulated and measured pressure sensitivities of the pressure sensor are in close agreement.Originality/valueThe work reported in this paper validates the use of MOSFETs connected in current mirror configuration for the measurement of tensile and compressive stresses developed in a silicon diaphragm under applied pressure. This current mirror readout circuitry integrated with MEMS pressure-sensing structure is new and fully compatible to standard CMOS processes and has a promising application in the development CMOS-MEMS-integrated smart sensors.

A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%

The present methodology of clock distribution inside high-performance central processing unit chip offers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to [Formula: see text]d[Formula: see text]/d[Formula: see text]. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current profile (current versus time), by controlling the current on all the complementary metal oxide semiconductor gates of the clock generation circuits. In our methodology, the time for the chip to reach the maximum saturation current is same when compared with the present linear current ramp methodology. We have also developed a new “optimizer program” to show the existence of a unique single current profile solution, which is different from the present methodology. The proposed method requires understanding of how the minimum value of the power supply voltage (supposed to be always 1[Formula: see text]V for the device) gets changed, when various gates in a clock tree are turned ON at different times ([Formula: see text], parameters of the problem) with different values of current ([Formula: see text], other parameters of the problem). Basically, an ensemble of “[Formula: see text]” number of transistors will be turned ON at time [Formula: see text] while it will pump the total current [Formula: see text]. This understanding generates the derivative function of the minimum noise point with respect to these said parameters, which in turn generates a new set of parameters to optimize the noise point. We have found that this optimizer program works and also converges for the generation of minimum power and ground noise, which is 40% lesser than the conventional approach.

Impact of the RT‐level architecture on the power performance of tunnel transistor circuits

SummaryTunnel field‐effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer–level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining and parallelism make it possibly to fully exploit the distinguishing characteristics of TFETs, and their relevance as competitive TFET circuit design solutions should be explored in greater depth.

High performance high-κ/metal gate complementary metal oxide semiconductor circuit element on flexible silicon

Thinned silicon based complementary metal oxide semiconductor (CMOS) electronics can be physically flexible. To overcome challenges of limited thinning and damaging of devices originated from back grinding process, we show sequential reactive ion etching of silicon with the assistance from soft polymeric materials to efficiently achieve thinned (40 μm) and flexible (1.5 cm bending radius) silicon based functional CMOS inverters with high-κ/metal gate transistors. Notable advances through this study shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using excimer laser. The impact of various mechanical bending and bending cycles show undeterred high performance of flexible silicon CMOS inverters. Future work will include transfer of diced silicon chips to destination site, interconnects, and packaging to obtain fully flexible electronic systems in CMOS compatible way.

Titanium Silicide/Titanium Nitride Full Metal Gates for Dual-Channel Gate-First CMOS

We demonstrate a thermally stable titanium silicide/titanium nitride (TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> /TiN) full metal gate (FMG) for dual-channel gate-first high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> /metal gate complementary metal–oxide–semiconductor technology. Unlike prior tungsten-based FMG, the simple TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> /TiN gate electrode does not require any additional barrier layer preventing oxygen down-diffusion during high-temperature processing, as the TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> itself blocks oxygen. With HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based gate dielectrics and without any oxygen scavenging scheme, we thus demonstrate a capacitance-equivalent thickness in inversion ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\mathrm {inv}})$ </tex-math></inline-formula> of 1.11 nm, corresponding to an equivalent oxide thickness of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 0.7$ </tex-math></inline-formula> nm. Silicon channel nFET and silicon germanium channel pFET parametrics are similar to those of control devices utilizing a conventional a-Si/TiN metal-inserted poly-Si stack (MIPS) gate, while providing superior gate sheet resistance. By supplanting MIPS with such an FMG, we anticipate that contacted gate pitch can be scaled aggressively via reduced gate height and borderless source/drain contacts.

Logic Gates Design and Simulation Using Spatial Wavefunction Switched (SWS) FETs

This paper presents the design and modeling of logic gates using two channel spatial wavefunction switched field-effect transistors (SWSFETs) it is also known as a twin-drain MOSFET. In SWSFETs, the channel between source and drain has two or more quantum wells (QWs) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum wells layers and it causes the switching of charge carriers from one channel to other channel of the device. The first part of this paper shows the characteristics of n-channel SWSFET model, the second part provides the circuit topology for the SWSFET inverter and universal gates- NAND, AND, NOR,OR, XOR and XOR. The proposed model is based on integration between Berkeley Short-channel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level. The results show that all basic two-input logic gates can be implanted by using n-channel SWSFET only, It covers less area compared with CMOS (Complementary metal–oxide–semiconductor) gates. The NAND-NOR can be performed by three SWSFET, moreover the exclusive-NOR “XNOR” can be done by four SWSFET transistors also AND, OR, XOR gates require two additional SWSFET for inverting.

Crosstalk Analysis of Current-Mode Signalling-Coupled RLC Interconnects Using FDTD Technique

ABSTRACTIn nanometre regimes, interconnect crosstalk noise has serious implications as it affects the signal integrity of the system. An accurate analysis of crosstalk effects is very essential and a critical issue. This paper efficiently models and analyses the crosstalk effects in current-mode signalling (CMS) multiline-coupled-distributed resistance-inductance-capacitance (RLC) interconnects. The interconnects are driven by complementary metal-oxide-semiconductor (CMOS) gates. The non-linear behaviour of metal-oxide-semiconductor (MOS) transistors in CMOS gate is characterized by an nth power law model. Both inductive and capacitive couplings have been considered to incorporate coupling effects in interconnects. The model is formulated using a finite-difference time-domain (FDTD) technique. The functional and dynamic crosstalk effects have been analysed for different interconnect lengths and varying transition time for the first time in CMS interconnects. The efficacy of CMS interconnects is evaluated by comparison with the conventional voltage-mode signalling (VMS) interconnects. It is analysed that CMS interconnects have lesser crosstalk-induced delay than VMS interconnects. Also, normalized undershoot voltage in CMS interconnects is lesser as compared to VMS signalling interconnects. The results are validated using simulation program with integrated circuit emphasis simulations. The analyses have been carried out for 32 nm technology node.

(Invited) Integration Challenges of Ferroelectric Hafnium Oxide Based Embedded Memory

System on chip (SoC) embedded memory solutions promise small form factors and high operating speed, as well as a high energy and cost efficiency. Single cell scalability and basic memory parameters such as data retention, cycling endurance and disturb characteristics on array level are important aspects in stand-alone memory development and can serve as a guideline for embedded solutions. However, one of the key aspects in embedded memory development is compatibility of the memory technology to its underlying complementary metal oxide semiconductor (CMOS) platform. This includes the voltage requirements for logic and memory operation, the need for additional lithographic steps and minimally CMOS invasive integration efforts, as well as the introduction of new materials and related contamination concerns. Especially in state of the art high-k metal gate (HKMG) CMOS technologies at minimum feature size (F) these aspects proof rather challenging when searching for a suitable embedded memory solution. As a consequence most approaches result in large memory cells of multiple F2 or leave a BEoL integration of the memory cell as the only viable option.With the introduction of ferroelectric hafnium oxide, however, a scalable one-transistor (1T) memory solution derived from the conventional HKMG transistor was presented for the 2X nm node. The therewith close resemblance of the memory and logic transistor appears ideally suited for combining nonvolatile data storage and logic circuitry on the same chip. Nevertheless, in order to fulfill these expectations and to ease manufacturing issues this resemblance has to be as close as possible. In the context of a minimally invasive memory integration strategy this means that ideally the ferroelectric hafnium oxide based memory transistor has to adapt to the HKMG transistor in terms of thermal budget and post treatments, vertical and lateral dimensions, the use of stress engineering, as well as metal gate and work function engineering. Based on experimental gate first transistor and metal insulator metal (MIM) capacitor data these aspects together with embedded memory requirements will be analyzed and critically discussed.

Experimental observation of voltage amplification using negative capacitance for sub-60 mV/decade CMOS devices

In this study, an experimental study of negative capacitance is performed in order to overcome the physical limit of subthreshold slope (SS), SS ≥ 60mV/decade at 300 K, which is originated from (i) using the thermionic emission process in complementary metal-oxide-semiconductor (CMOS) technology and (ii) non-scalability of the thermal voltage kBT/q (i.e., in order to realize SS lower than 60mV/decade at 300 K). To make the surface potential higher than the gate voltage, a step-up voltage amplifier is included in the CMOS gate stack using a ferroelectric capacitor implemented with ferroelectric material. The measured SS in long-channel CMOS transistors is 13 mV per decade at 300 K. A simple connection of the ferroelectric capacitor to a complementary metal oxide semiconductor (CMOS) gate electrode would provide a new evolutionary pathway for future CMOS scaling.

Design and fabrication of field-effect biosensors for biochemical detection.

Biochemically sensitive field-effect sensors are fabricated with simplified chip technology. Its fabrication process flow is designed based on metal gate complementary metal-oxide semiconductor technology, in which only six pattern masks are employed. The sensors are measured as field modulation resistors since they are made in its depletion mode. The milliampere magnitude response of conducting currents from certain biochemical materials achieves distinct sensitivity when measured on our fabricated sensors with different sensitive areas of W/L = 4.2 and 20.0. To check the stability of the sensor, up to 20 repeated tests are conducted on the same sensor chip operated in its three states, in which no materials (blank state, called 'blank'), pure water and biochemical materials are coated on its gate dielectric film, respectively. Measured results show that the response currents for certain materials are distributed in certain current range. Taking the response current of blank as a reference value, the response current of pure water is positive but very close to that of blank because of the small electric dipole properties of pure water. However, the response current of biochemical materials are negative and far apart from that of blank, because the biochemical materials have large electric dipole properties and clearly show measurement resolution.

Optimization of fat tree encoder for ultra high speed analog to digital converter using 45 nanometer technology

The design of high speed, compact and low power fat tree encoder circuits using static CMOS gates is presented. In this paper, we propose a modified 3 bit fat tree encoder (FTE) that can operate in high frequency without a sophisticated circuit structure. In addition, the technique of hardware sharing is adopted in this design to reduce the number of transistors. The study uses complementary metal oxide semiconductor (CMOS) 45nm-technology. The proposed static design has improved delay and power compared to a conventional ROM encoder circuit implementation. The simulation result indicates that it functions successfully and works at 200-MHz speed. The average power consumption of the circuit under room temperature is 20.7nW. The total core area is 0.011mm2. As expected, the proposed design can be easily integrated in various kind of digital application.

Optimum Reliability Sizing for Complementary Metal Oxide Semiconductor Gates

Introducing redundancy at the device-level has been proposed as the most effective way to improve reliability. With the remarkable reliability of the complementary metal oxide semiconductor (CMOS) transistors the semiconductor industry was able to fabricate, the research on device-level redundancy has reduced. However, the increasing sensitivity to noise and variations (due to the massive scaling) of the CMOS transistors has led to a revival of interest in device-level redundancy schemes during the last decade. In this paper, we introduce a novel transistor sizing method that can be used to significantly reduce the probability of failure of CMOS gates due to threshold voltage variations. The method has almost no impact on the occupied area. For a given reliability target, the proposed sizing method provides very large scale integration (VLSI) designers with several transistor sizing options which allow them to optimize the trade-off between reliability and the traditional power-area-delay design parameters. The simulation results reported in this paper will show that the proposed transistor sizing method can improve the reliabilities of classical INV, NAND-2, and NOR-2 CMOS gates by factors of more than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> , 10, and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> respectively, while the area is increased by less than 50%.

Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal–Oxide–Semiconductor Device and Inverter Circuit

Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal–Oxide–Semiconductor Device and Inverter Circuit

Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal–Oxide–Semiconductor Device and Inverter Circuit

This work estimates electrical and transfer-characteristic fluctuations in 16-nm-gate high-κ/metal gate (HKMG) metal–oxide–semiconductor field effect transistor (MOSFET) devices and inverter circuit induced by random interface traps (ITs) at high-κ/silicon interface. Randomly generated devices with two-dimensional (2D) ITs at HfO2/Si interface are incorporated into quantum-mechanically corrected 3D device simulation. Device characteristics, as influenced by different degrees of fluctuation, are discussed in relation to random ITs near source and drain ends. Owing to a decreasing penetration of electric field from drain to source, the drain induced barrier lowering (DIBL) of the edvice decreases when the number of ITs increases. In contrast to random-dopant fluctuation, the screening effect of device's inversion layer cannot effectively screen potential's variation; thus, devices still have noticeable fluctuation of gate capacitance (CG) under high gate bias. The cutoff frequency decreases as increasing the number of ITs owing to the decreasing transconductance and increasing CG. Decreasing on-state current and increasing CG further result in increasing intrinsic gate delay time (τ) when the number of ITs increases. The fluctuation magnitude of DIBL, cutoff frequency, and τ above is increased as the number of ITs increases. Even for cases with the same number of random ITs, noise margins (NMs) of the 16-nm-gate complementary metal–oxide–semiconductor inverter circuit are still quite different due to the different distribution of random ITs. The NMs of inverter circuit increase as the number of random ITs increases; however, the NMs' fluctuations are increased due to the more sources of fluctuation at HfO2/Si interface of HKMG devices.

Using Bayesian Networks to Accurately Calculate the Reliability of Complementary Metal Oxide Semiconductor Gates

Scaling complementary metal oxide semiconductor (CMOS) devices has been a method used very successfully over the last four decades to improve the performance and the functionality of very large scale integrated (VLSI) designs. Still, scaling is heading towards several fundamental limits as the feature size is being decreased towards 10 nm and less. One of the challenges associated with scaling is the expected increase of static and dynamic parameter fluctuations and variations, as well as intrinsic and extrinsic noises, with significant effects on reliability. Therefore, there is a clear, growing need for electronic design automation (EDA) tools that can predict the reliability of future massive nano-scaled designs with very high accuracy. Such tools are essential to help VLSI designers optimize the conflicting tradeoffs between area-power-delay and reliability requirements. In this paper, we introduce an EDA tool that quickly and accurately estimates the reliability of any CMOS gate. The tool improves the accuracy of the reliability calculation at the gate level by taking into consideration the gate's topology, the reliability of the individual devices, the applied input vector, as well as the noise margins. It can also be used to estimate the effect on different types of faults and defects, and to estimate the effects of enhancing the reliability of individual devices on the gate's overall reliability.