Gate Bias Stress Research Articles

Dual-source device architecture for self-diagnosis and correction of gate bias-stress instability in flexible transparent ZnO thin-film transistors

Flexible transparent ZnO thin-film transistors (TFTs) have gained momentum during the last decade because of the increasingly emerging demands in flexible transparent displays and wearable electronics industry. However, the instability issue regarding a deviation of turn-on voltage under gate bias stress has remained unsettled, greatly impeding the progress towards practical applications. Here we present a solution to this problem by adopting a new dual-source device architecture to self-diagnose and pull back the deviated turn-on voltage. The dual-source TFTs were fabricated on PEN substrate by conventional UV photolithography with ZnO channel prepared by magnetron sputtering technique. By combining the presented device architecture with a rapid correction process, the turn-on voltage shift was reduced to 0.1 V under −15 V gate voltage bias stress of 5000 s, which favors low power consumption circuits by preventing the TFTs drifting from enhancement to depletion mode. To illustrate its unique working mechanism, device physics simulation, square-law model deduction and circuit current analysis were carried out. The methodology we developed enhances the stability of flexible transparent oxide TFTs and can be adapted in other microelectronic and optoelectronic devices.

Electrical characteristics of amorphous indium‐tin‐gallium‐zinc‐oxide TFTs under positive gate bias stress

In this Letter, the authors investigate the electrical characteristics of amorphous indium-tin-gallium-zinc-oxide (a-ITGZO) thin-film transistors (TFTs) under positive gate bias stress (PBS). An as-prepared a-ITGZO TFT exhibits a mobility of 26.05 cm2/V⋅s, subthreshold swing of 183 mV, threshold voltage of −0.33 V, and on/off ratio of 1.34 × 108. These electrical characteristics deteriorate upon the application of PBS. The proposed experiments and simulations reveal that this deterioration can be attributed to the increase in the density of acceptor-like conduction band-tail states and donor-like Gaussian states within the bandgap of the a-ITGZO channel material.

Abnormal threshold voltage shift caused by trapped holes under hot-carrier stress in a-IGZO TFTs

In the investigation of the reliability of a back-channel-etching type amorphous InGaZnO thin film transistor, we found that hot carrier stress has caused an abnormal parallel negative threshold voltage shift in the ID–VG measurement. An electrical measurement method named drain stress was established to investigate this instability. Through the analysis of recovery behavior, gate bias stress and Silvaco simulation, we confirmed that holes from the drain side inject into the passivation layer and/or back-channel interface region rather than into the gate insulator under the transverse electric field. A physical model is proposed to verify this electrical degradation behavior. This work demonstrates that drain stress is valuable in examining the quality of the passivation layer in thin film transistors.

Positive Bias Stress Instability of InGaZnO TFTs With Self-Aligned Top-Gate Structure in the Threshold-Voltage Compensated Pixel

The instability induced under positive gate-bias stress (PBS) in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with self-aligned top-gate coplanar structure is investigated under the threshold-voltage $({V}_{T})$ compensated pixel scheme in the backplane of organic light-emitting diode displays and compared with that under a constant-PBS scheme . Based on the investigation, which combines the extraction of density of states, the decomposition of ${V}_{T}$ shift ( $\Delta {V}_{T}$ ), and technology computer-aided design, the unreleased electric field across the gate insulator (GI) and the maintained electron concentration are observed under the ${V}_{T}$ -compensated PBS condition. Indeed, the main difference between the two schemes originates from increasingly activated electron trapping within the GI deep-level traps and from the excessive oxygen-related peroxide bond-breaking in the a-IGZO-active film, i.e., O22− + $2 {e}^{-} \to$ O2− + O2−. Although the latter is quantitatively much smaller than the former, the two mechanisms are closely related to each other and should be jointly optimized. This is because a large amount of oxygen interstitials can generate a high density of GI electron traps. Since the GI deep-level trapping results in noticeable $\Delta {V}_{T}$ with an increase in PBS time, our results suggest that the $\Delta {V}_{T}$ should be seriously underestimated with respect to either the estimation of pixel lifetime or the assessment of ${V}_{T}$ -compensated pixel-circuit schemes, if the reliability/acceleration test relies only on the constant-PBS-based single-TFT device test.

Investigation of Hot-Carrier Degradation in 0.18-$\mu$ m MOSFETs for the Evaluation of Device Lifetime and Digital Circuit Performance

In this work, we investigate the hot-carrier reliability in $0.18{\mu}\text{m}$ MOSFET technology that is being extensively employed in various analog/digital applications. Hot-carrier degradation in MOSFETs is known to follow power-law relation where the time exponent of the degradation curve can be utilized to quantify the device ageing. Here, we examine the dependency of time power-law exponent on different gate stress bias to determine the physical mechanism responsible for device degradation. Extensive consideration is given to the maximum impact ionization condition Vgs = Vds/2 and maximum hot-electron injection condition Vgs = Vds . Time evolution of degradation curve depicts changing slope with increasing stress duration. This variation in time power-law exponent over different stress time intervals is an important indicator of changing degradation mechanism as the device ages. Since the operating conditions for a device directly relates to its targeted application, therefore DC lifetime prediction under the influence of different Vgs/Vds stress bias combinations is performed to determine the limiting case challenging the circuit integrity. Also, the impact of hot-carrier degradation on the circuit delay under the aforementioned stress conditions is evaluated for typical digital CMOS circuits. Effective switching current methodology is employed for the delay analysis in transistor stacks that comprise inverter, NAND, and NOR circuits to show the adverse effects of the damage caused by the hot-carriers.

Influence of Oxygen-Plasma Treatment on In-Situ SiN/AlGaN/GaN MOSHEMT with PECVD SiO2 Gate Insulator.

The influence of oxygen–plasma treatment on in situ SiN/AlGaN/GaN MOS high electron mobility transistor with SiO2 gate insulator was investigated. Oxygen–plasma treatment was performed on in situ SiN, before SiO2 gate insulator was deposited by plasma-enhanced chemical vapor deposition (PECVD). DC I-V characteristics were not changed by oxygen plasma treatment. However, pulsed I-V characteristics were improved, showing less dispersion compared to non-treated devices. During short-term gate bias stress, the threshold voltage shift was also smaller in a treated device than in an untreated one. X-ray photoemission spectroscopy also revealed that SiO2 on in situ SiN with oxygen–plasma treatment has an O/Si ratio close to the theoretical value. This suggests that the oxygen plasma treatment-modified surface condition of the SiN layer is favorable to SiO2 formation by PECVD.

Effect of Ambient Atmosphere on Abnormal Degradation Behavior in Metal-Oxide Thin-Film Transistor under Positive Gate-Bias and Temperature Stress

Effect of Ambient Atmosphere on Abnormal Degradation Behavior in Metal-Oxide Thin-Film Transistor under Positive Gate-Bias and Temperature Stress

Effect of Ambient Atmosphere on Abnormal Degradation Behavior in Metal-Oxide Thin-Film Transistor under Positive Gate-Bias and Temperature Stress

Proceedings of the International Display Workshops Volume 26 (IDW '19),Effect of Ambient Atmosphere on Abnormal Degradation Behavior in Metal-Oxide Thin-Film Transistor under Positive Gate-Bias and Temperature Stress

An Ultra‐Flexible Solution‐Processed Metal‐Oxide/Carbon Nanotube Complementary Circuit Amplifier with Highly Reliable Electrical and Mechanical Stability

AbstractHere, high‐performance flexible complementary metal‐oxide–semiconductor (CMOS) amplifiers with extremely stable electro‐mechanical characteristics by employing low‐temperature solution‐processed amorphous indium–gallium–zinc oxide (a‐IGZO) and single‐walled carbon nanotube (SWCNT) thin film transistors (TFTs) is demonstrated. The photochemical‐activated combustion sol–gel a‐IGZO and SWCNT TFTs show average saturation mobility of 6.82 and 0.51 cm2 V−1 s−1, respectively. Based on the devices, a‐IGZO/SWCNT‐based CMOS amplifiers are implemented on ultrathin and flexible substrates (thickness of ≈3 µm), exhibiting small‐signal gain and unity‐gain bandwidth of up to 25 dB and 25 kHz, respectively, with highly reliable characteristics from 1000 bending stress (radius of 125 µm) and positive gate bias stress conditions (for up to 3 h). The underlying mechanisms of the CMOS performance combined with large output impedance of the SWCNT load are investigated in detail via various circuit implementations and automatic integrated circuit modeling Spice simulation and comprehensive electrical analysis. To ensure the viability of the extremely stable electromechanical properties of the flexible amplifier, a numerical analysis is carried out based on finite‐element methods with an integrated circuit emphasis to find the best match of the CMOS architecture and optimized structural integrity, verifying highly reliable and scalable skin‐like electronics.

An Efficient Analog Compact NBTI Model for Stress and Recovery Based on Activation Energy Maps

Despite considerable research efforts, efficient and accurate analog bias temperature instability (BTI) stress and recovery models are still urgently needed to evaluate aging in circuit simulators. We present a model for arbitrary analog BTI stress based on distributed first-order reactions to model the time dynamics responsible for the threshold voltage shift of BTI. We use a single activation energy map, which includes the voltage and temperature dependence of stress and recovery. To validate the model, we present the calculation of the threshold voltage shift after arbitrary gate bias stress with high accuracy, industry-compatible measurement effort, and stress time-independent computational effort and introduce a model suitable for circuit simulations.

Amorphous Tin Oxide Applied to Solution Processed Thin-Film Transistors.

The limited choice of materials for large area electronics limits the expansion of applications. Polycrystalline silicon (poly-Si) and indium gallium zinc oxide (IGZO) lead to thin-film transistors (TFTs) with high field-effect mobilities (>10 cm2/Vs) and high current ON/OFF ratios (IOn/IOff > ~107). But they both require vacuum processing that needs high investments and maintenance costs. Also, IGZO is prone to the scarcity and price of Ga and In. Other oxide semiconductors require the use of at least two cations (commonly chosen among Ga, Sn, Zn, and In) in order to obtain the amorphous phase. To solve these problems, we demonstrated an amorphous oxide material made using one earth-abundant metal: amorphous tin oxide (a-SnOx). Through XPS, AFM, optical analysis, and Hall effect, we determined that a-SnOx is a transparent n-type oxide semiconductor, where the SnO2 phase is predominant over the SnO phase. Used as the active material in TFTs having a bottom-gate, top-contact structure, a high field-effect mobility of ~100 cm2/Vs and an IOn/IOff ratio of ~108 were achieved. The stability under 1 h of negative positive gate bias stress revealed a Vth shift smaller than 1 V.

Effect of annealing of NbLaO dielectric on the electrical properties of ZnO thin-film transistor

ZnO thin-film transistors (ZnO TFTs) with high-k NbLaO as a gate dielectric were fabricated on an indium tin oxide (ITO)-coated glass substrate. The NbLaO film was prepared by the sputtering method at room temperature and then annealed in N2 at 200, 300, and 400 °C. The effect of annealing temperature on the quality of NbLaO and ZnO films, especially on the electrical properties and the bias-stress stability of the ZnO TFT, was investigated. The AFM images reveal that the NbLaO film annealed at 300 °C exhibits a relatively smooth surface morphology with a root mean square roughness of 0.31 nm. AFM and x-ray diffraction measurements confirmed that the grain size of ZnO thin films slightly decreases with the increase of the annealing temperature. Except the mobility of slightly less than that of the device annealed 200 °C, the other electrical properties (off-state current, on/off current ratio, and subthreshold slope) of the ZnO TFT annealed at 300 °C are better than those of the samples annealed at 200 and 400 °C and show excellent gate-bias stress stability, which is due to a combination effect of a smoother interface, a denser structure, and the absence of indium doping in the NbLaO gate dielectric, thus resulting in a lower interfacial trap density.

Improving Charge Trapping/Detrapping Characteristics of Amorphous In-Ga-ZnO Thin-Film-Transistors Using Microwave Irradiation.

We investigated the effect of post-deposition annealing (PDA) on the gate-bias-stress-induced charge trapping/detrapping phenomenon in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). To evaluate device reliability, we used the microwave irradiation (MWI), rapid thermal annealing (RTA), and conventional thermal annealing (CTA) methods for PDA of the TFTs and compared the resulting device performances. Fabricated devices were measured in the dark and under light illumination under positive and negative gate-bias-temperature stress (PBTS and NBTS, respectively). Because microwave energy was transferred directly to the substrate in a short time of 2 min in the MWI device, defects were removed more effectively. The obtained results indicated that the threshold voltage (Vth) shift of the MWI-treated a-IGZO TFT with different temperatures and gate bias stresses in the dark and under light illumination was the smallest and the most reliable. Further, comparisons of the Vth recovery characteristics in the dark and under light illumination indicated that charge detrapping behaviors were enhanced under the latter condition. Furthermore, the average effective energy barrier based on Arrhenius plots was extracted. Therefore, the MWI method is considered promising for fabricating next-generation displays on various substrates.

Effect of Oxygen Content on Current Stress-Induced Instability in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors.

The effect of oxygen content on current-stress-induced instability was investigated in bottom-gate amorphous InGaZnO (a-IGZO) thin-film transistors. The observed positive threshold voltage shift (ΔVT) was dominated by electron trapping in the gate insulator (GI), whereas it was compensated by donor creation in a-IGZO active regions when both current flows and a high lateral electric field were present. Stress-induced ΔVT increased with increasing oxygen content irrespective of the type of stress because oxygen content influenced GI quality, i.e., higher density of GI electron traps, as well as typical direct current (DC) performance like threshold voltage, mobility, and subthreshold swing. It was also found that self-heating became another important mechanism, especially when the vertical electric field and channel current were the same, independent of the oxygen content. The increased ΔVT with oxygen content under positive gate bias stress, positive gate and drain bias stress, and target current stress was consistently explained by considering a combination of the density of GI electron traps, electric field relaxation, and self-heating-assisted electron trapping.

Asymmetric Bipolar Injection in a Schottky-Metal/${p}$ -GaN/AlGaN/GaN Device Under Forward Bias

In this letter, we investigated the electroluminescence (EL) spectra and photovoltage spectrum of a Schottky-metal/p-GaN/AlGaN/GaN diode with a semitransparent anode electrode. By analyzing the bias-dependence of the EL spectra of the diode as well as the gate stress bias-/time-dependences of the threshold voltage shift of a p-GaN gate HEMT, the electron/hole injection sequence, electron trapping, hole-assisted de-trapping, and optical pumping processes in the p-GaN gate region are identified. The band diagrams of the Schottky-metal/p-GaN/AlGaN/GaN heterostructure under different forward bias voltages are proposed.

Effects of electrode materials on the device performances and instabilities in amorphous InGaZnO thin film transistors

The effects of electrode materials on the device performances and instabilities in amorphous InGaZnO thin film transistors (a-IGZO TFTs) have been investigated. The dependences of the source and drain resistance (RSD) and the effective channel length (Leff) on the gate biases were explained by the accumulation layer under the gate overlap (LGOV) which was formed due to the oxygen out diffusion from the channel layer. The RSD with electrode materials is determined by not only workfunction (ΦM) but the electrical property of the metal oxide formation. From the threshold voltage shifts with different electrode materials under positive gate bias stress (PBS), the more device degradation could occur when the more electrons are accumulated in LGOV.

(Invited) Design of SiO2/4H-SiC Formation Process with H2O Annealing to Improve MOSFET Performance

4H-SiC has attractive properties for power devices of high voltage applications, however, the performance of MOSFETs is often severely limited by the poor SiO2/SiC interface quality. One of the common techniques to passivate the interface defects is the nitrogen introduction by NO annealing [1] while introduction of wide variety of impurity elements have also been studied [2]. It has been pointed out that SiC MOS characteristics are significantly different between dry-oxidized and wet-oxidized interfaces, and wet-oxidation of SiC often results in a dramatic reduction of interface defect density [3]. To consider the possible reason of the benefit of oxidation by H2O, it should be noticed that the remained carbon at the interface as the thermal oxidation byproduct causes various kinds of interface defects formation. We found that H2O-oxidation does not leave CO-related defect structures near the interface [4]. At the same time H2O-oxidation results in the formation of less-strained SiO2 at the interface than O2-oxidation, which was clarified from the difference of the Si-O-Si vibration mode frequencies in FTIR spectra [3]. Since the formation of near-interface oxide traps of electrons with long time constants is one of the serious causes of the poor MOSFET channel properties, such improvement of near-interface structure would be an advantage of H2O-oxidation. Based on these considerations, we have demonstrated the benefit of the post-oxidation annealing in H2O (H2O-POA) after a simple dry-oxidation, as the way to improve the performance of NMOSFETs formed on 4H-SiC (0001). In this study the H2O-POA ambient was produced by bubbling of O2 or N2 flowing gas through hot water kept at ~97oC to have H2O vapor pressure of ~0.9 atm. It should be noted that this process effectively works with only < 1nm additional growth of oxide at the interface during H2O-annealing [5]. The peak channel mobility ~ 50 cm2/Vs was observed for the channel of ~ 5×1015 cm-3 doping concentration, or that ~35 cm2/Vs for the channel of ~1.3×1016 cm-3 doping concentration, which were higher values than the typical results of conventional NO-passivation processes. We also investigated the combined passivation process of the NO annealing and the low-temperature H2O-annealing on 4H-SiC (0001), to take the advantages of both the nitrogen passivation and the interface structural modification by H2O-oxidation [6]. After the growth of ~30 nm-thick SiO2 layer in dry-O2, the annealing in NO:N2 =1:2 ambient at 1150oC (NO-POA) and the additional annealing in 0.9 atm-H2O ambient at 800oC (H2O post nitridation annealing; H2O-PNA) were sequentially conducted. From XPS analysis on SiC surface after removal of oxides by HF etching, it was found that most of the surface-terminating nitrogen atoms still remained at the interface after a short-time H2O-PNA to cause the growth of limited amount of SiO2 around a few angstroms. The interface state density (Dit) of SiO2/SiC MOS interface was minimized by such short-time H2O-PNA, while an excess time of PNA resulted in rather increase of Dit probably because a part of the surface-terminating nitrogen atoms was removed by H2O-oxidation. A significant improvement of NMOSFET mobility was also successfully demonstrated for the cases of short-time H2O-PNA. Finally the effects of oxygen partial pressure (pO2) in H2O-annealing ambient were studied for the case of H2O-PNA. The impact of pO2 in the ambient on channel mobility was not significant as long as the amount of additional SiO2 growth during H2O-PNA was limited to around a few angstroms. However, a significant difference was observed when positive gate bias stress was applied to the stack. When ~+3 MV/cm constant voltage stress was applied, increase of flatband voltage shift was clearly observed for the samples annealed with pO2 in PNA ambient above ~0.1 atm, which is suggesting deterioration of SiO2 bulk film quality. In contrast, such deterioration was efficiently suppressed when we employed H2O-PNA ambient without any intentional introduction of O2, probably because O2 in H2O-ambient has a role to assist an additional unwanted reaction to form oxide traps in SiO2 bulk layer. These results indicates that the oxide quality on SiC would be quite sensitive to pO2 when the stack was annealed in H2O-ambient.

Self-Aligned Top-Gate Amorphous InGaZnO TFTs With Plasma Enhanced Chemical Vapor Deposited Sub-10 nm SiO2 Gate Dielectric for Low-Voltage Applications

In this letter, self-aligned top-gate (SATG) amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) with an 8.62-nm SiO2 gate dielectric grown by conventional plasma enhanced chemical vapor deposition (PECVD) at 300 °C are fabricated. The results show that the ultrathin PECVD SiO2 film has excellent dielectric properties, such as a low leakage current density of 10−8 A/cm2 at 2 MV/cm, a high breakdown electric field of 9.3 MV/cm, and an almost independent capacitance of bias frequency. The fabricated SATG a-IGZO TFTs with the ultrathin SiO2 gate dielectric exhibit high electrical performances, with major parameters, including a low gate leakage current of 10−13 A, a small subthreshold swing value of 124 mV/decade, a decent field-effect mobility of 10.13 cm2/ $\text{V}\cdot \text{s}$ , and a high ON/OFF current ratio up to 108. Furthermore, the TFTs also show a good electrical stability under positive and negative gate bias stresses.

Improvement of the Bias Stress Stability in 2D MoS2 and WS2 Transistors with a TiO2 Interfacial Layer.

The fermi-level pinning phenomenon, which occurs at the metal–semiconductor interface, not only obstructs the achievement of high-performance field effect transistors (FETs) but also results in poor long-term stability. This paper reports on the improvement in gate-bias stress stability in two-dimensional (2D) transition metal dichalcogenide (TMD) FETs with a titanium dioxide (TiO2) interfacial layer inserted between the 2D TMDs (MoS2 or WS2) and metal electrodes. Compared to the control MoS2, the device without the TiO2 layer, the TiO2 interfacial layer deposited on 2D TMDs could lead to more effective carrier modulation by simply changing the contact metal, thereby improving the performance of the Schottky-barrier-modulated FET device. The TiO2 layer could also suppress the Fermi-level pinning phenomenon usually fixed to the metal–semiconductor interface, resulting in an improvement in transistor performance. Especially, the introduction of the TiO2 layer contributed to achieving stable device performance. Threshold voltage variation of MoS2 and WS2 FETs with the TiO2 interfacial layer was ~2 V and ~3.6 V, respectively. The theoretical result of the density function theory validated that mid-gap energy states created within the bandgap of 2D MoS2 can cause a doping effect. The simple approach of introducing a thin interfacial oxide layer offers a promising way toward the implementation of high-performance 2D TMD-based logic circuits.

Highly stable flexible organic field-effect transistors with Parylene-C gate dielectrics on a flexible substrate

Abstract Poly(chloro-p-xylene), or Parylene-C, is a polymeric insulating material that has good physical and chemical properties, such as a high dielectric strength, a pin-free surface, and good mechanical/chemical stability, but is difficult to apply to top-contact-structured OFETs since its hydrophobic and very rough surfaces hinder the growth of organic semiconductor crystals and promote the formation of interface traps. Herein, we applied a blend of PS and TIPS-PEN dissolved in 1,2,3,4 tetrahydronaphthalene to overcome these limitations of Parylene-C. To confirm the influence of this system, we analyzed the morphologies of crystals grown on Parylene-C surfaces modified by various organic and polymer materials, including methacryloxypropyltrimethoxysilane, hexamethyldisilazane, and dimethylchlorosilane-terminated polystyrene. Our investigation showed the ability of the PS:TIPS-PEN blend system to be used to overcome the above-described limitations of Parylene-C, and to manufacture top-contact OFETs displaying stable operation under gate-bias stress. Notably, we applied Parylene-C and this blend system in practical flexible OFETs that displayed highly stable properties.