Gate Bias Stress Research Articles

산화물 박막 소자의 단기 열화 특성 분석 및 예측식 모델링

Gate bias stress can change the threshold voltage of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT). Especially, short-term degradation of threshold voltage should be compensated since it causes motion artifacts in the display. Therefore, a new short-term degradation model was proposed based on the stretched-exponential model. Moreover, the accuracy of the proposed model was confirmed by calculating the coefficient of determination between the measured data and the fitted data.

High Mobility IZTO Thin-Film Transistors Based on Spinel Phase Formation at Low Temperature through a Catalytic Chemical Reaction.

In this paper, In0.22 Znδ Sn0.78- δ O1.89- δ (δ = 0.55) films with a single spinel phase are successfully grown at the low temperature of 300 °C through careful cation composition design and a catalytic chemical reaction. Thin-film transistors (TFTs) with amorphous In0 .22 Znδ Sn0.78- δ O1.89- δ (δ = 0.55) channel layers have a reasonable mobility of 41.0 cm2 V-1 s-1 due to the synergic intercalation of In and Sn ions. In contrast, TFTs with polycrystalline spinel In0 .22 Znδ Sn0.78- δ O1.89- δ (δ = 0.55) channel layers, achieved through a metal-induced crystallization at 300 °C, exhibit a remarkably high field-effect mobility of ≈83.2 cm2 V-1 s-1 and excellent stability against external gate bias stress, which is attributed to the uniform formation of the highly ordered spinel phase. The relationships between cation composition, microstructure, and performance for the In2 O3 -ZnO-SnO2 ternary component system are investigated rigorously to attain in-depth understanding of the roles of various crystalline phases, including spinel Zn2- y Sn1- y In2 y O4 (y = 0.45), bixbyite In2-2 x Znx Inx O4 (x = 0.4), rutile SnO2 , and a homologous compound of compound (ZnO)k (In2 O3 ) (k = 5). This work concludes that the cubic spinel phase of Zn2- y Sn1- y In2 y O4 (y = 0.45) film is a strong contender as a substitute for semiconducting polysilicon as a backplane channel ingredient for mobile active-matrix organic light-emitting diode displays.

Effect of Gate Bias Stress on the Electrical Characteristics of Ferroelectric Oxide Thin-Film Transistors with Poly(Vinylidenefluoride-Trifluoroethylene).

We investigated the effect of gate bias stress (GBS) on the electrical characteristics of ferroelectric oxide thin-film transistors (FeOxTFTs) with poly(vinylidenefluoride-trifluoroethylene). Generally, conventional oxide thin-film transistors (OxTFTs) with dielectric gate insulators exhibit a small negative shift under negative gate bias stress (NBS) and a large positive shift under positive gate bias stress (PBS) in transfer characteristic curves. In contrast, the FeOxTFTs show a small positive shift and a large negative shift under NBS and PBS, respectively. It was confirmed that sufficient changes in the electrical characteristics are obtained by 10 min NBS and PBS. The changed electrical characteristics such as threshold voltage shift, memory on- and memory off-current were maintained for more than 168 h after NBS and 24 h after PBS. It is deduced that, since the dipole alignment of the ferroelectric layer is maximized during GBS, these changes in electrical properties are caused by the remnant dipole moments still being retained during the gate sweep. The memory on- and memory off-current are controlled by GBS and the best on/off current ratio at 107 was obtained after NBS. By repeatedly alternating NBS and PBS, the electrical characteristics were reversibly changed. Our results provide the scientific and technological basis for the development of stability and performance optimization of FeOxTFTs.

Abnormal Degradation Behaviors Under Negative Bias Stress in Flexible p-Channel Low-Temperature Polycrystalline Silicon Thin-Film Transistors After Laser Lift-Off Process

This work investigates the abnormal phenomena that are observed in electrical characteristics under negative bias stress (NBS) in flexible p-channel low-temperature polycrystalline silicon thin-film transistors (p-channel LTPS TFTs) after TFTs being lifted off from a rigid substrate. During the lift-off process, mechanical strain accumulates in the buffer layer due to the unilateral force, thus resulting in the generation of defects in the buffer layer. Therefore, abnormal degradation behaviors in electrical characteristics of the lifted-off TFTs were observed during negative gate bias stress. A study on physical mechanisms is introduced to describe such abnormal phenomena, and it is confirmed that defects are produced in the buffer layer when the LTPS TFTs are lifted off. In addition, different device dimensions were discussed to support our proposed model. The findings in this work are supported by the discussion of electrical characteristics, trap state extraction, and COMSOL simulation.

Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs

In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from -0.85 V to -0.74 V after applying a high gate bias stress at 150 °C for 10-2 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device's reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.

Performance enhancement of solution-processed amorphous WZTO TFT with HAO gate dielectric via power ultrasound technology

In this paper, power ultrasound technology (PUT) is employed to prepare the high-k hafnium-aluminum oxide (HAO) dielectric and thin film transistor (TFT). The continuous propagation of high-intensity ultrasonic waves in the metal oxide precursor solution can improve the dissolution efficiency of the solute and speed up the formation of the HAO precursor solution. The prepared HAO films have a smooth surface roughness of 0.36 nm and high optical transmittance of 85 %. Moreover, HAO films obtain excellent electrical properties with a relative permittivity of 15.9 and a leakage current density of 9.1 × 10−8 A/cm2 at 2 MV/cm as well. Finally, we successfully fabricate TFT with HAO dielectric using PUT, these TFTs exhibit switch characteristics with field effect mobility of 18.7 cm2v−1s−1, threshold voltage (Vth) of −0.47 V, and Vth shift of 0.35 V under positive gate bias stress. The results show that the PUT is a promising method that can remarkably decrease the preparation time of the precursor solution and improve the TFT performance.

Improvement in current drivability and stability in nanoscale vertical channel thin-film transistors via band-gap engineering in In–Ga–Zn–O bilayer channel configuration

Vertical channel thin film transistors (VTFTs) have been expected to be exploited as one of the promising three-dimensional devices demanding a higher integration density owing to their structural advantages such as small device footprints. However, the VTFTs have suffered from the back-channel effects induced by the pattering process of vertical sidewalls, which critically deteriorate the device reliability. Therefore, to reduce the detrimental back-channel effects has been one of the most urgent issues for enhancing the device performance of VTFTs. Here we show a novel strategy to introduce an In–Ga–Zn–O (IGZO) bilayer channel configuration, which was prepared by atomic-layer deposition (ALD), in terms of structural and electrical passivation against the back-channel effects. Two-dimensional electron gas was effectively employed for improving the operational reliability of the VTFTs by inducing strong confinement of conduction electrons at heterojunction interfaces. The IGZO bilayer channel structure was composed of 3 nm-thick In-rich prompt (In/Ga = 4.1) and 12 nm-thick prime (In/Ga = 0.7) layers. The VTFTs using bilayer IGZO channel showed high on/off ratio (4.8 × 109), low SS value (180 mV dec−1), and high current drivability (13.6 μA μm−1). Interestingly, the strategic employment of bilayer channel configurations has secured excellent device operational stability representing the immunity against the bias-dependent hysteretic drain current and the threshold voltage instability of the fabricated VTFTs. Moreover, the threshold voltage shifts of the VTFTs could be suppressed from +5.3 to +2.6 V under a gate bias stress of +3 MV cm−1 for 104 s at 60 °C, when the single layer channel was replaced with the bilayer channel. As a result, ALD IGZO bilayer configuration could be suggested as a useful strategy to improve the device characteristics and operational reliability of VTFTs.

Microwave-Irradiated Metal-Oxide Thin-Film Transistors With Recessed Gate Structure and Their Applications in Logic Circuits

The effects of a recessed gate structure on the device performance of sol-gel-based metal-oxide thin-film transistors (oxide-TFTs) consisting of aluminum oxide dielectric and indium-gallium-zinc oxide semiconducting films fabricated through effective microwave irradiation are investigated, as compared with elevated and non-patterned gate structures. Low-voltage operating oxide-TFTs with an optimized recessed gate structure exhibited improved device performance including OFF-state current of approximately <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{11}}$ </tex-math></inline-formula> A and field-effect mobility of 3.4 cm2/V-s in the linear regime, compared with those with elevated (~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{9}}$ </tex-math></inline-formula> A and 1.9 cm2/V-s) and non-patterned (~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{10}}$ </tex-math></inline-formula> A and 2.8 cm2/V-s) gate structures. Furthermore, the charge transport mechanism responsible for improved device performance and operational stability against prolonged positive and negative gate bias stresses in the oxide-TFTs with the recessed gate structure is investigated through activation energy and velocity distribution that are determined from direct-current and time-domain non-quasi-static transient analyses, respectively. Finally, enhancement-load-type nMOS inverters operating at 5 V are developed for logic circuits, which exhibit a relatively high dc gain of 32.2 in the recessed gate structure, compared with that of 17.1 and 27.1 in the elevated and the non-patterned gate structures, respectively.

Suppression of Kink in the Output Characteristics of AlInN/GaN High Electron Mobility Transistors by Post-Gate Metallization Annealing

In this paper, we report the effect of post-gate metallization annealing on the performance of GaN-based High Electron Mobility Transistors (HEMTs). The performances of HEMTs annealed at 200 °C (HEMT1) and at 400 °C (HEMT2) for 5 minutes in N2 ambient are compared. While there is a kink in the output characteristics of HEMT1, there is no such kink in the output characteristics of HEMT2. The kink is attributed to impact ionization in the GaN channel. Surface and interface traps of HEMT1 increase the peak electric field at the drain side gate edge and cause impact ionization. The post-gate metallization annealing at a higher temperature reduces the surface and interface traps, which reduces the peak electric field in HEMT2 and suppresses impact ionization. This is substantiated by TCAD simulations. Threshold voltage instability on the application of negative gate bias stress was also examined for these devices. A positive shift in threshold voltage was observed in HEMT1 on the application of negative gate bias stress, whereas the corresponding shift was negative in HEMT2, indicating the presence of two different types of traps in HEMT1 and HEMT2.

Low‐Voltage, High‐Performance, Indium‐Tin‐Zinc‐Oxide Thin‐Film Transistors Based on Dual‐Channel and Anodic‐Oxide

AbstractOxide semiconductor thin‐film transistors (TFTs) with low‐voltage operation, excellent device performance, and bias stability are highly desirable for portable and wearable electronics. Here, the development of low‐voltage indium‐tin‐zinc‐oxide (ITZO) TFTs with excellent device performance and bias stability based on a dual‐channel layer and an anodic‐oxide dielectric layer are reported. An ultra‐thin anodic AlxOy film as a gate dielectric layer is prepared using an anodization process. The dual‐channel layer consists of an oxygen‐uncompensated channel layer and an oxygen‐compensated capping layer. It is confirmed that the dual‐channel structure is effective for enhancing device performance and bias stability in comparison with the single‐channel structure. As a result, the dual‐channel ITZO TFT gated with anodic AlxOy exhibits an effective saturation mobility of 12.56 cm2 Vs−1, a threshold voltage of 0.28 V, a subthreshold swing of 76 mV dec−1, a low‐voltage operation of 1 V, and good operational stability (threshold voltage shift (ΔVTH) &lt; −0.03 V under a negative gate bias stress and ΔVTH &lt; 0.15 under positive gate bias stress of 3600 s). The work shows that the ITZO TFTs, based on a dual‐channel layer and an anodic‐oxide gate dielectric layer, have great potential for low‐power, portable, and wearable electronics.

Effect of Back-Channel Surface on Reliability of Solution-Processed In0.51Ga0.15Zn0.34O Thin-Film Transistors with Thin Active Layer.

We have investigated the degradation mechanism of solution-processed indium-gallium-zinc-oxide (IGZO) thin-film transistors. The threshold voltage shift (ΔVth) followed a linear function under negative gate bias stress (NBS), while it showed a stretched-exponential behavior under positive gate bias stress. The slope of ΔVth for stress time was rarely changed with variations below 0.3 mV/s. The thickness of the fabricated IGZO layer (In0.51Ga0.15Zn0.34O) was approximately 10 nm. The Debye length (LD) was larger than IGZO thickness (tIGZO) due to the fully depleted active layer under NBS. Therefore, the degradation phenomenon under NBS was related to the adsorption at back-channel surface. The back-channel surface could be affected by the gate bias under NBS, and the molecules adsorbed at the IGZO layer were positively charged and induced extra electrons by NBS. We verified that the number of positively charged adsorbates had a proportional relationship with the ΔVth based on the two-dimensional technology computer-aided design (TCAD) simulation. Furthermore, we investigated the degradation phenomenon with the ΔVth equation regarding the adsorbates, and the result confirmed that the adsorption process could cause the linear ΔVth. We experimentally confirmed the effect of back-channel surface by comparing the ΔVth between different atmospheric conditions and LD. Consequently, the reaction at the back-channel surface should be considered to develop the metal-oxide semiconductor devices.

High Performance of InGaZnO TFTs Using HfxAlyOz Nanolaminates as Gate Insulators Prepared by ALD

In this study, HfxAlyOz nanolaminate, single-layer Al2O3, and HfO2 gate insulators were fabricated by atomic layer deposition (ALD) to successfully integrate the InGaZnO (IGZO) thin-film transistors (TFTs). Compared with single-layer HfO2-based TFTs, the HfxAlyOz-based IGZO TFTs showed a larger field-effect mobility of 10.31 cm2/Vs and a smaller subthreshold swing of 0.12 V/decade. Moreover, it showed a smaller threshold voltage shift of 0.5 V than that of HfO2-based TFTs under gate-bias stress at +5 V for 900 s due to the smooth surface. Moreover, the high dielectric HfxAlyOz nanolaminate had a larger equivalent SiO2 thinness than that of Al2O3 gate insulators, which are beneficial in applications of high-resolution display. Thus, the high mobility and high stability TFTs could be regarded as good candidates for active-matrix flat panel displays.

Enhanced Electrical and Mechanical Performance of InSnZnO TFTs With Multifunctional Laminated Organic Passivation Layer

To realize high-performance and stable electrical characteristics for ZnO-based thin-film transistors (TFTs) under various environments, we propose InSnZnO (ITZO) TFTs with multifunctional laminated organic (MLO) passivation layers (PVLs). The MLO PVLs were constructed from self-assembled monolayers (SAMs) and an ultraviolet (UV) light absorber-modified polydimethylsiloxane (PDMS) layer. The SAMs can passivate the ITZO surface and suppress the chemical reaction during the spin-coating process, and the modified PDMS layer can block UV light. The MLO-treated ITZO TFTs exhibited a high-performance and robust stability with high mobility (~21.18 cm2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> V−1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> s−1), a considerable ON– OFF current ratio (~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.65\times10$ </tex-math></inline-formula> 9), and a steep subthreshold slope (~100 mV/dec). The shift of the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\textit V}_{{\mathrm {th}}}$ </tex-math></inline-formula> ) under gate bias stress and UV light illumination stress was investigated for the devices with different PVLs. The ITZO TFTs with MLO PVLs showed improved stability under positive gate bias stress (PBS), positive gate bias illumination stress (PBIS), and negative gate bias illumination stress (NBIS) compared to untreated and SAM-treated ITZO TFTs. Furthermore, the MLO-treated ITZO TFTs achieved a weak response to 365-nm UV light and showed superb stability with the negligible change of electrical performance, even after a 1-h water soaking test and a 100-day storing test. In addition, the MLO PVL exhibited high flexibility without signs of cracking even after 10 000 bending cycles and was proven suitable for fabricating flexible oxide TFTs.

Effect of Humidity on Properties of Aqueous-Processed Tb-Doped Indium Oxide Thin-Film Transistors

Aqueous route is readily for fabricating oxide thin-film transistors (TFTs), but the relative humidity (RH) impacts evolution of oxide thin films. Herein, the effect of RH on the electronic performance and bias stability of aqueous-processed Tb-doped indium oxide (Tb:In2O3) TFTs is investigated. The mobility is sensitive to RH. By tuning the RH for desirable thickness and density of the obtained Tb:In2O3 films, the TFTs present optimized mobility of 13.0 cm2/Vs, with high ON/OFF ratio of 108. Notably, low threshold voltage shift of −0.35 V and 0.42 V under negative and positive gate bias stress are simultaneously obtained with a fabricating RH of 40%. Moreover, dry ambience (RH <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\le23$ </tex-math></inline-formula> %) affords to abundant nanopores and defects, resulting in inferior performance and stability of the aqueous-processed oxide TFTs. And high humid ambience easily ruins the uniform of precursor films. This work indicates the strategy to fabricate highly stable oxide TFTs with high performance.

Rational design of oxide heterostructure InGaZnO/TiO2 for high-performance thin-film transistors

In this study, hetero-structured and self-passivated oxide thin film transistors (TFTs) were fabricated, wherein the channel comprised a N2O plasma (a-IGZO:N2O) treated a-IGZO front layer and TiO2 ultra-thin back layer. A high field-effect mobility (μFE) of 40.5 cm2/Vs and small sub-threshold swing (SS) of 250 mV/decade upon a SiO2/Si substrate were achieved using a rational design. Moreover, small threshold voltage shifts (ΔVth) of 0.5 (−0.7) and 0.8 (−0.9) V under gate bias and light illumination stress tests were obtained. Using Si3N4/HfO2 gate dielectrics, μFE and SS were enhanced to 53.6 cm2/Vs and 75 mV/decade, respectively. Experimental observations indicate that the electrons transfer from TiO2 to a-IGZO:N2O layer resulted in the accumulation of free carriers near a-IGZO:N2O/TiO2 interfaces. Additionally, an appropriate N2O treatment reduced the oxygen-related defects and bulk/interface trap density, while controlling the carrier density in the bilayer a-IGZO:N2O/TiO2 TFTs. Furthermore, the ultra-thin TiO2 layer acted as a surface passivation layer that reduced the leakage current and protected the channel from ambient influences. The proposed high-performance hetero-structured a-IGZO:N2O/TiO2 TFTs with superior stability are expected to provide a new and effective approach to obtaining high-performance metal oxide TFTs for application in thin film electronics.

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

The negative gate bias stress (NBS) reliability of n-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a distinct defective grain boundary (GB) in the channel is investigated. Results show that conventional NBS degradation with negative shift of the transfer curves is absent. The on-state current is decreased, but the subthreshold characteristics are not affected. The gate bias dependence of the drain leakage current at V ds of 5.0 V is suppressed, whereas the drain leakage current at V ds of 0.1 V exhibits obvious gate bias dependence. As confirmed via TCAD simulation, the corresponding mechanisms are proposed to be trap state generation in the GB region, positive-charge local formation in the gate oxide near the source and drain, and trap state introduction in the gate oxide.

37.3: Self‐Aligned Top‐Gate Amorphous ZnSnO Thin‐Film Transistor with Thermal‐Stable Al Reaction‐Doped Source/Drain

This work develops self‐aligned top‐gate (SATG) amorphous ZnSnO (a‐ZTO) thin‐film transistor (TFT) with thermal‐stable low‐resistance source/drain regions using Al reaction method. Compared with Ar plasma treatment, Al reaction doped a‐ZTO films exhibit higher carrier concentration, lower resistance and better thermal stability in oxygen ambient. The fabricated SATG a‐ZTO TFT with Al reaction doped source/drain thus shows excellent electrical performance, such as low channel width normalized source/drain resistance of 7.1 Ω cm, high mobility of 15.7 cm2/Vs. Moreover, good electrical stabilities under high‐temperature oxygen ambient or gate bias stresses are also obtained in Al reaction treated devices.

Impact of the Low Temperature Ohmic Contact Process on DC and Forward Gate Bias Stress Operation of GaN HEMT Devices

In AlGaN/GaN high electron mobility transistors (HEMTs), high temperature processes (such as ohmic annealing with >800°C value) could deform the crystal structure and induce trap states within the bulk and surface. Expanded defect densities cause crucial problems, such as threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula> ) instability, current collapse, and high leakages. In this work, a low temperature ohmic contact process (630°C, 10 minutes) is adopted with recess etch, and contact resistances <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; 0.1\Omega ~\cdot $ </tex-math></inline-formula> mm with low sheet resistances are achieved. The positive impact of this low thermal budget process on surface morphology, DC operation, long-term stability, and forward gate bias stress of the device is studied.

Improved Stability With Atomic-Layer-Deposited Encapsulation on Atomic-Layer In2O3 Transistors by Reliability Characterization

Ultrathin In2O3 and other recently explored low-thermal-budget ultrathin oxide semiconductors have shown great promise for back-end-of-line (BEOL)-compatible logic layers and monolithic 3-D (M3-D) integration. However, the long-term stability and reliability of these defect-rich atomically thin channels have not been intensively explored yet. Here, we present a study of the long-term reliability of transistors with 1.2-nm-thick atomic-layer-deposited (ALD)-grown In2O3 channels by room-temperature positive bias instability (PBI) and negative bias instability (NBI) experiments. The observed behavior can be largely explained by a trap neutrality level (TNL) model. A route to reduce the parameter drift has been developed using encapsulation in sequence with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> engineering by an O2 plasma treatment. After treatment, the magnitude of long-term <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> shift is reduced for both positive and negative gate bias stresses, and for negative bias stress, other transistor parameters are stabilized as well. In all cases, the subthreshold swing (SS) does not change over time, suggesting that stress-induced interface defects form far below the conduction band, if at all.

Improvement in Short-Channel Effects of the Thin-Film Transistors Using Atomic-Layer Deposited In–Ga–Sn–O Channels With Various Channel Compositions

In–Ga–Sn–O (IGTO) thin-film transistors (TFTs) were fabricated with channel lengths from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3 \mu \text{m}$ </tex-math></inline-formula> to 500 nm to investigate the short-channel effects (SCEs), in which IGTO channel compositions were modulated during the atomic-layer deposition. The SCEs appearing in the IGTO TFTs were found to be manifested by increasing the In/Ga ratio of IGTO channel, showing typical channel composition dependence. Alternatively, small values of the channel-length reduction and contact resistance could be obtained to be 50 nm and 0.52 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{k}\Omega $ </tex-math></inline-formula> , respectively, for the device using the IGTO channel with an In/Ga ratio of 1.7. Threshold voltage shifts of the IGTO TFT were estimated to be only +0.03 and +1.22 V under negative and positive gate-bias stress for 104 s, respectively, even with a channel length as short as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1 \mu \text{m}$ </tex-math></inline-formula> .