Gate Bias Stress Research Articles

Abnormal hysteresis formation in hump region after positive gate bias stress in low-temperature poly-silicon thin film transistors

Degradation in low-temperature polycrystalline-silicon thin-film transistors after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (SS) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in SS values which appears in the hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI.

Excellent Uniformity and Reliability Top‐Gate Self‐Aligned IGZO TFTs with Cu Electrode

A top‐gate self‐aligned oxide amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistor (TFT) was examind for active matrix organic light‐emitting diode (AMOLED) display. The device exhibited robust device performance, such as excellent threshold voltage uniformity, high mobility, and good gate bias stress stabilities. Furthermore, remarkable short channel characteristics were achieved

Effect of Simplified-Single-Step Microwave Annealing in O2 Ambient for High Performance Solution-Processed In–Ga–Zn–O Thin Film Transistors

In this study, we propose a simplified-single-step microwave annealing (S₃-MWA) technique in an O₂ ambient, which is a low thermal budget heat treatment method, for the application in solutionprocessed amorphous indium-gallium-zinc oxide (a-IGZO) thin films. For the application of solutionprocessed a-IGZO films in electronic devices, a multi-step post deposition annealing (PDA) process, which involves baking at low temperatures to vaporize the solvent, and high temperature conventional thermal annealing to remove defects in the film, is essential. To simplify the multi-step PDA process, we studied the possibility of reducing the thermal process temperature and time by replacing it with a single-step PDA process using microwave equipment. The electrical properties were compared to investigate the effect of the annealing method and ambient on solution-processed a-IGZO thin film transistors (TFTs). As a result, the S₃-MWA-processed a-IGZO TFTs were found to exhibit superior electrical characteristics in comparison with the conventional PDA-processed devices. It was found that the O₂ ambient process not only shortened the annealing time of S₃-MWA but also improved the electrical properties. Furthermore, the S₃-MWA was superior to the conventional PDA in the evaluation of device reliability under a gate bias stress test. The S₃-MWA process in the O₂ ambient was also responsible for improving the reliability of solution-processed a-IGZO TFTs. Therefore, we confirmed that the proposed S₃-MWA in the O₂ ambient is a more effective and promising technique than conventional PDA for the low thermal budget treatment of solution-processed a-IGZO TFTs.

Significant improvement of spray pyrolyzed ZnO thin film by precursor optimization for high mobility thin film transistors

Metal-oxide thin-film transistors (TFT) fabricated by spray pyrolysis are of increasing interest because of its simple process and scalability. A bottleneck issue is to get a bubble-free and dense material. We studied the effect of ammonium acetate (AA) addition in the oxide precursor solution on the performance of spray-coated ZnO TFTs. AA acts as a stabilizer, which increases the solubility of the solution and enhances the film quality by reducing the defects. With AA addition in ZnO precursor, the films are coffee ring free with high mass density and better grain orientation. The ZnO TFT with AA exhibit a remarkable improvement of its device performance such as saturation mobility increasing from 5.12 to 41.53 cm2V−1s−1, the subthreshold swing decreasing from 340 to 162 mV/dec and on/off current ratio increasing from ~105 to 108. Additionally, the TFTs show excellent stability with a low threshold voltage shift of 0.1 V under gate bias stress. Therefore, the addition of AA is a promising approach to achieve high-performance ZnO TFTs for low-cost manufacturing of displays.

Characterization and analysis of low-temperature time-to-failure behavior in forward-biased Schottky-type p-GaN gate HEMTs

The low-temperature gate reliability of Schottky-type p-GaN gate AlGaN/GaN heterojunction field-effect transistors under forward gate voltage stress is investigated. Both temperature-accelerated and voltage-accelerated time-dependent gate breakdown stress experiments are performed. The p-GaN gate exhibits a shorter time-to-failure at a lower temperature. It is found that the time-to-failure at “use conditions” predicted by acceleration tests at high gate bias stress could be overestimated at low temperatures. Such a discrepancy stems from the distinct dominant gate leakage mechanisms at high/low gate bias stress conditions. The dominant physical mechanism of the low-temperature gate leakage current is identified to be Poole–Frenkel emission at low gate bias and Fowler–Nordheim tunneling at high bias. From the physical model, a more accurate lifetime projection can be obtained for given use conditions.

Tunable Stability of All-Inkjet-Printed Double-Gate Carbon Nanotube Thin Film Transistors

In this letter, we improved the stability of all-inkjet-printed carbon nanotube thin film transistors (CNT TFTs) by employing a double gate (DG) structure under an optimal bias condition. In the single-gate structure, the positive threshold voltage ( $\text{V}_{\text {TH}}$ ) shift under 10 V positive gate bias stress (PGBS) was significantly reduced with poly(4-vinylphenol) passivation. However, after 100 s, the on-current level was decreased, and a large negative $\text{V}_{\text {TH}}$ shift was observed. We adopted DG CNT TFTs for a further improvement. When −3 V was applied to the top gate, the DG CNT TFTs not only exhibited a much lower $\text{V}_{\text {TH}}$ shift but also showed a stabilized on-current level. When an appropriate bias is applied to the top gate, charge trapping is induced at the top gate interface and it might balance between the positive and negative shifts. As a result, the overall stress effect is reduced. The p-type only inverter adopting a DG CNT TFT showed improved stability under −3 V of top gate bias. Our experimental result shows that DG structure is a promising candidate for various CNT circuit designs.

Reliability Characterization of Gallium Nitride MIS-HEMT Based Cascode Devices for Power Electronic Applications

We present a detailed study of dynamic switching instability and static reliability of a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High-Electron-Mobility-Transistor (MIS-HEMT) based cascode switch under off-state (negative bias) Gate bias stress (VGS, OFF). We have investigated drain channel current (IDS, Max) collapse/degradation and turn-on and rise-time (tR) delay, on-state resistance (RDS-ON) and maximum transconductance (Gm, max) degradation and threshold voltage (VTH) shift for pulsed and prolonged off-state gate bias stress VGS, OFF. We have found that as stress voltage magnitude and stress duration increases, similarly IDS, Max and RDS-ON degradation, VTH shift and turn-on/rise time (tR) delay, and Gm, max degradation increases. In a pulsed off-state VGS, OFF stress experiment, the device instabilities and degradation with electron trapping effects are studied through two regimes of stress voltages. Under low stress, VTH shift, IDS collapse, RDS-ON degradation has very minimal changes, which is a result of a recoverable surface state trapping effect. For high-stress voltages, there is an increased and permanent VTH shift and high IDS, Max and RDS-ON degradation in pulsed VGS, Stress and increased rise-time and turn-on delay. In addition to this, a positive VTH shift and Gm, max degradation were observed in prolonged stress experiments for selected high-stress voltages, which is consistent with interface state generation. These findings provide a path to understand the failure mechanisms under room temperature and also to accelerate the developments of emerging GaN cascode technologies.

(Invited) Considerations on H2o-Annealing Effects on SiO2/4H-SiC Mos Interface Structures to Improve MOSFET Perormances

4H-SiC has attractive properties for power devices of high voltage applications, however, the performance of MOSFETs is often severely limited by the SiO2/SiC interface quality. Although the most common way to passivate the interface defects is the nitrogen introduction through NO annealing [1], it is noteworthy that SiC MOS characteristics are often significantly improved only by wet-oxidizing processes compared to the ones of dry-oxidizied interface [2]. In this paper we discuss the essential differences between the dry-oxidation and wet-oxidation of SiC, especially focusing on the oxidation reaction mechanisms and the interface physical structures.The remained carbon at SiC MOS interface as the thermal oxidation byproduct causes various kinds of interface defects formation. We found that H2O-oxidation does not leave CO-related defect structures near the interface. Moreover H2O-oxidation results in the formation of less-strained SiO2 at the interface than O2-oxidation, which was clarified from the difference of the Si-O-Si vibration mode frequencies in FTIR spectra [3]. Since the formation of near-interface oxide traps of electrons with long time constants is one of the serious causes of the poor MOSFET channel properties, such improvement of near-interface oxide structures would be an advantage of H2O-oxidation. The significant quality difference may be attributable to the essential differences of the interface reactions. The thermodynamics suggest that SiO generation is easier for SiC-O2 system (dry oxidation) than SiC-H2O system (wet oxidation) where SiO+CO generation is not preferred to SiO2+CO generation even at high temperatures, as long as a certain partial pressure of H2O was kept supplied. Based on these considerations, we have demonstrated the benefit of the post-oxidation annealing in H2O (H2O-POA) after a simple dry-oxidation, as the way to improve the performance of NMOSFETs formed on 4H-SiC (0001) [4]. In this study the H2O-POA ambient was produced by bubbling of O2 or N2 flowing gas through a temperature-controlled hot water. It should be noted that this process effectively works with only < 1nm additional growth of oxide at the interface during H2O-annealing to demonstrate a comparative or higher channel mobility than the typical results of conventional NO-passivation processes.We also examined the effects of similar processes on PMOSFET, since Dit near valence band edge was found to be reduced by our H2O-POA processes significantly. One of the typical drawbacks of the conventional NO treatment is to introduce hole trapping sites [1] probably in near-interface oxide. In contrast, we found that the H2O-POA processes can reduce Dit while avoiding the formation of hole traps. We fabricated MOS capacitors on p-type 4H-SiC substrate with H2O-POA to examine the negative gate bias stress effects on Vfb. As a result, Vfb stability was significantly better for H2O-POA than NO-annealed one, as long as H2O-POA process was conducted in H2O+N2 ambient (w/o intentional introduction of O2). In contrast, when we introduce some O2 into H2O-POA ambient, the Vfb stability was significantly deteriorated which would be consistent with what has been often reported for wet or pyrogenic oxidized SiC MOS interface [2]. These results clearly indicate that control of oxygen partial pressure is crucial to suppress the defect formation in near-interface oxide by SiC wet oxidation processes.In conclusion, we have clarified the essential differences between O2-oxidized SiC interface and H2O-oxidized one, and systematically investigated the impacts of H2O-annealing to grow an ultrathin interface layer from the view point of NMOSFET channel mobility enhancement. Such process is also effective for PMOSFET channel property improvement. The O2-content in H2O-annealing ambient was found to be a crucial factor to suppress the oxide trap formation by the annealing.

Mobility Improvement of Amorphous Indium-gallium-zinc Oxide Thin Film Transistor by Roll-to-roll Compatible Plasma Treatment

For the mobility enhancement of amorphous indium-gallium-zinc oxide thin film transistor (a-IGZO TFT), Ar plasma treatment was proposed at room temperature under air as an economic and continuous process. Through the suggested method, the field effect mobility (μFE) improves significantly from 1.69 cm²/V·s to 4.20 cm²/V·s. The increase of oxygen vacancy (VO) and decrease of metal-oxide bonding are observed in the plasma treated device by X-ray photoelectron spectroscopy (XPS) analysis. The increased VO is thought to enhance the carrier concentration and mobility. Some of VO, however, will be an inactive and deep state in the forbidden energy gap of IGZO and deteriorate the electrical stability. To avoid this side effect, the selective Ar plasma treatment was also adapted on source/drain (S/D) contact region and threshold voltage shift under the constant positive gate bias stress was measured to decrease from 6.2 V to 4.8 V, which is similar with the untreated device of 4.4 V. In the contract region plasma device, the μFE improves also by 39.6 % to 2.35 cm²/V·s mainly due to the reduction of S/D contact resistance extracted by the transmission line method (TLM).

Fluoroelastomer encapsulation for enhanced reliability of solution-processed carbon nanotube thin-film transistors

Single-walled carbon nanotube (SWCNT) has attracted considerable attention as a promising semiconducting material due to its high field-effect mobility, high current-carrying capability, and superior mechanical durability. However, SWCNT-based thin-film transistors (SWCNT-TFTs) generally show insufficient electrical reliability in terms of the drain-current hysteresis and threshold voltage shift under the bias stress. To facilitate the great advantages of SWCNT in commercial electronic devices, strategies are required for enhancing the electrical reliability of SWCNT-TFTs without compromising their mechanical flexibility. In this work, we demonstrate solution-processed, hysteresis-free, and bias-stable SWCNT-TFTs encapsulated with elastomeric poly(vinylidene fluoride-co-hexafluoropropylene) (e-PVDF-HFP) using a lamination method. The dipolar nature of e-PVDF-HFP suppresses the charge trapping, resulting in elimination of hysteresis as well as enhancement of field-effect mobility and subthreshold slope. The bias instability under the negative gate bias stress is also alleviated because the hydrophobic encapsulation layer can exclude physisorbed water/oxygen molecules on the hydrophilic surface. Besides, our solvent-free lamination method effectively prevents the potential damages of the active and electrode layers from the use of the solvents. The proposed encapsulation method with laminating the e-PVDF-HFP film can provide a possibility for realization of wearable applications based on highly reliable solution-processed SWCNT-TFT.

Experimental evaluation of interface states during time-dependent dielectric breakdown of GaN-based MIS-HEMTs with LPCVD-SiNx gate dielectric**Project supported by the National Key Research and Development Program of China (Grant No. 2017YFB0402800), the Key Research and Development Program of Guangdong Province, China (Grant Nos. 2019B010128002 and 2020B010173001), the National Natural Science Foundation of China (Grant Nos. U1601210 and 61904207), the Natural Science

We experimentally evaluated the interface state density of GaN MIS-HEMTs during time-dependent dielectric breakdown (TDDB). Under a high forward gate bias stress, newly increased traps generate both at the SiNx/AlGaN interface and the SiNx bulk, resulting in the voltage shift and the increase of the voltage hysteresis. When prolonging the stress duration, the defects density generated in the SiNx dielectric becomes dominating, which drastically increases the gate leakage current and causes the catastrophic failure. After recovery by UV light illumination, the negative shift in threshold voltage (compared with the fresh one) confirms the accumulation of positive charge at the SiNx/AlGaN interface and/or in SiNx bulk, which is possibly ascribed to the broken bonds after long-term stress. These results experimentally confirm the role of defects in the TDDB of GaN-based MIS-HEMTs.

Effects of hydrogen plasma treatment on the electrical performances and reliability of InGaZnO thin-film transistors

In this work, we have investigated the effects of hydrogen (H) plasma treatment on the electrical performances and reliability of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs). By optimizing the H plasma treatment time, the a-IGZO TFT with H plasma treatment time of 1 min exhibits excellent electrical performances and reliability, such as high field-effect mobility (μFE) of 26.5 cm2/V s and small threshold voltage shifts (ΔVth) value of 2.5 V and −2.3 V under positive gate bias stress (PBS) and negative gate bias stress (NBS) measurements without any passivation layers. The increased performance relies that the H plasma treatment not only could increase the carrier concentration (Ne) but also reduce the surface defects of channel layer and interface trap density of a-IGZO TFTs. The X-ray photo-electron spectroscopy measurement reveals that the H treatment passivated the oxygen vacancy (VO) defects and formed center-bonded complex states (HO or VO-H) in the a-IGZO films, which act as a shallow donor in a-IGZO films. Therefore, the high performances and excellent reliability of a-IGZO TFTs is suggesting that H is a very promising treatment for TFTs to be used for flexible thin film electronic applications.

Rare Metal‐Free High‐Performance Zinc–Tin Oxide Thin Film Transistors Using Efficient Energy Conversion of Microwave Annealing

Herein, a rare metal‐free oxide‐based semiconductor channel layer is constructed with excellent electrical properties and stabilities by fabricating zinc–tin oxide (ZTO) thin film transistors (TFTs) using tin (Sn) as the dopant element in ZnO. Furthermore, to improve the performance and stability of ZTO TFTs, microwave annealing (MWA) powered by energy conversion from electromagnetic energy to heat energy rather than heat transfer is conducted as the post‐deposition annealing (PDA) process of the ZTO channel layer. As a result, the electrical performance of ZTO TFTs is improved by MWA despite the much shorter PDA time because of the efficient energy transfer compared with that of furnace‐used thermal annealing (FTA) in conventional furnaces. The ZTO TFTs subjected to MWA exhibit a high on/off current ratio of 1.7 × 107, a high field‐effect mobility of 20.6 cm2 V−1 s−1, a small hysteresis voltage of 0.9 V, and a low interface trap density of 1.8 × 1012 cm−2 eV−1. In addition, the instabilities due to the positive and negative gate bias stresses at various operating temperatures are evaluated, and the results show that the instability of the ZTO TFT is significantly reduced by MWA.

Annealing atmosphere-dependent electrical characteristics and bias stability of N-doped InZnSnO thin film transistors

The dependence of electrical characteristics and gate bias stress stability of N-doped InZnSnO (IZTO:N) thin film transistors (TFTs) on annealing atmosphere was investigated. The annealing process was performed in air, O2 and N2, respectively, after the deposition of IZTO:N thin film by magnetron sputtering. All annealed IZTO:N films are amorphous and show a high transmittance in the visible light range. The N2-annealed TFT has the highest saturation mobility (μSAT) of 39.5 cm2 V−1s−1 and the lowest subthreshold swing (SS) of 0.40 V/decade. The air-annealed TFT shows similar mobility and SS to the N2-annealed TFT while the O2-annealed TFT shows the lowest mobility and the largest SS. We found that annealing atmosphere has impact on the bias stress stability of the TFTs. Bias stress induced threshold voltage shift of the O2-annealed TFTs is reduced compared to that of air-annealed and N2-annealed TFTs due to the decrease in oxygen vacancy.

Severe hump phenomenon induced by increased charge trapping and suppression of electron capture effect in amorphous In-Ga-Zn-O thin-film transistors under unipolar pulsed drain bias with static positive gate bias stress

This paper demonstrates degradation of amorphous indium gallium zinc oxide thin-film transistors under AC current stress (ACS), which is unipolar AC drain bias applied with positive static gate-bias stress. Under ACS, a severe hump occurs in current-voltage curves; the phenomenon causes a large negative shift similar to degradation caused by positive gate-bias stress (PGS) and a large positive shift by DC-current stress (DCS). In a saturation measurement, the degradation caused by factors in source region had the greatest effect on the hump phenomenon; this result confirms that hump characteristics are caused by charge trapping rather than by defect-state generation by impact ionization. The changes of threshold voltage shifts were extracted at two current levels, then analyzed by comparing with the results of PGS, DCS, and synchronized AC gate and drain bias stress. Positive shift in high-current level was larger after ACS (+3.80 V) than after PGS (+3.48 V) because current-caused Joule-heat thermally energized additional electrons to be trapped in front channel region. Negative shift in low-current level was larger after ACS (−2.42 V) than after DCS (−1.32 V). Under DCS, the amount of positively-charged species decreased because of neutralization of oxygen vacancies. The flow of current supports electron to be captured in ionized oxygen vacancies and the amount of negative shift is saturated at specific value (−1.32 V) under DCS. The characteristic time constant of stretched exponential curve-fitting reveals clear saturation tendency.

Achieving High Mobility and Excellent Stability in Amorphous In–Ga–Zn–Sn–O Thin-Film Transistors

This article reports the fabrication of high-performance amorphous indium gallium zinc tin oxide ( ${a}$ -IGZTO) thin-film transistors (TFTs) with superior bias stability. For comparison, amorphous indium gallium zinc oxide ( ${a}$ -IGZO) TFTs were also investigated to clarify the origin of the superior performance of IGZTO TFTs. It was found that the simultaneous heavy loading of In and Sn into the IGZTO system facilitated an effective mass densification, leading to a reduction in tail states and deep states. The fabricated ${a}$ -IGZTO TFTs exhibited a high electron mobility ( $\boldsymbol {\mu }_{\text {FE}}$ ) of 46.7 cm2/Vs, a subthreshold swing (SS) gate of 0.15 V/decade, and an ${I}_{\text {ON/OFF}}$ ratio $> {1} \times {10}^{{8}}$ . Furthermore, greater gate-bias stress stability was observed for the IGZTO TFTs compared with the IGZO TFTs.

Bias stress and humidity exposure of amorphous InGaZnO thin-film transistors with atomic layer deposited Al2O3 passivation using dimethylaluminum hydride at 200 °C

Highly reliable amorphous InGaZnO (a-IGZO) (In:Ga:Zn:O = 2:2:1:7) thin-film transistors (TFTs) were fabricated with 25 nm-thick Al2O3 passivation deposited by atomic layer deposition (ALD) using dimethylaluminum hydride (DMAH). Al2O3 passivation deposited at various temperatures was studied to determine its effect on TFT behavior following gate bias stress and humidity exposure. The Al2O3-passivated a-IGZO TFTs demonstrated an on-off current ratio (Ion/Ioff) of ~108 and linear mobility (µ) of 9 to 13 cm2 V−1 s−1. An optimum ALD temperature of 200 °C was demonstrated to result in Al2O3-passivated a-IGZO TFTs with very small on-voltage shifts of 0.3 V and −2.7 V against positive bias stress and negative bias illumination stress (NBIS) after 10 000 s of stress time. Furthermore, negligible degradation was observed after humidity exposure. The results of x-ray photoelectron spectroscopic analysis of the O 1s spectra showed the highest peak area ratio for metal–oxygen (M–O) bonding and lowest metal–oxygen vacancy (M–Vo) bonding, relating to the least amount of trap sites both in the bulk region of a-IGZO and near the interface of Al2O3/a-IGZO, for the device passivated at 200 °C. It was also found that at a low deposition temperature (⩽100 °C), low-density Al2O3 was formed with high carbon contamination and hydrogen while at a high deposition temperature (⩾300 °C), high hydrogen concentration was also present in high-density Al2O3. The hydrogen incorporation from Al2O3 passivation to a-IGZO channel creates bulk defects and trap sites as well as in the interface of a-IGZO and SiO2 gate insulator. At 200 °C, high quality Al2O3 passivation was achieved with high density and reduced impurities leading to improved device reliability. These results can be applied to long term sustained device operations which are reliable against different stresses.

Verification of microwave annealing ambient effect on sol-gel-processed amorphous In–Ga–Zn–O thin-film transistors and application to inverter circuit

In this study, we conducted microwave annealing (MWA) on amorphous In–Ga–Zn–O (a-IGZO) thin films deposited by the sol-gel method, and then investigated the effects of ambient conditions on the electrical properties and reliability of a-IGZO thin-film transistors (TFTs) and on the optical and chemical properties of a-IGZO thin films. On the other hand, pure N2 ambient-treated TFTs exhibited the poorest transfer and output characteristics, but improved with increasing O2 mixing ratio. In terms of stability, pure O2 ambient-treated a-IGZO TFTs were excellent for both positive and negative gate bias stresses, but deteriorated with increasing N2 mixing ratio. Also, static and dynamic tests of resistor-loaded inverters were carried out. As a result, the pure O2 ambient-treated inverter showed excellent characteristics, while the pure N2 ambient-treated inverter had poor characteristics. Meanwhile, pure O2 ambient MWA has excellent carbon removal ability in sol-gel-processed a-IGZO films, lowering oxygen vacancies and impurities. Besides, it has an effect of increasing energy band gap, improving transmittance, increasing Fermi level and electron concentration, and contributing to improvement of mobility. Therefore, it was verified that MWA in pure O2 ambient is very beneficial to improve the optical and chemical properties of the sol-gel-processed a-IGZO thin film and the electrical properties of TFTs.

The influence of ZnO layer thickness on the performance and electrical bias stress instability in ZnO thin film transistors

Thin Film Transistors (TFTs) are the active elements for future large area electronic applications, in which low cost, low temperature processes and optical transparency are required. Zinc oxide (ZnO) thin film transistors (TFTs) on SiO2/n+-Si substrate are fabricated with the channel thicknesses ranging from 20 nm to 60 nm. It is found that both the performance and gate bias stress related instabilities of the ZnO TFTs fabricated were influenced by the thickness of ZnO active channel layer. The effective mobility was found to improve with increasing ZnO thickness by up to an order in magnitude within the thickness range investigated (20–60 nm). However, thinner films were found to exhibit greater stability in threshold voltage and turn-on voltage shifts with respect to both positive and negative gate bias stress. It was also observed that both the turn on voltage (Von) and the threshold voltage (VT) decrease with increasing channel thickness. Moreover, the variations in subthreshold slope (S) with ZnO thickness as well as variations in VT and Von suggest a possible dependence of trap states in the ZnO on the ZnO thickness. This is further correlated by the dependence of VT and Von instabilities with gate bias stress.

Significant enhancement of the bias stability of Zn-O-N thin-film transistors via Si doping

Si doping was used to significantly improve the bias stability of ZnON thin-film transistors. Si 3 W (~1%) doped ZnON TFTs showed a saturation mobility of 19.70 cm2/Vs along with remarkable improvements in the threshold voltage shift for negative gate bias stress (NBS) within 1.69 V. The effects of Si doping were interpreted by the experimental correlation between device performance and physical analysis, as well as by the theoretical calculation. Si doping induces the reduction of N-related defects by increasing stoichiometric Zn3N2, and decreasing nonstoichiometric ZnxNy. In addition, Si doping reduces the band edge states below the conduction band. According to density functional theory (DFT) calculations, Si, when it substitutes for Zn, acts as a carrier suppressor in the ZnON matrix.