Gate Array Logic Research Articles

Nonvolatile logic gate and full adder based on tri-terminal oxide resistive switching devices

Today's on-chip computing power is constrained by the “memory wall” and “power wall” caused by the Von Neumann bottleneck. As a potential solution, this work has developed nonvolatile logic gates based on field-effect tri-terminal oxide resistive switching memory devices (3T-RRAM). A compact circuit model using a polynomial control source (PCS) is proposed to describe the behavior of the fabricated 3T-RRAM. The 3T-RRAM can be regarded as a nonvolatile transmission gate for constructing nonvolatile logic gates. Additionally, a full adder with input storage functionality has been designed using only eight 3T-RRAMs (four nonvolatile logic gates), and a binarized neural network (BNN) based on 3T-RRAM logic gate arrays has been proposed. This demonstrates the great potential of nonvolatile logic gates in computing-in-memory applications.

Development of All Solid State Nanosecond Pulse Transformer Fault Detection Device Based on Marx Circuit

Abstract a nanosecond pulse generator with a fast leading edge for transformer fault diagnosis is developed. The device is composed of a full solid-state nanosecond pulse generator based on Marx circuit and with a tail cut switch and a field programmable logic gate array (FPGA) device. Among them, the nanosecond pulse source is mainly composed of DC power supply, control circuit and main circuit. The main circuit is a 9-level modular Marx circuit, using MOSFET as the main switch and tail cut switch; The control circuit generates a synchronous trigger pulse signal, which drives the MOSFET to work synchronously after being isolated through the optical fiber. The output nanosecond pulse voltage parameters are adjustable amplitude 0-8kv, pulse width 100˜1000ns, repetition frequency 1hz˜1000hz, rising edge 30ns and falling edge 40ns. The transformer fault diagnosis platform is built, and the transformer off-line and on-line fault diagnosis is carried out, which paves the way for further exploration of transformer fault diagnosis technology.

Modeling and simulation of three-phase IGBT full-bridge inverter circuit based on FPGA

The field of motor drive makes extensive use of electronic power modeling and simulation of three-phase IGBT full-bridge inverter circuits. The accuracy and computational efficiency of these models have a direct impact on the dependability of the motor control system. The majority of earlier research focused solely on static processes of turning on and off in IGBTs, disregarding the transient proesses that occur when three-phase IGBT full-bridge inverter circuits are switched at high frequencies. This has an impact on the circuits' accuracy in real-time simulation. Therefore, this paper proposes and builds a field-programmable logic gate array (FPGA)-based steady-state and transient dual-phase three-phase IGBT full-bridge inverter circuit model for the static and transient characteristics of the insulated gate bipolar transistor (IGBT) element in the circuit. Depending on whether or not the switching states of the six IGBTs in the three-phase IGBT full-bridge inverter circuit are altered, the simulation process is split into steady state and transient phases. In the steady state phase with large step size, the circuit is discretized using the binary L/C approach. In the transient phase, the transient process is divided into several small-step-long time domains. Real-time simulation waveforms are generated by interleaving and combining the multistage fitting method's solution of the circuit's transient waveforms at tiny step lengths with the steady state phase. Finally, in order to demonstrate the accuracy of the circuit model in this work, the simulation results of the two-stage three-phase IGBT full-bridge inverter circuit model based on FPGA are compared with those of the conventional ideal model for waveform comparison and data analysis.

A tunable hybrid metasurface design with integrated diffusion and absorption

AbstractIn this letter, a tunable hybrid metasurface (THMS) with electromagnetic switching characteristics based on the field‐programmable logic gate array (FPGA) is developed, which combines the mechanisms of both phase cancellation and absorption. Compared to other hybrid metasurface, the proposed design possesses two major functions of electromagnetic switching and dynamic tuning. By adjusting the bias voltage of the active components controlled by FPGA module, the in‐band tuning and active switching at different frequency bands of 3.63–5.57, 4.86–10.47, and 9.40–12.36 GHz can be obtained. A physical prototype with the size of 350 mm × 370 mm is fabricated and measured for verification, and the measurement shows that the monostatic radar cross section achieves varying degrees of reduction from 1.66 to 12.04 GHz.

Design of a Power Efficient Model of PWM Generator for Green Communication using High Performance FPGAs

Aim: This paper will focus on promoting the ideas of green communication Background: Pulse Width Modulation (PWM) generator is used to control the power transfer in any communication model. It is one of the most crucial parts of an electrical circuit. Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication Objective: Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication. Methods: In order to make the PWM suitable for GC, we have implemented the design on VIVADO ISE from Xilinx. The power analysis as well as resource utilization are targeted on three different FPGAs. Results: Different IO standards of Stub Series Terminated Logic (SSTL) family are explored at different FPGA’s. Power analysis is deployed on the 7 series FPGAs of 3 different categories i.e., Spartan 7 (channel length = 28 nm), Kintex 7 (channel length = 20 nm) and ultra scale Zynq 7 (channel length = 16 nm). Conclusion: It can be concluded from power analysis that SPARTAN-7 device is the most powerefficient and ZYNQ Ultra scale+utilizes the highest amount of power. However, KINTEX-7 Ultrascale device lies in the middle of both these devices as far as power consumption is concerned. There is a reduction of 43.07% TP consumption for SPARTAN-7 device with SSTL135 IO when equated with ZYNQ Ultra scale+ with SSTL18_I IO. Also, it can be observed from sections 5.1, 5.2 and 5.3 that there is more contribution of DP in TP consumption than SP. Hence the device utilizes additional power when it is in active state than static state. Since PWM generator is an integral part of data and wireless communication, it should require less power for proficient transmission and wellorganized green computing and communication.

Light induced photovoltaic and pyroelectric effects in ferroelectric BaTiO3 film based Schottky interface for self‐powered and flexible multi‐modal logic gates

AbstractOptoelectronic logic gates have emerged as one of the key candidates for the creation of next generation logic devices. However, current optoelectronic logic gates can provide only one or two logic gates, severely limiting their applications. Here we report a self‐powered and mechanically flexible device based on a BaTiO3 ferroelectric film to produce multi‐modal logic gates. By exploiting the photo‐induced photovoltaic and pyroelectric effects of a Schottky junction which is created between BaTiO3 and LaNiO3, the device is able to provide five different optoelectronic logic gates, which can be operated using input lasers of different wavelength (405 or 785 nm). The mode of operation of the logic gate can be switched by controlling the wavelength and intensity of the input laser, where the switching process is both lossless and reversible. A logic gate array was designed to conduct the five logic operations, with 100% accuracy, thereby providing application potential for the Internet of Things, big data, and secure solutions for data processing and transmission.image

A real-time dynamic range expansion approach of multi-channel sampling system

Dynamic range (DR) is one of the most critical factors for evaluating a signal processing system. It is limited by all electronic components that signal passes through in the circuit, including the amplifier, analog-to-digital converter and etc. Based on the signal acquisition structure of synchronous sampling with multiple conditioning channels, this paper proposed a method to expand the DR of the system. The proposed method involves the iterative algorithm to calculate the gain and offset between different channels, the threshold voltage setting principles of channel switching, and the data combination approach. More importantly, it can easily be applied in programmable logic gate array in the real-time system. On the basis of ensuring system sensitivity, the input voltage range is increased by combining data from different channels, thereby the DR of the system is increased. The experimental results in the sampling board of the vibration and audio signal analyzer show that the method we discussed in this article has a significant effect on DR expansion in the sampling system.

An adaptive laser processing method of multilayer heterogeneous materials by monitoring dynamic spectrum at kHz-MHz level

Laser micro/nano processing exhibits significant advantages in manufacturing capability and performance. However, the properties of ablated materials cannot be sensed and identified during processing is an intractable challenge. In particular, multilayer heterogeneous materials often evolve into excessive residues and damages during laser selective removal. In this study, we developed an adaptive laser processing method that includes material interface adaptive and laser power adaptive for selective removal of multilayer heterogeneous materials by monitoring dynamic spectrum at kHz-MHz level. The mechanism of interface sensing and the threshold of laser selective removal of multilayer materials were investigated. Dual-channel parallel detection mode of the blazed grating with the ultrafast photodetector at the kHz-MHz pulse level has been designed and verified for monitoring adjacent layers synchronously. High-speed signals with a pulse width of 30 ns and a repetition frequency of 0–15 MHz were identified by the Field Programmable Logic Gate Array (FPGA), and pulse-level closed-loop feedback was finished. Patterned selective removal on an FR-4 copper clad laminate (CCL) and flexible printed circuit (FPC) was completed. The method exhibited sensitive signal characteristics, accurately sensed the material interface, and provided a clear criterion for identifying the removal process of multilayer materials by quantitative analysis of signal variation, which provides an innovative scheme for laser intelligent manufacturing of multilayer heterogeneous materials.

Electrically Sensitive Plasmonic Photonic Crystals for Dynamic Upconversion Manipulation

AbstractLocal optical field modulation using plasmonic materials or photonic crystals provides a powerful strategy for enhancing upconversion emission of lanthanide‐doped upconversion nanocrystals (UCNPs). However, it is restricted to static UC enhancement and the corresponding dynamic modulation of UC is yet to be reported, limiting its practical applications in information devices. Here, a dynamic UC modulation system is reported through electric stimulation by integrating UCNPs with electrically sensitive WO3−x plasmonic photonic crystals (PPCs). The tunable emission enhancement of UCNPs varying from five to 26 folds is achieved in WO3−x PPCs/UCNPs hybrids through external electric stimulation within +1.6 and −1.6 V. It stems from the reversible control of the photonic bandgaps and localized surface plasmon resonance of WO3−x PPCs, ascribed to the variation of refractive index and oxygen vacancy of WO3−x, induced by the reversible change of atomic ratio of W5+ to W6+ under different applied voltages. Moreover, the electrically triggered information encryption devices are developed, employing a programmable logic gate array based on WO3−x PPCs/UCNPs with the ability to convert information‐encrypted electrical signals into visible patterns. These observations offer a new attempt to manipulate the UC and will simulate the new applications in the display and optical storage devices.

Method of solving single-event upset for heterogeneous dual field programmable logic gate array for infrared remote sensing camera in orbit

On-orbit reconstruction is a hotspot technology in the field of space infrared remote sensing cameras technology. Since the space infrared remote sensing cameras perform detection work under the space radiation environment, the core part of its image processing unit, which is a static random-access memory type field programmable logic gate array (FPGA), is susceptible to the impact of high-energy particles, especially during single-event upset events. The occurrence of point-like granular noise in remote sensing images will affect the normal imaging detection performance of the system, and even lead to abnormal timing of infrared detectors in severe cases, thereby affecting the normal operation of infrared remote sensing cameras. Aiming at the reliability requirements of the normal operation of space infrared remote sensing cameras in the space radiation environment, we propose a modular architecture of heterogeneous dual FPGA for XilinxVirtex-5 series FPGA, which carries out periodic refresh, reconstruction, and uploading of Virtex-5 series FPGA through antifuse FPGA. The antifuse FPGA periodically refreshes and reconstructs the Virtex-5 series FPGA from a one-time programmable read-only memory and injects the program into the program storage NOR flash device, and periodically refreshes and reconstructs the Virtex-5 series FPGA from NOR flash. This method can refresh and reconstruct the space infrared remote sensing camera in orbit. The in-orbit flight data verification shows that this method can effectively solve the impact of single-particle turnover event and improve the reliability of the infrared remote sensing camera in orbit operation.

PID-FUZZY Control System for Autonomous Underwater Vehicles (AUV): Highly Accurate FPGA Implementation

Because of the linear and nonlinear variations in the operating environment, autonomous underwater vehicles (AUVs) are one of the most difficult applications. The complexity of the control algorithm should be less for real-time implementation in a field programable gate array logic (FPGA) device. In this work, a highly accurate FPGA implementation of PID-Fuzzy control strategy is proposed for an AUV operation that is extremely precise. Parameters such as weight, water density, and depth are used to perform highly efficient and accurate control for the proposed system. A type II fuzzy logic controller and accompanying proportional-integral- derivative controller are used to confine pitch and depth boundaries. The proposed design is modeled using SIMULINK software, and Verilog code is generated using hardware description language coder from MATLAB. Xilinx software is used to synthesize the Verilog code for spartan FPGA. The proposed technique improves the accuracy and reduces the response time when compared to the conventional control strategy.

SPAD-Based LiDAR With Real-Time Accuracy Calibration and Laser Power Regulation

This brief reports a light detection and range (LiDAR) imager which incorporates an image sensor based on a single-photon avalanche diode (SPAD) with the resolution of 32 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {\times }$ </tex-math></inline-formula> 32, a VCSEL-based laser emission system with the same resolution as image sensor as well as the pixel spacing, and a field programmable logic gate array (FPGA) used to realize the calibration algorithm and control the working time of the LiDAR imager. A gating high-voltage driver circuit drives the image sensor to reduce background noise interference and realize real-time accuracy calibration for the time-to-digital converter (TDC) with the resolution of 200 ps. The common-cathode driver circuit with the narrow pulse, adaptive frequency and power regulation drives different channels of VCSEL based on the time-division multiplexing method to improve the signal-to-noise ratio and reduce power consumption of the LiDAR imager. The LiDAR imager based on the proposed circuit architecture and calibration algorithm can achieve depth imaging up to 10 m revealing a repeatability error of 10 cm at 10 frames/s.

An FPGA-based trigger system for CSHINE

A trigger system of the general function was designed using the commercial module of CAEN V2495 for heavy-ion nuclear reaction experiments at Fermi energies. The system was applied and verified on the compact spectrometer for heavy IoN experiment (CSHINE). Based on the field-programmable logic gate array technology of the command register access and remote computer control operation, trigger functions can be flexibly configured according to experimental physical goals. Using the trigger system on CSHINE, we conducted a beam experiment at 25 MeV/u $$^{86}\textrm{Kr}+ ^{124}\textrm{Sn}$$ on the Radioactive Ion Beam Line 1 in Lanzhou, China. The online results demonstrated that the trigger system worked normally and correctly. This system can be extended to other experiments as well.

THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs

To address some of the challenges of asynchronous design, we propose a new, decomposable asynchronous logic block architecture based on our TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> programmable threshold cell, and we use it to implement common threshold functions found in asynchronous, null convention logic circuits. At a minimum, programmable gate arrays require a programmable logic cell that can implement a complete set of logic. It is well known that a NAND function forms a complete set of logic, and in null convention logic, the TH12 and TH22 threshold cells are used to form a basic two-input NAND function. The TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell is capable of performing both TH12 and TH22 operations, so it too forms a complete set of logic. In this paper, we present our eight-transistor mask-programmable gate array logic cell, 16-transistor field-programmable gate array logic cell, and new decomposable field-programmable gate array logic block architecture, all based on the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell and suitable for implementing null convention logic asynchronous functions. To minimize the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell area for both TH12 and TH22 modes, we designed a layout with common Euler paths and no diffusion breaks for both modes. The highly compact nature of the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell&#x2013;along with the symmetry of the mask- and field-programmable gate array logic cells&#x2013;made it an ideal candidate for an asynchronous field-programmable logic block structure. This paper is part of an ongoing project, and it only addresses the programmable logic block architecture, not a complete FPGA fabric.

A System-on-Chip Based Hybrid Neuromorphic Compute Node Architecture for Reproducible Hyper-Real-Time Simulations of Spiking Neural Networks.

Despite the great strides neuroscience has made in recent decades, the underlying principles of brain function remain largely unknown. Advancing the field strongly depends on the ability to study large-scale neural networks and perform complex simulations. In this context, simulations in hyper-real-time are of high interest, as they would enable both comprehensive parameter scans and the study of slow processes, such as learning and long-term memory. Not even the fastest supercomputer available today is able to meet the challenge of accurate and reproducible simulation with hyper-real acceleration. The development of novel neuromorphic computer architectures holds out promise, but the high costs and long development cycles for application-specific hardware solutions makes it difficult to keep pace with the rapid developments in neuroscience. However, advances in System-on-Chip (SoC) device technology and tools are now providing interesting new design possibilities for application-specific implementations. Here, we present a novel hybrid software-hardware architecture approach for a neuromorphic compute node intended to work in a multi-node cluster configuration. The node design builds on the Xilinx Zynq-7000 SoC device architecture that combines a powerful programmable logic gate array (FPGA) and a dual-core ARM Cortex-A9 processor extension on a single chip. Our proposed architecture makes use of both and takes advantage of their tight coupling. We show that available SoC device technology can be used to build smaller neuromorphic computing clusters that enable hyper-real-time simulation of networks consisting of tens of thousands of neurons, and are thus capable of meeting the high demands for modeling and simulation in neuroscience.

Four-Channel Buck-Type LED Driver with Automatic Current Sharing and Soft Switching

A buck-type LED driver together with automatic current sharing and high step-down voltage conversion ratio but without complex control is proposed. The proposed LED driver can not only achieve zero voltage switching (ZVS) turn-on by adding only one resonant coupled inductor, which resonates with parasitic capacitors of active switches, but also can obtain lower voltage gain and better conversion efficiency. In this paper, the operating principles and design considerations of the proposed converter are discussed in detail. In addition, the number of LED strings can be extended to more than four channels. Finally, the theoretical analysis and performance of the proposed LED driver are verified by simulations and experiments using a field-programmable logic gate array (FPGA) named EP3C5E144C8N as a circuit control kernel.

FPGA-based multi-channel thermocouple temperature measurement system

Aiming at the high and low temperature test requirements of spacecraft before being sent into space, this paper designs and implements a multi-channel thermocouple temperature measurement system based on FPGA.The system adopts thermocouple as temperature sensor, and ADT7310 is used as thermocouple cold junction temperature compensation, which solves the problem of thermocouple cold junction compensation better.The front end adopts AD7193, a 24-bit analog-to-digital converter with low noise, multi-channel and low power consumption, to amplify and A/D convert the signal at measuring junction of thermocouple.The control core is a field programmable logic gate array FPGA, which can better solve the problem of parallel processing of multi-channel temperature signals. At the same time, it uses the transposition method of the thermocouple standard graduation table, the interpolation look-up table algorithm and the cold junction compensation reverse look-up table algorithm, which is effective The temperature measurement accuracy of each channel is improved.The experimental results show that the system can be connected to 24 K-type or T-type thermocouple sensors, the measurement range can reach -200°C∼220°C (73.15K∼493.15K), and the relative error is less than ±0.3%F.S.

Multiple molecular logic gate arrays in one system of (2-(2'-pyridyl)imidazole)Ru(ii) complexes and trimeric cyclophanes in water.

Shape-switchable cyclophane hosts allow the controlled capture and release of reactive polypyridineRu(ii) complexes in water. This gives rise to a network of host-guest binding, acid-base reactions in ground and excited states, and chemical redox interconversions. In the case of (2-(2'-pyridyl)imidazole)Ru(ii) complexes, several molecular logic gate arrays of varying complexity emerge as a result. Cyclophane-induced 'off-on' switching of luminescence in neutral solution is found to originate from two features of these aromatic hosts: enhancement of radiative decay by the polarizable host and the suppression of nonradiative decay involving deprotonation by reducing the water content within the deep host cavity. These are examples of nanometric coordination chemistry/physics being controlled by inclusion in an open box. The aromatic units of the macrocycle are also responsible for the shape-switching mechanism of wall collapse/erection.

A Large-Range Steering Optical Phased Array Chip and High-Speed Controlling System

The optical phased array (OPA) chip is becoming the core component of all-solid-state lidars. In order to realize the wide-angle range beam scanning and rapid control of OPA-based solid-state lidars, we design and fabricate a 64-channel silicon-based OPA chip based on thermo-optical modulation. In accordance with the optical phase control characteristics of the multichannel thermo-optic OPA chip, we propose a parallel random access memory (RAM) array technique to realize high-speed phase control for the OPA chip and build the hardware system with a field-programmable logic gate array (FPGA). This system is used to test the main performance indicators of the OPA chip and realizes the high-speed scanning control of the wide-angle range of the OPA output beam. The test results show that the OPA chip we designed can achieve fast beam scanning within a large angle range between &#x2212;32.5&#x00B0; and &#x002B;32.5&#x00B0;, and the chip has high working reliability. Combined with the control system we build, it can meet the high-speed radar scanning requirements of all-solid-state lidars. This work lays a good foundation for the subsequential development of our thermo-optical and electrooptic OPA all-solid-state lidar prototypes.

Non-blocking programmable delay line with minimal dead time and tens of picoseconds jitter

We report a non-blocking high-resolution digital delay line based on an asynchronous circuit design. Field-programmable gate array logic primitives were used as a source of delay and optimally arranged using combinatorial optimization. This approach allows for an efficient trade-off of the resolution and a delay range together with a minimized dead time operation. We demonstrate the method by implementing the delay line adjustable from 23ns up to 1635ns with a resolution of 10ps. We present a detailed experimental characterization of the device focusing on thermal instability, timing jitter, and pulse spreading, which represent three main issues of the asynchronous design. We found a linear dependence of the delay on the temperature with the slope of 0.2 ps K-1 per logic primitive. We measured the timing jitter of the delay to be in the range of 7-165ps, linearly increasing over the dynamic range of the delay. We reduced the effect of pulse spreading by introducing pulse shrinking circuits and reached the overall dead time of 4-22.5ns within the dynamic range of the delay. The presented non-blocking delay line finds usage in applications where the dead time minimization is crucial, and tens of picoseconds of excess jitter is acceptable, such as in many advanced photonic networks.