There has been a classic design trade-off between electromagnetic interference (EMI) and power efficiency in switching power circuits historically. This work explores the technical strategies that well balance this trade-off. In particular, an emulated Miller plateau tracking scheme is proposed to identify critical di/dt and dv/dt instants, which are susceptible to load current and power input voltage conditions. An adaptive strength gate driving scheme facilitates low di/dt and high dv/dt switching operation, which leads to the targeted EMI and switching loss optimization. A switching power converter IC prototype was implemented in a 0.35-μm high-voltage (HV) Bipolar-CMOS-DMOS (BCD) process. Operating at 10 MHz, the converter regulates an output at 5 V with 6-W power range, accommodating a wide input supply voltage ranging from 5 to 40 V. It achieves above 70% efficiency over 95.8% of the full power range, with a peak efficiency of 81.4% at 1.25 W. With the proposed strategies, the peak EMI of the converter is reduced by 19.23 dBμV in Band B (<;30 MHz) and 9 dBμV in Band C/D (>30 MHz), with only 2.44% efficiency penalty.
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