Avoiding Si MOSFET Avalanche and Achieving Zero-Voltage Switching for Cascode GaN Devices

Abstract

The cascode structure is widely used for high-voltage normally-on wide-bandgap devices. However, the interaction between the high-voltage normally-on device and the low-voltage normally-off Si MOSFET may induce undesired features. This paper analyzes the voltage distribution principle during the turn-off transition as well as the zero-voltage-switching (ZVS) principle during the turn-on transition for cascode GaN devices. The capacitance mismatch between high-voltage normally-on GaN switch and the low-voltage Si MOSFET causes the Si MOSFET to avalanche, and internal high-voltage GaN switch lose the ZVS condition. This issue must be solved in consideration of both power loss and reliability. A simple and effective solution is proposed by adding an extra capacitor to compensate the capacitance mismatch, thereby avoiding Si MOSFET avalanche and achieving true ZVS for cascode GaN devices. The benefits and small penalty of this solution are analyzed in detail. The theoretical analysis is validated by experiments, which are implemented based on a 600-V cascode GaN device. The experiment shows that the proposed method improves the 600-V cascode GaN devices performance significantly in high-frequency applications. The analysis and proposed solution are also applicable to other cascode devices.