GaN Power Research Articles

Internally Harmonic Matched Compact GaN Power Amplifier with 78.5% PAE for 2.45 GHz Wireless Power Transfer Systems

In this paper, a high-efficiency compact power amplifier is designed and fabricated with a 0.25 μm GaN high electron mobility transistor (HEMT) to meet the demands of a high integration level and high efficiency for microwave wireless power transfer (WPT) systems. The proposed power amplifier (PA) is implemented using an internally matched method to achieve a compact circuit size. The output second and third harmonic impedances can be optimized through output matching circuits, eliminating the need for additional harmonic matching networks. This approach simplifies the design of matching circuits and reduces the circuit size. Furthermore, the input third harmonic has been controled for improving the efficiency of DC-to-RF conversion. The total size of the proposed PA is 13.4 × 13.5 mm2. The test results obtained from the continuous wave (CW) testing indicate that the output power of the power amplifier at 2.45 GHz reaches 43.75 dBm. Additionally, the large-signal gain is measured at 15.75 dB, and the power-added efficiency (PAE) achieves a value of 78.5%.

Optimizing Forward Drop and Reverse Leakage Trade‐Off in AlGaN/GaN Lateral Diode with Schottky‐Metal‐Insulator‐Semiconductor Cascode Anode

Herein, AlGaN/GaN lateral diode with the Schottky‐Metal‐Insulator‐Semiconductor (MIS) cascode anode (CALD) to optimize forward voltage drop (VF) and reverse leakage current (ILEAK) trade‐off is proposed. In the CALD device, a normally‐on Ni/HfO2/AlGaN MIS‐controlled channel as well as a lateral Ni/GaN Schottky contact are cascoded at the anode. The designed normally‐on MIS‐controlled channel has high electron concentration at forward bias and prevents high electric‐field at reverse bias, which ensure both low VF and low ILEAK. Meanwhile, the Ni/GaN Schottky contact with a high Schottky barrier height further suppresses the ILEAK. As a result, the fabricated CALD demonstrates an optimized VF–ILEAK trade‐off relationship, including a low VF of 1.6 V and a low ILEAK of 5.2 × 10−8 A mm−1 (at reverse voltage of 400 V), together with a high breakdown voltage (BV) >700 V. These high performances suggest that the CALD can be a promising candidate for GaN power diode applications requiring a better VF–ILEAK trade‐off.

Recovery of drain-induced threshold voltage shift by positive gate bias in GaN power HEMTs with p-GaN gate

We demonstrate that exposure to positive gate bias can favor a fast recovery of the threshold voltage variation induced by off-state stress, in p-GaN gate high electron mobility transistors. Two process splits were investigated, having different Schottky barriers at the metal/p-GaN junction. Results indicate that: (a) drain stress may result in significant threshold voltage increase; (b) devices with sufficiently high gate leakage current show an immediate recovery after gate turn-on, resulting in stable operation in actual applications. The contribution of leakage current is demonstrated, based on recovery experiments at different voltages and for the same rate of hole injection from the gate.

A Novel Isolation Approach for GaN-Based Power Integrated Devices.

This paper introduces a novel technology for the monolithic integration of GaN-based vertical and lateral devices. This approach is groundbreaking as it facilitates the drive of high-power GaN vertical switching devices through lateral GaN HEMTs with minimal losses and enhanced stability. A significant challenge in this technology is ensuring electrical isolation between the two types of devices. We propose a new isolation method designed to prevent any degradation of the lateral transistor's performance. Specifically, high voltage applied to the drain of the vertical GaN power FinFET can adversely affect the lateral GaN HEMT's performance, leading to a shift in the threshold voltage and potentially compromising device stability and driver performance. To address this issue, we introduce a highly doped n+ GaN layer positioned between the epitaxial layers of the two devices. This approach is validated using the TCAD-Sentaurus simulator, demonstrating that the n+ GaN layer effectively blocks the vertical electric field and prevents any depletion or enhancement of the 2D electron gas (2DEG) in the lateral GaN HEMT. To our knowledge, this represents the first publication of such an innovative isolation strategy between vertical and lateral GaN devices.

A broadband high-efficiency quasi class E internally-matched GaN power amplifier with a compact band-pass output matching structure

A broadband high-efficiency quasi class E internally-matched GaN power amplifier with a compact band-pass output matching structure

High Power GaN Doubler with High Duty Cycle Pulse Based on Local Non-Reflection Design

High Power GaN Doubler with High Duty Cycle Pulse Based on Local Non-Reflection Design

Investigation of the Trapping and Detrapping Behavior by the On-State Resistance at Low Off-State Drain Bias in Schottky p-GaN Gate HEMTs

GaN power HEMTs enable the design of power electronic systems with highest efficiencies and reduced size. Despite strong advancements in device reliability, charge carrier trapping is still an important challenge. The applied methodology allows to characterize defects that cause the dynamic RDS,on in GaN power devices at product level with flexibility in duty cycle, number of pulses and mission profile. A pronounced trapping is observed for lateral GaN-on-Si HEMTs with Schottky p-GaN gate structure at low drain bias and long off-state pulses (> 100 ms). The effect is investigated by fast determination of the on-state resistance RDS,on under different trap capturing conditions: a) different drain bias b) off-state time and number of cycles c) variation of temperature. The trapping and detrapping effects are characterized and the activation energy is extracted from time constants. An elevated on-state resistance was present for up to 3 hours. The threshold voltage modification due to high drain bias does explain the significant RDS,on increase.

A CMOS-Compatible Process for ≥3 kV GaN Power HEMTs on 6-inch Sapphire Using In Situ SiN as the Gate Dielectric.

The application of GaN HEMTs on silicon substrates in high-voltage environments is significantly limited due to their complex buffer layer structure and the difficulty in controlling wafer warpage. In this work, we successfully fabricated GaN power HEMTs on 6-inch sapphire substrates using a CMOS-compatible process. A 1.5 µm thin GaN buffer layer with excellent uniformity and a 20 nm in situ SiN gate dielectric ensured uniformly distributed VTH and RON across the entire 6-inch wafer. The fabricated devices with an LGD of 30 µm and WG of 36 mm exhibited an RON of 18.06 Ω·mm and an off-state breakdown voltage of over 3 kV. The electrical mapping visualizes the high uniformity of RON and VTH distributed across the whole 6-inch wafer, which is of great significance in promoting the applications of GaN power HEMTs for medium-voltage power electronics in the future.

Investigation of Saturated RON on GaN Power HEMTs by a Re-Configurable Continuous Switching Platform

Investigation of Saturated <i>R</i>ON on GaN Power HEMTs by a Re-Configurable Continuous Switching Platform

Minimizing Output Capacitance Loss in GaN Power HEMT

Minimizing Output Capacitance Loss in GaN Power HEMT

In-Chip Microfluidic Cooling Integrated on GaN Power IC Reaching High Power Density of 78 kW/l

In-Chip Microfluidic Cooling Integrated on GaN Power IC Reaching High Power Density of 78 kW/l

Synthesis of nano-diamond film on GaN surface with low thermal boundary resistance and high thermal conductivity

Joule self-heating is the main obstacle limiting the performance of GaN power devices. A nano-diamond (NCD) film for near-junction heat transfer has been approved as an effective approach to overcome this issue. In the present study, we developed a scheme to deposit a smooth NCD film with high thermal conductivity (TC) over the surface of GaN. First, a 10-nm Si3N4 was deposited as the protective layer of GaN, followed by electrostatic seeding to improve nucleation density and particle distribution uniformity. Second, argon and gradient methane gas were introduced to prepare the NCD film based on nucleation and the growth period. The resulting thickness of the NCD film was 150 nm with a roughness of about 20 nm. The thermal boundary resistance (TBReff) between GaN and NCD film was only 12.8 ± 0.64 m2K/GW, whereas the TC of the NCD film was 200 ± 40 W m−1 K−1, which was similar to the theoretical prediction. Thus, it could be inferred that the high crystallinity of the NCD film contributes to the low TBReff and high TC through the whole NCD layer.

Study on Single Event Effects of Enhanced GaN HEMT Devices under Various Conditions.

GaN HEMT devices are sensitive to the single event effect (SEE) caused by heavy ions, and their reliability affects the safe use of space equipment. In this work, a Ge ion (LET = 37 MeV·cm2/mg) and Bi ion (LET = 98 MeV·cm2/mg) were used to irradiate Cascode GaN power devices by heavy ion accelerator experimental device. The differences of SEE under three conditions: pre-applied electrical stress, different LET values, and gate voltages are studied, and the related damage mechanism is discussed. The experimental results show that the pre-application of electrical stress before radiation leads to an electron de-trapping effect, generating defects within the GaN device. These defects will assist in charge collection so that the drain leakage current of the device will be enhanced. The higher the LET value, the more electron-hole pairs are ionized. Therefore, the charge collected by the drain increases, and the burn-out voltage advances. In the off state, the more negative the gate voltage, the higher the drain voltage of the GaN HEMT device, and the more serious the back-channel effect. This study provides an important theoretical basis for the reliability of GaN power devices in radiation environments.

The role of carbon segregation in the electrical activity of dislocations in carbon doped GaN

Dislocations have been proposed to affect the performance and reliability of GaN power semiconductors by being conductive pathways for leakage current. However, no direct evidence of a link between their electrical behavior and physical nature in carbon-doped semi-insulating GaN buffer layers has been obtained. Therefore, we investigate the electrical activity of dislocations by conductive atomic force microscopy and electron beam induced current to distinguish electrically active dislocations from non-active ones. We investigated six electrically active dislocations and discovered distinct carbon enrichment in the vicinity of all six dislocations, based on cross-sectional scanning transmission electron microscopy using electron energy loss spectrometry. Electrically non-active dislocations, which are the vast majority, sometimes also showed carbon enrichment, however, in only two out of seven cases. Consequently, carbon segregation seems to be a requirement for electrical activity, but a carbon surplus is not sufficient for electrical activity. We also performed first-principles total-energy calculations for mixed type threading dislocations, which validates carbon accumulation in the dislocation vicinity. The electrical and physical characterization results, complemented by density functional theory simulations, support the previously hypothesized existence of a carbon defect band and add new details.

Analyzing false turn-on events with varying gate drive parameters in high voltage GaN devices

In this paper, we address the problem of false turn-on effects in a half-bridge GaN power converter in terms of circuit and device parameters. The model shows that the inherent false turn-on problem is caused by slew rates dvdsdt and dvgsdtduring the switching transients occurring at the turn-on and off phases. A higher slew rate propagates the gate driver voltage to overshoot beyond the threshold voltage causing it to accidentally turn on This study shows that dvdsdt is dependent on the internal device parameters such as gfs (transconductance) and Coss(output capacitance). From the CV characteristics, it is pretty much evident that the internal capacitances Cossand Crss (reverse transfer capacitance) are reduced with higher drain voltage enabling higher slew rates which increases the probability of false turn-on problems. Experimental results at numerous operating points at 400 V with the variation in different gate drive parameters support the analysis.

Current Saturation Behavior in GaN Polarization Superjunction Hybrid Diode

This is the first report on the current saturation behavior observed in the forward characteristics of polarization superjunction (PSJ)‐based hybrid PiN‐Schottky GaN power diodes fabricated on Sapphire. In the current saturation region, most of the applied anode voltage is dropped across the regions immediately adjacent to the edge of the doped P‐GaN region closest to the cathode. This significant potential drop occurs within a short distance, resulting in a high electric field and depletion of electrons, causing the current saturation behavior via velocity saturation in these PSJ hybrid diodes.

Reliability Assessment of 60-GHz GaN Power Amplifier Under High-Level Input RF Stress

Reliability Assessment of 60-GHz GaN Power Amplifier Under High-Level Input RF Stress

SPICE Modelling-Assisted evaluation of dynamic on-resistance characterization in Schottky p-GaN HEMTs amid synchronous buck transient instabilities

This study addresses the critical gap in dynamic on-resistance characterization for GaN HEMTs within the initial unstable state in a non-isolated DC-DC converter, where the output voltage and currents fluctuate and exhibit overshoots or undershoots before stabilizing to their steady-state values, a domain within solar photovoltaic (PV) Maximum Power Point Tracking (MPPT) implementations which is crucial yet insufficiently examined. The authors present a novel multi-pulse test circuit within a synchronous buck converter configuration, complemented by SPICE simulation. This combination allows for the accurate assessment of clamping circuits' performance during transient states, significantly improving the precision of RDS(ON) measurements in unsteady phases. The approach deviates from conventional methods by merging empirical data with simulation insights to validate the efficacy of clamping circuits. The experimental results affirm the methodology's precision, with the highlighted Circuit V showcasing a marginal deviation of 2.32 % from existing benchmarks. This finding substantiates the method's dependability and practicality contributing to the GaN power electronics field. In addition, this research provides a powerful analytical tool for RDS(ON) evaluation, culminating in the design of a test PCB that synergizes with both simulated and empirical evidence, contributing future research in GaN HEMT power converter applications.

Modeling and Suppression of Conducted Interference in Flyback Power Supplies Based on GaN Devices

The application of GaN power devices has significantly increased the power density of flyback power supplies but has also caused severe electromagnetic interference (EMI) issues. To address the challenge of conducted interference in flyback power supplies, a comprehensive analysis of the transmission mechanism of conducted common-mode noise is undertaken. This analysis involves simplifying the equivalent model of conducted interference and leveraging the circuit characteristics of conducted noise to propose a solution for attenuating common-mode noise. Considering the constraints of external compensation capacitors, a balanced winding is further introduced to mitigate the impact of noise. To enhance the efficacy of conducted interference suppression, it is suggested to change the winding structure of the transformer and incorporate a shielding winding. This configuration aims to minimize the generation and propagation of common-mode noise within the transformer. Finally, experimental verification is carried out using a 150 W GaN flyback power supply prototype. The experimental results demonstrate that the proposed method effectively suppresses common-mode noise in the circuit.

Aging Reliability Compact Modeling of Trap Effects in Power GaN HEMTs

Aging Reliability Compact Modeling of Trap Effects in Power GaN HEMTs