GaN Metal Insulator Semiconductor Research Articles

Presence of High Density Positive Fixed Charges at ALD–Al2O3/GaN (cap) Interface for Efficient Recovery of 2‐DEG in Ultrathin‐Barrier AlGaN/GaN Heterostructure

The ultrathin‐barrier (UTB) AlGaN/GaN heterostructure exhibits great promise as a technology for manufacturing high‐performance normally OFF GaN metal–insulator–semiconductor high‐electron‐mobility transistors (MIS–HEMTs) due to its unique gate recess‐free feature. However, a critical challenge in UTB MIS–HEMTs is the recovery of the 2D electron gas in the access region, particularly with regard to achieving low ON resistance. In this study, a new approach is proposed to address this issue by utilizing a low‐thermal‐budget Al2O3 film grown through atomic layer deposition (ALD). By analyzing the capacitance–voltage characteristic and correlating it with the threshold voltage shift versus dielectric thicknesses for SiNx and Al2O3, high density of positive fixed charges (≈2.382 × 1013 cm−2) is confirmed to be induced at the interface between ALD–Al2O3 and GaN (cap), which is also in good agreement with 1D Poisson simulations of energy band diagrams. The positive charges are probably originated from the interface AlAl bonds revealed by X‐Ray photoelectron spectroscopy analysis.

Dynamic RON Degradation Suppression by Gate Field Plate in Partially Recessed AlGaN/GaN Metal–Insulator–Semiconductor High‐Electron‐Mobility Transistors

This study investigates the impact of gate field plate (G‐FP) lengths on the dynamic on‐resistance degradation in partially recessed‐gate D‐mode GaN metal–insulator–semiconductor high‐electron‐mobility transistors (MIS‐HEMTs). Devices with G‐FPs of varying lengths are fabricated, and their electrical characteristics are evaluated. It is found that G‐FPs effectively reduce electron trapping and suppress the dynamic on‐resistance degradation, leading to improved device performance. The study provides design suggestions for enhancing the reliability and stability of AlGaN/GaN‐based MIS‐HEMTs.

Control of Surface Chemistry in Recess Etching toward Normally Off GaN Metal–Insulator–Semiconductor High‐Electron‐Mobility Transistors

Reducing off‐state and gate leakage current is crucial in the development of metal–insulator–semiconductor high‐electron‐mobility transistors (MIS‐HEMTs). This work reports interface engineering in the gate recess region through low‐damage digital etching during the fabrication of normally off GaN MIS‐HEMTs. Conventional plasma etching leads to a reduction of the N/(Al+Ga) ratio, but this value recovers to almost 1 with optimized oxidation condition during digital etching, suggesting a reduction of the Al/Ga dangling bonds based on the proposed technique. GaN MIS‐HEMTs with digital etching exhibits a threshold voltage of 1.0 V at 1 μA mm−1, a high ON/OFF current ratio of 1010, a gate breakdown voltage of 22 V, and a low gate leakage current of 10−8 mA mm−1.

Comparative Study on Schottky Contact Behaviors between Ga- and N-Polar GaN with SiNx Interlayer

We conducted a comparative study on the characterization of Ga-polar and N-polar GaN metal–insulator–semiconductor (MIS) Schottky contact with a SiNx gate dielectric. The correlation between the surface morphology and the current–voltage (I–V) characteristics of the Ga- and N-polar GaN Schottky contact with and without SiNx was established. The insertion of SiNx helps in reducing the reverse leakage current for both structures, even though the leakage is still higher for N-polar GaN, consistent with the Schottky barrier height calculated using X-ray photoelectron spectroscopy. To optimize the electric property of the N-polar device, various substrate misorientation angles were adopted. Among the different misorientation angles of the sapphire substrate, the GaN MIS Schottky barrier diode grown on 1° sapphire shows the lowest reverse leakage current, the smoothest surface morphology, and the best crystalline quality compared to N-polar GaN grown on 0.2° and 2° sapphire substrates. Furthermore, the mechanism of the reverse leakage current of the MIS-type N-polar GaN Schottky contact was investigated by temperature-dependent I–V characterization. FP emissions are thought to be the dominant reverse conduction mechanism for the N-polar GaN MIS diode. This work provides a promising approach towards the optimization of N-polar electronic devices with low levels of leakage and a favorable ideality factor.

Non-equilibrium thermal transport study in steady state GaN MISHEMT channel layer based on electron Monte Carlo and phonon BTE

An electro-thermal coupling simulator for GaN devices based on electron Monte Carlo (e-MC) simulations is established. Taking GaN Metal Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) as example, the non-equilibrium thermal transport processes of self-heating effect in the channel layer are studied. This simulator is mainly coupled by e-MC and the phonon Boltzmann transport equation (pBTE), physical property parameters and electric field parameters are provided by first-principles and Technology Computer Aided Design (TCAD), respectively. We first verify the e-MC program by calculating the electron transport properties of GaN materials, verify the feasibility of the established GaN MISHEMT model by using TCAD and obtained its operating characteristics. Further, the simulator is used to evaluate the non-equilibrium processes inside the channel layer in detail, the results show that there is significant consistency in the peak positions of electric field strength, heat generation and diffusion temperature, the diffusion temperature peak occurs at the secondary peak of heat generation. The frequency distribution of phonon emission under different drain-source bias voltages is revealed by phonon emission spectrum analysis. The strength of the non-equilibrium effect is measured by effective temperature. Increasing the drain-source bias voltage will significantly increase the peak temperature of hotspot and further enhance the non-equilibrium effect. Our study reports an efficient scheme for electro-thermal simulations of GaN MISHEMT, which provides insights for thermal management of GaN-based transistor devices.

Improved breakdown performance in recessed-gate normally off GaN MIS-HEMTs by regrown fishbone trench

This work develops a regrown fishbone trench (RFT) structure in selective area growth (SAG) technique to fabricate recessed-gate normally off GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs). The RFT structure effectively modulates the electric field at high drain and gate biases, thus allowing the device to feature improved off-state and gate breakdown performance with a high positive Vth of 2 V. The simulated carrier concentration and electric field distributions reveal the mechanism of electric field weakening by RFT architecture. Meanwhile, the current collapse phenomenon is significantly suppressed, and the gate voltage swing is also enlarged. The maximum gate drive voltage of 9.2 V for 10-year reliability of RFT GaN MIS-HEMT, together with the improved linearity and block voltage, broadens the applications of SAG devices. Furthermore, the RFT structure also provides an etching-free method for fabricating normally off GaN MIS-HEMTs with multi-dimensional gates.

Effects of ammonia and oxygen plasma treatment on interface traps in AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors

A HfO2/Al2O3/AlN stack deposited in a plasma-enhanced atomic layer deposition system is used as the gate dielectric for GaN metal–insulator–semiconductor structures. Prior to the deposition, in situ remote plasma pretreatments (RPPs) with O2, NH3, and NH3–O2 (in sequence) were carried out. Frequency-dependent capacitance–voltage (C–V) measurements reveal that for all the RPP-treated samples, the interface trap density Dit was significantly reduced compared to the sample without RPP. In particular, the NH3-treated sample exhibits an extremely low Dit of ∼1011 cm−2·eV−1 from EC − 0.31 eV to EC − 0.46 eV. To characterize the interface traps at deeper levels, the transfer pulsed I–V measurement was employed further. In the energy range of EC − ET > 0.54 eV, the interface trap charge density Qit of various samples demonstrates the following order: NH3 RPP < NH3–O2 RPP < O2 RPP < without RPP. By adjusting multiple pulse widths, the Dit derived from the Qit result matches the C–V measurement precisely. Moreover, X-ray photoelectron spectroscopy analysis of the Ga 3d core-level indicates that NH3 RPP facilitates the conversion of Ga2O into GaN at high RF power of 2500 W, whereas O2 RPP mainly oxidizes GaN to relatively stable Ga2O3. Combined with the C–V and pulsed I–V measurements, it is confirmed that a strong positive correlation exists between Ga2O and the interface traps, rather than Ga2O3.

Fabrication and Switching Performance of 8 A–500 V D‐Mode GaN MISHEMTs

In this work, the design, fabrication, static device testing, and double‐pulse switching performance of multi‐finger D‐mode GaN metal–insulator–semiconductor high‐electron‐mobility transistors (MISHEMTs) on silicon are discussed. Utilizing an metal‐organic chemical vapor deposition‐grown GaN high‐electron‐mobility transistors stack with a superlattice buffer, field‐plated devices with a meandering gate geometry and a total gate width of 30 mm are fabricated. Plasma enhanced chemical vapor deposition SiNx is used as the gate dielectric, followed by an optimized bilayer SiNx passivation scheme. Devices with 100 μm gate width have an ON/OFF ratio of ≈108. They are analyzed for dynamic Ron (normalized Ron = 3 at 100 μs) and time‐dependent dielectric breakdown for gate reliability, resulting in a β value of 2.65 from the Weibull plot. Devices with a 30 mm gate width exhibit a maximum ON current of 8 A at zero gate voltage and a three‐terminal breakdown of ≈500 V. The devices are diced, wire‐bonded to a printed circuit board, and a double‐pulsed test is performed for switching transient characterization under clamped inductive load. The OFF‐state and ON‐state energy loss are estimated to be Eon = 14 μJ and EOFF = 27 μJ, respectively, when switched at 5 A, 50 V. In this study, the potential of GaN MISHEMTs with bilayer SiNx passivation for low‐power D‐mode switching applications (5 A, 50 V) is demonstrated.

N-Polar GaN HEMTs in a High-Uniformity 100-mm Wafer Process With 43.6% Power-Added Efficiency and 2 W/mm at 94 GHz

We report the fabrication of N-polar GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) with a power-added efficiency (PAE) of 43.7% from an 8-V supply measured by load pull at 94 GHz. The devices are fabricated on 100-mm SiC substrates and exhibit excellent uniformity, constituting the first report on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$</tex-math> </inline-formula> -band power performance across a 100-mm N-polar GaN sample. Compared with the available efficiency of N-polar GaN on SiC at 94 GHz, the devices presented here demonstrate among the highest PAE performance, while delivering a power density of 2 W/mm, competitive with highly scaled, and previously reported both Ga and N-polar devices using an 8-V power supply.

A numerical modeling of the frequency dependence of the capacitance–voltage and conductance–voltage characteristics of GaN MIS structures

The capacitance–voltage (C–V) and conductance–voltage (G–V) characteristics of GaN metal–insulator–semiconductor (MIS) structures have a frequency dependence due to the capture and emission of electrons by the high density of the interface states. However, the details of how an interface state affects C–V and G–V characteristics is still not well understood. In this paper, we report a numerical modeling method that can simulate the frequency dependent C–V and G–V characteristics of GaN MIS structures.

Bias-Dependent Conduction-Induced Bimodal Weibull Distribution of the Time-Dependent Dielectric Breakdown in GaN MIS-HEMTs

In this article, we investigated the bimodal behavior in the Weibull distribution of time to breakdown during time-dependent dielectric breakdown (TDDB) measurement in GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) with Si3N4 gate insulator. We propose that the gate leakage current is a mixture mechanism of Poole–Frenkel (PF) emission and Fower–Nordheim (FN) tunneling current. The dominant mechanism of devices could shift from PF emission to FN tunneling when the stress bias is above a certain value, which is related to the properties of traps in the gate dielectric. The evolution of the leakage mechanism with stress bias leads to the deviation of the Weibull slope from the original one at low stress bias, where PF emission is the dominant one.

Evaluation of the border traps in LPCVD Si3N4/GaN/AlGaN/GaN MIS structure with long time constant using quasi-static capacitance voltage method

We extract the electric properties of border traps with long time constant in low-pressure chemical vapor deposition (LPCVD) Si3N4/GaN/AlGaN/GaN metal–insulator–semiconductor (MIS) structure using quasi-static capacitance voltage method. The energy and depth distribution of the border traps is calculated based on the analysis of energy band diagram and charging dynamic of border traps in the MIS structures. With this method, it is found that LPCVD Si3N4/GaN/AlGaN/GaN MIS structure have a high density of border traps in the order up to 1021 cm−3 eV−1 located at energy level between E C,GaN − 0.04 eV and E C,GaN − 0.66 eV with distance of 1.0–4.2 nm from the Si3N4/GaN interface. Microstructure analysis suggests that the high density of border traps is possibly correlated to the oxygen content at the Si3N4/GaN interface. Meanwhile, the proposed method is also suitable for MIS or metal-oxide-semiconductor structure on other semiconductors, providing another powerful tool to analysis the physical properties of border traps.

Low trap density of oxygen-rich HfO2/GaN interface for GaN MIS-HEMT applications

The high-k nature of HfO2 makes it a competitive gate oxide for various GaN-based power devices, but the high trap densities at the HfO2/GaN interface have hindered the application. This work was specifically carried out to explore the interface between GaN and ozone-based atomic-layer-deposited HfO2 gate oxide. Furthermore, the GaN surface is preoxidized before gate oxide deposition to prepare an oxygen-rich HfO2/GaN interface. On the preoxidized GaN surface, a sharper HfO2/GaN interface and amorphous HfO2 bulk form during the subsequent deposition, translating to improved electric performance in metal–insulator–semiconductor (MIS) devices. The ozone-based HfO2 shows a high breakdown electric field (∼7 MV/cm) and a high dielectric constant (∼28). Furthermore, the MIS high electron mobility transistors' negligible VTH hysteresis and parallel conductance measurements reflect the ultralow trap densities of the HfO2/GaN interface (&amp;lt;1012 cm−2 eV−1). Therefore, the proposed HfO2 gate oxide scheme offers a promising solution for developing GaN MIS devices.

Implementation of Recessed Gate Normally off GaN Metal–Insulator–Semiconductor High Electron Mobility Transistors by Electrodeless Photoelectrochemical Etching

We demonstrated that electrodeless photoelectrochemical (ELPEC) etching can be used to realize recessed gate normally off GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs). A slower speed etching of 0.36 nm/min has been achieved by the ELPEC etching, and it was easy to control the etching depth at this etching rate. The normally off GaN MISHEMT has been fabricated with a 20 nm atomic layer deposition hafnium oxide (HfO2) gate dielectric after a 55 min ELPEC etching, and low etched surface roughness has been obtained. A threshold voltage shift from −3.6 to 0.5 V has been achieved, performing with normally off properties. A maximum output current of 500 mA/mm and a high maximum field-effect mobility of 194 cm2/V·s has been obtained due to the high quality etching surface created with ELPEC etching.

Impact of gate electrode formation process on Al2O3/GaN interface properties and channel mobility

The interface properties of GaN metal–insulator–semiconductor (MIS) structures with a gate electrode metal deposited by electron beam (EB) or resistive heating evaporation were investigated. Also, the impact of the interface properties on the channel mobility in GaN MIS field-effect transistors was investigated. It was confirmed that interface charges including both interface states and positive fixed charges were introduced to an Al2O3/GaN interface by the formation of a gate electrode by EB evaporation. Consequently, the introduced interface charges degraded the electron mobility in the MIS channel.

Well-suppressed interface states and improved transport properties of AlGaN/GaN MIS-HEMTs with PEALD SiN gate dielectric

SiN deposited by plasma-enhanced atomic layer deposition (PEALD) is investigated as gate dielectric layer for GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs). The X-ray photoelectron spectroscopy (XPS) confirms low oxygen content in SiN-layer and the interface of SiN/(Al)GaN. The fabricated MIS-HEMTs exhibit significant reduction in gate leakage current (two or three orders of magnitude) and improvement in drain current (ID) characteristics, compared with the controlled HEMTs. A remarkable small threshold voltage (VTH) hysteresis (0.12 ± 0.05 V) and an enhanced 2DEG channel mobility are also achieved for PEALD SiN/(Al)GaN MIS-HEMTs. Simultaneously, a distribution of the interface states is quantitatively described by constant-capacitance deep-level transient spectroscopy (CC-DLTS), displaying a low density of 1.6 × 1013 cm−2 eV−1 at level depth of 0.03 eV and below 2.1 × 1012 cm−2 eV−1 at deep level depth of EC - ET > 0.4 eV. The suppressed interface traps density results in an improved performance for MIS-HEMTs. The dependence of the characteristics of MIS-HEMTs on SiN thickness (tSiN) was also studied in detail.

Current Transport Mechanism of High-Performance Novel GaN MIS Diode

In this work, we report a high-performance lateral GaN metal-insulator-semiconductor (MIS) diode with a low turn-on voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) of 0.32 V. Both in-depth theoretical calculations on current transport mechanisms and a forward conduction model are demonstrated. Based on the calculation results, the direct tunneling (DT) and thermionic emission (TE) coexist as the forward conduction mechanism, contributing to this low subthreshold swing (SS). Furthermore, a 1.8 nm thick Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> interlayer increases the equivalent Schottky barrier height ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Phi _{\text {B}}$ </tex-math></inline-formula> ) which effectively suppresses the reverse leakage to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.5\times 10^{-{4}}$ </tex-math></inline-formula> mA/mm at room temperature.

Current Understanding of Bias-Temperature Instabilities in GaN MIS Transistors for Power Switching Applications

GaN-based high-electron mobility transistors (HEMTs) have brought unprecedented performance in terms of power, frequency, and efficiency. Application of metal-insulator-semiconductor (MIS) gate structure has enabled further development of these devices by improving the gate leakage characteristics, gate controllability, and stability, and offered several approaches to achieve E-mode operation desired for switching devices. Yet, bias-temperature instabilities (BTI) in GaN MIS transistors represent one of the major concerns. This paper reviews BTI in D- and E-mode GaN MISHEMTs and fully recess-gate E-mode devices (MISFETs). Special attention is given to discussion of existing models describing the defects distribution in the GaN-based MIS gate structures as well as related trapping mechanisms responsible for threshold voltage instabilities. Selected technological approaches for improving the dielectric/III-N interfaces and techniques for BTI investigation in GaN MISHEMTs and MISFETs are also outlined.

Suppression and characterization of interface states at low-pressure-chemical-vapor-deposited SiNx/III-nitride heterostructures

Silicon nitride (SiNx) grown by low-pressure chemical vapor deposition (LPCVD) at a reduced growth temperature (650 °C), is utilized for fabrication of GaN metal–insulator-semiconductor (MIS) power devices. An atomically sharp interface between the LPCVD-SiNx and GaN was achieved, featuring a disordered region with only a thickness of 2.5 ~ 5 Å. A fabricated LPCVD-SiNx/GaN/AlGaN/GaN MIS diode exhibits a sharp two-step capacitance–voltage behavior with small frequency dispersion of 0.4 V in the right step. The improved interface was quantified by a well-elaborated constant-capacitance deep-level transient Fourier spectroscopy (CC-DLTFS), delivering quite low density of 1.5×1013cm-2 eV-1 at the level depth of 30 meV and about 4×1011~1.2×1012cm-2eV-1 at the level depth of 1 eV. Distributions of interface states can be described by a proposed physics-based decoupling function featuring an exponential law. A discrete level at the SiNx/GaN border or in the barrier layer with the level depth and the capture cross section being 0.8 eV and 5.5×10-14cm2 respectively, can thus be detached from the interface states.

Effect of surface treatment on electrical properties of GaN metal–insulator–semiconductor devices with Al2O3 gate dielectric

This research proposes an economical and effective method of 1-octadecanethiol (ODT) treatment on GaN surfaces prior to Al2O3 gate dielectric deposition. GaN-based metal–insulator–semiconductor (MIS) devices treated by HCl, O2 plasma and ODT are demonstrated. ODT treatment was found to be capable of suppressing native oxide and also of passivating the GaN surface effectively; hence the interface quality of the device considerably improved. The interface trap density of Al2O3/GaN was calculated to be around 3.0 × 1012 cm−2 eV−1 for devices with ODT treatment, which is a relatively low value for GaN-based MIS devices with Al2O3 as the gate dielectric. Moreover, there was an improvement in the gate control characteristics of MIS-HEMTs fabricated with ODT treatment.