GaN-based High Electron Mobility Transistors Research Articles

Suppression of Short-Channel Effects in AlGaN/GaN HEMTs Using SiNx Stress-Engineered Technique

In this work, we present the novel application of SiNx stress-engineering techniques for the suppression of short-channel effects in AlGaN/GaN high-electron-mobility transistors (HEMTs), accompanied by a comprehensive analysis of the underlying mechanisms. The compressive stress SiNx passivation significantly enhances the barrier height at the heterojunction beneath the gate, maintaining it above the quasi-Fermi level even as Vds rises to 20 V. As a result, in GaN devices with a gate length of 160 nm, the devices with compressive stress SiNx passivation exhibit significantly lower drain-induced barrier lowering (DIBL) factors of 2.25 mV/V, 2.56 mV/V, 4.71 mV/V, and 3.84 mV/V corresponding to drain bias voltages of 5 V, 10 V, 15 V, and 20 V, respectively. Furthermore, as Vds increases, there is an insignificant degradation in transconductance, subthreshold swing, leakage current, or output conductance. In contrast, the devices with stress-free passivation show relatively higher DIBL factors (greater than 20 mV/V) and substantial degradation in pinch-off performance and output characteristics. These results demonstrate that the SiNx stress-engineering technique is an attractive technique to facilitate high-performance and high-reliability GaN-based HEMTs for radio frequency (RF) electronics applications.

Improved breakdown voltage and dynamic Ron characteristics in normally-off GaN-based HEMTs featuring fully-recessed and bilayer-dielectric gate structure

Abstract The degradation of dynamic on-resistance (Ron) is a major challenge in GaN-based high electron mobility transistors (HEMTs), which seriously affects their performance and reliability. The degradation area of dynamic Ron mainly comes from two aspects. One is the region below the gate that also affects the threshold voltage (Vth) of the devices. And the other one is the interface region of the gate to drain access. The optimal device exhibits a Vth of 0.97 V, a small Vth hysteresis of only 20 mV, a high current density of 723 mA/mm, and a breakdown voltage (BV) of 760 V which could be further boosted when additional field plate design is employed. It is found that when high voltage drain stress is applied, a positive Vth shift is induced, leading to the decrease of the effective gate driving voltage, and thus the dynamic Ron of the devices is increased. Of particular concern is the effects of dielectric layer and/or interface of the access region on the dynamic Ron degradation, which can be alleviated by removing the dielectric layer of the access region.

The degradation mechanism of high power S-band AlGaN/GaN HEMTs under high temperature

Abstract The radio frequency (RF) degradation mechanism under high temperature is proposed in this paper. The saturated output power (P sat), power added efficiency (PAE) and gain of the HEMTs deteriorate significantly under high power dissipation operation conditions, which contribute to an elevation of the junction temperature (T j). The high T j causes a negative shift of the threshold voltage and a reduction of electron mobility, as well as enhancing the trapping effects of the devices. As a result, the P sat and PAE of the high-power HEMTs (P sat = 152 W) decreased by 0.76 dB and 8.3%, respectively, which is more severe compared to low-power HEMTs (P sat = 20 W), where P sat and PAE reduced by 0.16 dB and 3.1% when the operation temperature was increased from 25 °C to 150 °C. By increasing the gate-to-drain distance from 1.625 to 2.175 μm, drain current stability and high temperature reverse bias reliability are improved. The results demonstrate that the trapping effect can be suppressed by decreasing the electric field under the gate; therefore, the RF output characteristics are boosted by 1.2 W, 1 dB and 2.6% for a device with gate width of 11.52 mm.

Temperature dependence of the low-frequency noise in AlGaN/GaN fin field effect transistors

Low-frequency (LF) noise measurements are compared for Schottky-gate AlGaN/GaN heterostructure planar and fin field-effect transistors (FinFETs) as functions of gate voltage and measuring temperature. The noise of each device type is consistent with a carrier number fluctuation model. Similar effective defect-energy Eo distributions are derived for each of the two device architectures from measurements of excess drain-voltage noise-power spectral density vs temperature from 80 to 380 K. Defect- and/or impurity-related peaks are observed in the inferred energy distributions for Eo < 0.2 eV, Eo ≈ 0.45 eV, and Eo > 0.6 eV. Significant contributions to the LF noise are inferred for nitrogen vacancies and ON and FeGa impurity complexes. Ga dangling bonds at fin interfaces with gate metal are likely candidates for enhanced noise observed in FinFETs, relative to planar devices. Reducing the concentrations of these defects and impurity complexes should reduce the LF noise and enhance the performance, reliability, and radiation tolerance of GaN-based high electron mobility transistors.

Improvement of DC Performance and RF Characteristics in GaN-Based HEMTs Using SiNx Stress-Engineering Technique.

In this work, the DC performance and RF characteristics of GaN-based high-electron-mobility transistors (HEMTs) using the SiNx stress-engineered technique were systematically investigated. It was observed that a significant reduction in the peak electric field and an increase in the effective barrier thickness in the devices with compressive SiNx passivation contributed to the suppression of Fowler-Nordheim (FN) tunneling. As a result, the gate leakage decreased by more than an order of magnitude, and the breakdown voltage (BV) increased from 44 V to 84 V. Moreover, benefiting from enhanced gate control capability, the devices with compressive stress SiNx passivation showed improved peak transconductance from 315 mS/mm to 366 mS/mm, along with a higher cutoff frequency (ft) and maximum oscillation frequency (fmax) of 21.15 GHz and 35.66 GHz, respectively. Due to its enhanced frequency performance and improved pinch-off characteristics, the power performance of the devices with compressive stress SiNx passivation was markedly superior to that of the devices with stress-free SiNx passivation. These results confirm the substantial potential of the SiNx stress-engineered technique for high-frequency and high-output power applications, which are crucial for future communication systems.

(Electronics and Photonics Division Award) Research Advances Wide- and Ultrawide-Bandgap Power Switching Devices

Wide bandgap semiconductors such as SiC and GaN (WBG) and emerging ultrawide-bandgap materials such as Ga2O3, AlGaN, and Diamond (UWBG) represent the next-generation materials for high performance medium voltage and high voltage power switch technology. Such devices have a wide range of immediate Naval applications, including high-power satellite communications and radar, unmanned underwater and aerial vehicles, ship drive components, and hybrid vehicle inverters. Vertical SiC power device technology has matured rapidly over the past two decades, owing to advances in substrates, a fundamental understanding of epitaxial growth to eliminate performance-limiting defects, as well as device design breakthroughs. This has enabled breakthroughs in highly integrated module design for medium voltage power conversion with switching frequency >100 kHz. In parallel, lateral GaN-based high electron mobility transistor (HEMT) technology has been highly successful for RF power amplifiers and is well positioned to supersede GaAs-based microwave circuits. Recently, GaN-based vertical and lateral power devices have attracted significant interest due to promising device results coupled with progress in native substrate, epitaxial growth, and processing technology developments. This seminar will present an overview of the WBG/UWBG power device efforts at NRL. This research has four primary focus areas – 1) thermal management in III-N power device structures by diamond thin film integration, 2) characterization of substrate materials and homoepitaxial layers used for drift regions of power devices identify appropriate specifications and benchmark performance, 3) process module development, particularly for selective area doping by ion implantation, and 4) pilot production manufacturing of 1.2kV-class PiN diodes including reliability assessments to identify and mitigate performance limiting defects.

Optimization of embedded cooling for hotspots based on compound plate thermal spreading model

Heat fluxes of GaN-based high electron mobility transistors (HEMTs) can reach dozens of kilowatts per square centimeter, and the heat is generated only within a small area with feature size of micrometer to millimeter length scales, which poses a huge challenge for thermal management. In this study, an embedded microfluidic cooling solution is proposed to dissipate heat from the hotspots, and thermal test vehicles are fabricated using the Micro-Electro-Mechanical System (MEMS) process. Cooling performances of hotspots with sizes ranging from 40 × 40 μm2 to 500 × 500 μm2 and varying locations are demonstrated. Thermal resistances of the test samples are analysed and the heat transfer coefficient can achieve 1.5 × 105 W/(m2∙K) using embedded microchannel cooling. We propose a compound plate spreading thermal resistance model to demonstrate the effect of the dielectric layer and the size of the heat source on heat dissipating capability of the microfluidic cooling system. Based on the thermal spreading model, when the heat source is small, integrating high thermal conductivity materials near the heat source can reduce its total thermal resistance by two orders of magnitude. By balancing the heat spreading resistance with the convective resistance of microchannel cooling, we find that ∼1 mm can be considered as the critical length for distinguishing the primary thermal management approach for different sized hotspots. This paper provides useful design guidelines for embedded microchannel cooling of devices with localized heat generation patterns, such as HEMT devices.

Threshold voltage mapping at the nanoscale of GaN-based high electron mobility transistor structures using hyperspectral scanning capacitance microscopy

Threshold voltage mapping at the nanoscale of GaN-based high electron mobility transistor structures using hyperspectral scanning capacitance microscopy

High-speed independent polarization modulation based on dual channel 2DEG anisotropic terahertz metasurfaces.

In communication and imaging systems, anisotropic metasurfaces bring new degrees of freedom for the independent control of electromagnetic waves with different polarizations. This paper proposes a dual-polarization modulation metasurface (DPMM) operating in the terahertz (THz) frequency range, which can effectively and independently modulate two orthogonally linearly polarized electromagnetic waves. The metasurface unit adopts an anisotropic structure, and by integrating multiple GaN-based high electron mobility transistors (GaN-HEMTs) into the anisotropic structure, independent control of the two-dimension electron gas (2DEG) carrier concentration in the dual-polarization channel is achieved, enabling selective modulation of x-polarization and y-polarization waves. Simulation and static experimental results demonstrate the excellent modulation isolation performance of the DPMM, with a maximum isolation exceeding 45 dB. Dynamic experiments further highlight the high-speed modulation effect, with modulation speeds exceeding 1 GHz for a single channel and an overall modulation speed of 2 GHz for dual polarization, highlighting its potential for enhancing channel capacity and information throughput in THz communication and imaging systems.

Comparison of performance in GaN-HEMTs on thin SiC substrate and sapphire substrates

We have investigated the electrical properties of GaN-based high electron mobility transistors (HEMT) on N+-type 4H SiC substrates and on sapphire substrate as a reference. The three-terminal off-state breakdown voltage (BV) as a function of gate-drain spacing (LGD) was measured. Both devices possess superior Baliga figure of merit parameters (BFOM= BV3/Ron). For GaN/Sapphire with LGD of 10 μm, Ron is 14.65 mΩ·cm2 and the corresponding BFOM yields a remarkably high value of 9.88 × 108V2·Ω−1·cm−2. Conversely, GaN/N+ SiC with 20 μm LGD exhibited an Ron of 43.23 mΩ·cm2 and a BFOM value of 1.55 × 107V2·Ω−1·cm−2. In addition, we perform AFM, XRD, SEM and TEM analysis to further explore the differences in the DC-current properties for these two distinct substrates. The XRD FWHM scales with surface roughness, moreover grain boundaries for GaN-based HEMTs grown on SiC are more distinct compared to Sapphire substrate. This study provide valuable insight into the structural and morphological disparities that may contribute to the observed variations in device performance.

Temperature rise detection in GaN high-electron-mobility transistors via gate-drain Schottky junction forward-conduction voltages

An electrical measurement method for the junction temperature and thermal resistance of GaN high-electron-mobility transistors (HEMTs) is discussed. It is based on the forward voltage drop across the gate-drain Schottky diode. During measurement of this temperature-sensitive parameter, the source is left floating while the drain is grounded. Previous studies have shown that the hot spot in GaN HEMTs is near the gate side, close to the drain. The forward voltage drop across the gate-drain diode yields higher and more consistent temperatures relative to those using the forward voltage drop across the gate-source Schottky diode. This method could potentially provide more accurate data for thermal management and reliability analyses of GaN-based HEMTs. The maximum temperature of the sample was 44.8 °C on the grate-drain side and approximately 40.5 °C on the gate-source side when the sample exhibited 3.44W thermal power consumption for 1 min. Hence, the proposed method is practical and instructive.

Effect of annealing on the electrical performance of N-polarity GaN Schottky barrier diodes

A nitrogen-polarity (N-polarity) GaN-based high electron mobility transistor (HEMT) shows great potential for high-frequency solid-state power amplifier applications because its two-dimensional electron gas (2DEG) density and mobility are minimally affected by device scaling. However, the Schottky barrier height (SBH) of N-polarity GaN is low. This leads to a large gate leakage in N-polarity GaN-based HEMTs. In this work, we investigate the effect of annealing on the electrical characteristics of N-polarity GaN-based Schottky barrier diodes (SBDs) with Ni/Au electrodes. Our results show that the annealing time and temperature have a large influence on the electrical properties of N-polarity GaN SBDs. Compared to the N-polarity SBD without annealing, the SBH and rectification ratio at ±5 V of the SBD are increased from 0.51 eV and 30 to 0.77 eV and 7700, respectively, and the ideal factor of the SBD is decreased from 1.66 to 1.54 after an optimized annealing process. Our analysis results suggest that the improvement of the electrical properties of SBDs after annealing is mainly due to the reduction of the interface state density between Schottky contact metals and N-polarity GaN and the increase of barrier height for the electron emission from the trap state at low reverse bias.

Effect of Fe Doping Profile on Current Collapse in GaN-based RF HEMTs.

Using computer-aided design (TCAD) simulation, the impact of the Fe doping profile, including concentration, decay rate, and depth of the doping region on current-collapse magnitude (▵CC) in 0.5-μm gated GaN-based high electron mobility transistors (HEMTs) is systematically investigated. Accurate simulation models are established and developed to facilitate the fabrication of electronics. It is elucidated that the intricate interplay between trapping and de-trapping of Fe-related traps at the gate-drain edge is responsible for current collapse. The concentration and decay rate of the doping region have a more significant impact on current collapse than the depth. Increased trap state density near two-dimensional electron gas (2DEG) channel caused by deep-level acceptors would boost ▵CC. However, a minor dynamic reduction in 2DEG density (nT) induces a relatively small ▵CC. By adjusting the concentration, decay rate, and depth of the doping region, ▵CC of GaN-based Radio Frequency (RF) HEMTs can be reduced by approximately 50.3 %. The optimized distribution of Fe doping discussed in this work helps to prepare GaN-based RF HEMTs with a limited current collapse effect.

Performance improvement of enhancement-mode GaN-based HEMT power devices by employing a vertical gate structure and composite interlayers*

In this work, p-n junction vertical gate (JVG) and polarization junction vertical gate (PVG) structures are for the first time proposed to improve the performance of GaN-based enhancement-mode (E-mode) high electron mobility transistor (HEMT) devices. Compared with the control group featuring the vertical gate structure, a highly improved threshold voltage (V th) and breakdown voltage (BV) are achieved with the assistance of the extended depletion regions formed by inserting single or composite interlayers. The structure dimensions and physical parameters for device interlayers are optimized by TCAD simulation to adjust the spatial electric field distribution and hence improve the device off-state characteristics. The optimal JVG-HEMT device can reach a V th of 3.4 V, a low on-state resistance (R on) of 0.64 mΩ cm2, and a BV of 1245 V, while the PVG-HEMT device exhibits a V th of 3.7 V, an R on of 0.65 mΩ cm2, and a BV of 1184 V, which could be further boosted when an additional field plate design is employed. Thus, the figure-of-merit value of JVG- and PVG-HEMT devices rise to 2.4 and 2.2 GW cm−2, respectively, much higher than that for the VG-HEMT control group (1.0 GW cm−2). This work provides a novel technical approach to realize higher-performance E-mode HEMTs.

Insights into dynamic switching behavior and electric field distribution of depletion-mode GaN HEMT with bonding pad over active layout

Bonding pad over active (BPOA) layout, which stacks traditional horizontal structure pad electrodes vertically above the active area, is an area-effective device architecture and packaging-enabled solution for GaN-based high electron mobility transistors (HEMTs). In this work, the dynamic switching and electric field distribution of such layout, as well as associated capacitance–voltage and trapping characteristics, are comprehensively studied on D-mode GaN-on-sapphire HEMT by performing numerical simulations. In terms of different pad electrodes covering the active area, BPOA is composed of various structures such as gate-related and drain-related BPOAs (i.e. G-BPOA and D-BPOA), among which G-BPOA exhibits inferior switching characteristics due to the additional introduction of Miller capacitance that prolongs the device switching, while breakdown voltage of D-BPOA is 400–900 V lower than other BPOA counterparts due to the interplay between D-BPOA and the drain electrode. Furthermore, the effects of trap capture cross section and trap density on switching characteristics are evaluated. These results highlight the differences in electrical characteristics of various structures within the BPOA layout, and provide valuable insights into BPOA device design and performance improvement.

Improving Optical and Electrical Characteristics of GaN Films via 3D Island to 2D Growth Mode Transition Using Molecular Beam Epitaxy

Molecular beam epitaxy (MBE) is demonstrated as an excellent growth technique for growing a low-defect GaN channel layer, which is crucial for controlling vertical leakage current and improving breakdown voltage (BV) in GaN-based high-electron mobility transistors (HEMTs). The 3D islands to 2D growth mode transition approach was induced by modulating substrate growth temperature (Tsub), displaying an overall improvement in film quality. A comprehensive investigation was conducted into the effects of Tsub on surface morphologies, crystal quality, and the optical and electrical properties of GaN films. Optimal results were achieved with a strain-relaxed GaN film grown at 690 °C, exhibiting significantly improved surface characteristics (root-mean-square roughness, Rq = 0.3 nm) and impressively reduced edge dislocations. However, the film with the smoothest surface roughness, attributed to the effect of the Ga-rich condition, possessed a high surface pit density, negatively affecting optical and electrical properties. A reduction in defect-related yellow emission further confirmed the enhanced crystalline quality of MBE GaN films. The optimized GaN film demonstrated outstanding electrical properties with a BV of ~1450 V, surpassing that of MOCVD GaN (~1180 V). This research significantly contributes to the advancement of MBE GaN-based high electron mobility transistor (HEMT) applications by ensuring outstanding reliability.

Impact of Parasitic Gate Capacitance on RF Performance in GaN-Based HEMTs for X-Band Applications

GaN-based high-electron-mobility transistors (HEMTs) are intensively researched for high-power radio frequency (RF), low noise, and aerospace applications, thanks to their high breakdown electric field, high carrier mobility and density at the hetero-interface, and wide bandgap [1-2]. For the improvement of RF performance, various approaches have been reported, including T-gate structure [3-4], surface passivation [5], n+-regrown source and drain contact [6], thin barrier structure [7], and graded-channel [8]. Among them, the T-gate structure has been extensively employed for the reduction of the gate resistance (Rg ) and thereby improvement of the RF performance. However, the usage of the wide T-gate structure enlarges parasitic gate capacitance components, which deteriorates the RF performance. As a result, one should pay careful attention to the dimension of the wide T-gate structure to reduce Rg as much as possible, not to enlarge the parasitic gate capacitance components. This motivates us to explore the optimum dimension of the wide T-gate structure in GaN-based HEMTs for X-band RF applications.To investigate the detailed impact of the gate resistance and parasitic gate capacitance components, we fabricated LG = 0.15 μm GaN-based HEMTs with various dimensions of the T-gate head from 0.5 to 0.8 μm during an e-beam lithography process step. The unit gate width (WG ) and number of gate finger (NF ) were 100 μm and 2, respectively.For comparison of the device characteristics with respect to the dimension of the gate head, DC and RF measurements were conducted for the fabricated GaN-based HEMTs with various dimensions of T-gate head. The DC characteristics in terms of the threshold voltage (VTH ), the maximum transconductance (gm,max ), and the saturation drain current (Id,sat ) were almost identical, regardless of the dimension of the T-gate head. On the contrary, the current-gain cut-off frequency (fT ) and maximum oscillation frequency (fMAX ) were improved by 26.5% and 21.0%, respectively, when the T-gate head size was reduced from 0.8 to 0.5 μm.In an effort of explore the origin of the dependence of the T-gate head on the RF performance, we have carried out small-signal modeling to extract the parasitic gate capacitance and gate resistance components from the measured RF data. As the T-gate head size was reduced from 0.8 to 0.5 μm, the gate-source parasitic capacitance component (Cgs_par ) was reduced by 19%, while the gate resistance component was increased by 32%. In our device design and fabrication, it turned out that the reduction of Cgs_par was more beneficial than the increase of Rg , leading to the improved RF performance with the gate head size decrease.In this work, our systematic research revealed that, unlike earlier reports [3-4], the reduction of the parasitic gate capacitance was essential for the improvement of the RF performance as opposed to the reduction of the gate resistance in LG = 0.15 μm GaN-based HEMTs for X-band RF applications. Acknowledgement This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MIST) (No. NRF-2021M3C1C3097672).

Novel T-Shaped Gate Structure of AlGaN/GaN HEMTs on Si for RF Application

Due to the high electron saturation velocity and breakdown electric field, GaN-based high electron mobility transistors (HEMTs) have been widely used in high frequency and power application, such as telecommunication, satellite communication, and radar system [1]. Since first demonstration of AlGaN/GaN HEMTs in 1993 [2], the RF performance of these device has continuously improved by the progress on epitaxy and device scaling technology [3].The current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) from the small-signal equivalent circuit of the HEMT are derived by the following equations [4].From these equations, it can be concluded that in order to achieve high frequency operation, HEMTs should be designed with a T-shaped gate structure that simultaneously achieves low gate resistance (Rg) and low parasitic capacitance (Cgs and Cgd). However, there are complex fabrication processes to form the T-shaped gate. Typically, the T-shaped gate structure is implemented through electron beam lithography process using a tri-layer resist such as PMMA/PMGI/PMMA, which requires multiple exposures or developments. Multiple exposures can cause overlay errors that can significantly affect the T-shaped gate with smaller gate lengths [5]. Also, it is difficult to obtain an undercut structure that enables a good lift-off and guarantees a high yield due to the need for precise dose control. In addition, since the T-shaped gate has an unstable structure in which a narrow foot supports the weight of a wide head, the gate may collapse during a subsequent process.In this work, we fabricated a novel T-shaped gate using the negative e-beam resist HSQ, which offers a simple T-shaped gate fabrication process. The HSQ that was exposed to e-beam is located underneath the gate head and on both sides of the gate foot in our novel T-shaped gate design, providing a robust structure. The HSQ-assisted gate HEMTs exhibit comparable DC/RF performance compared to conventional T-shaped gate HEMTs. Acknowledgement This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MIST) (No. NRF-2021M3C13097672).

(Invited) Selective Area Growth, Etching, and Doping of GaN By MOCVD for Power Electronics

Gallium Nitride (GaN) possesses a wide band gap and excellent transport properties, making it a highly promising material for high-power and high-frequency applications. Microwave power amplification for commercial and military purposes has already benefited from GaN-based high electron mobility transistors (HEMTs). However, currently available GaN optoelectronic and electronic devices use planar junctions and heterostructures prepared by epitaxy, typically via metalorganic chemical vapor deposition (MOCVD). To enable more sophisticated device configurations, in-plane lateral junctions are necessary. The most effective method for achieving this is through selective area etching (SAE) followed by selective area growth (SAG). In this talk, we will discuss the progress made at Yale in the selective-area etching, growth, and doping of GaN.Selective-area etching of GaN is the most challenging and critical step in this process. Instead of using conventional ICP etching, we have employed tertiarybutylchloride (TBCl) as an in-situ chemical etchant of GaN in MOCVD to create smooth trenches and remove plasma etching-generated damages on the surface. With electrical and material characterizations, we have confirmed that TBCl etching is a low-damage and clean etching process. We will also describe our recent efforts to bypass the constraint of dielectric masking during in-situ etching and perform maskless selective area etching (SAE) to create low-defect lateral p-n junctions for GaN power electronics. Additionally, we will discuss non-planar selective-area growth and doping, including the principles of growth evolution, non-uniform Mg distribution, and parasitic impurities.This work is supported by the Advanced Research Projects Agency-Energy (ARPA-E), U.S. DOE, under DE-AR0000871 as part of the PNDIODES program managed by Dr. Isik Kizilyalli.

Effects of Thermal Boundary Resistance on Thermal Management of Gallium-Nitride-Based Semiconductor Devices: A Review.

Wide-bandgap gallium nitride (GaN)-based semiconductors offer significant advantages over traditional Si-based semiconductors in terms of high-power and high-frequency operations. As it has superior properties, such as high operating temperatures, high-frequency operation, high breakdown electric field, and enhanced radiation resistance, GaN is applied in various fields, such as power electronic devices, renewable energy systems, light-emitting diodes, and radio frequency (RF) electronic devices. For example, GaN-based high-electron-mobility transistors (HEMTs) are used widely in various applications, such as 5G cellular networks, satellite communication, and radar systems. When a current flows through the transistor channels during operation, the self-heating effect (SHE) deriving from joule heat generation causes a significant increase in the temperature. Increases in the channel temperature reduce the carrier mobility and cause a shift in the threshold voltage, resulting in significant performance degradation. Moreover, temperature increases cause substantial lifetime reductions. Accordingly, GaN-based HEMTs are operated at a low power, although they have demonstrated high RF output power potential. The SHE is expected to be even more important in future advanced technology designs, such as gate-all-around field-effect transistor (GAAFET) and three-dimensional (3D) IC architectures. Materials with high thermal conductivities, such as silicon carbide (SiC) and diamond, are good candidates as substrates for heat dissipation in GaN-based semiconductors. However, the thermal boundary resistance (TBR) of the GaN/substrate interface is a bottleneck for heat dissipation. This bottleneck should be reduced optimally to enable full employment of the high thermal conductivity of the substrates. Here, we comprehensively review the experimental and simulation studies that report TBRs in GaN-on-SiC and GaN-on-diamond devices. The effects of the growth methods, growth conditions, integration methods, and interlayer structures on the TBR are summarized. This study provides guidelines for decreasing the TBR for thermal management in the design and implementation of GaN-based semiconductor devices.