GaN-based Field Effect Transistors Research Articles

Analytical models for GaN-based heterostructure-free normally off fin-shaped field-effect transistor

Analytical models for threshold voltage and subthreshold swing of GaN-based fin-shaped field-effect transistors (FinFETs) are obtained. Analytical expressions for the drain-induced barrier lowering effect and threshold voltage roll-off effect are presented. The explicit expressions for threshold voltage and subthreshold swing make the model suitable for being embedded in circuit simulations and design tools.

NiO gate GaN-based enhancement-mode hetrojunction field-effect transistor with extremely low on-resistance using metal organic chemical vapor deposition regrown Ge-doped layer

In this paper, we present a normally-off GaN-based transistor with an extremely low on-resistance (Ron) fabricated by using a Ge-doped n++-GaN layer for ohmic contacts. We developed a novel GaN regrowth technique using Ge as a dopant, which achieved an extremely high doping concentration of 1 × 1020 cm−3, and thereby the lowest specific contact resistance of 1.5 × 10−6 Ω·cm2. The NiO gate fabricated using an atomic layer deposition technique reduced the spacing between the source and drain electrodes. The fabricated device showed the record-breaking Ron of 0.95 Ω·mm with the maximum drain current and transconductance of 1.1 A/mm and 490 mS/mm, respectively. Note that the obtained threshold voltage was 0.55 V. This extremely low Ron characteristic indicates the great potential of NiO-gate GaN-based heterojunction field-effect transistors.

On the design of GaN vertical MESFETs on commercial LED sapphire wafers

Design of GaN-based vertical metal-semiconductor field-effect transistors (MESFETs) on commercial light-emitting-diode (LED) epi-wafers has been proposed and proof of principle devices have been fabricated. In order to better understand the IV curves, these devices have been simulated using the charge transport model. It was found that shrinking the drain pillar size would significantly help in reaching cut-off at much lower gate bias even at high carrier concentration of unintentionally doped GaN and considerable leakage current caused by the Schottky barrier lowering. The realization of these vertical MESFETs on LED wafers would allow their chip-level integration. This would open a way to many intelligent lighting applications like on-chip current regulator and signal regulation/communication in display technology.

Design and simulation of high-breakdown-voltage GaN-based vertical field-effect transistor with interfacial charge engineering

A high-breakdown-voltage GaN-based vertical field-effect transistor with negative fixed interfacial charge engineering (GaN ICE-VHFET) is proposed in this work. The negative charge inverts an n-GaN buffer layer along the oxide/GaN interface, inducing a vertical hole layer. Thus, the entire buffer layer consists of a p+-hole inversion layer and an n-pillar buffer layer, and the p-pillar laterally depletes the n-GaN buffer layer, and the electric field distribution becomes more uniform. Simulation results show that the breakdown voltage of the GaN ICE-VHFET increases by 193% and the on-resistance of such a device is still very low when compared with those of conventional vertical FETs. Its figure of merit even exceeds the GaN one-dimensional limit.

On a GaN-based ion sensitive field-effect transistor (ISFET) with a hydrogen peroxide surface treatment

A GaN-based ion sensitive field-effect transistor (ISFET) prepared by a hydrogen peroxide (H2O2) treatment is fabricated and studied. A 3-nm-thick GaxOy layer formed by an immersion in H2O2 solution is examined and confirmed by EDS and XPS analyses. Experimentally, the studied pH-ISFET presents a higher voltage sensitivity (54.88mV/pH), a higher current sensitivity (−56.09μA/pHmm), a lower drift rate (1.41μA/hmm), an extremely low hysteresis (0.4mV), and a lower voltage decay rate (−0.14mV/pHday) after 28 days. Moreover, insignificant interference effects from Na+ and K+ ions were observed. Thus, the studied GaN-based ISFET utilizing an H2O2 treatment promises to fabricate high-performance pH sensing applications.

GaN FET Nonlinear Modeling Based on Double Pulse <formula formulatype="inline"><tex Notation="TeX">${ I}/{ V}$</tex></formula> Characteristics

A state-space empirical nonlinear model for GaN-based field-effect transistors (FETs) is defined, along with the associated identification procedures based on a recently published double pulse measurement technique. Charge trapping phenomena are dealt with in terms of a nonlinear state equation, which describes the rate of change of the trap state as a function of its actual distance from the corresponding steady state. Model experimental validation is carried out, after on-wafer characterization of a 1-mm AlGaN-GaN on SiC FET, both under strong and mild nonlinear operation.

Call for papers: Noise modeling of high-frequency semiconductor devices

Noise processes in solid-state active devices often determine their fundamental operational limits. This is especially true in situations where a device operates under tight sensitivity and accuracy constraints, as is the case in satellite communication systems, aerospace instrumentation, and deep-space radio astronomy. Today’s ultra-high frequency transistors that meet these demanding low-noise performance characteristics often leverage progressive device downscaling techniques in conjunction with improved semiconductor alloys. To enable the design of next-generation low-noise devices, however, accurate and flexible models that characterize the connection between the physics of microscopic noise processes and measurable macroscopic performance are called for. The objective of this Special Issue is to collect and disseminate recent results addressing the topic of modeling and simulation of the macroscopic noise performance of highfrequency transistors including but not limited to GaAs-based and GaN-based field-effect transistors, Si metal–oxide–semiconductor FETs and FinFETs, InP-based high-electron-mobility transistors, and GaAs and SiGe heterojunction bipolar transistors. It is worth pointing out that because of frequency up-conversion phenomenacaused by a device’snonlinearities,lowfrequencynoiseprocessesmaystrongly impact microwave and millimeter wave behavior as well. Contributions focusing on low-frequency noise modeling therefore will be considered as well. This issue will include both invited and contributed manuscripts. Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1099-1204/ homepage/ForAuthors.html. Potential contributors may contact the Guest Editors to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM’s manuscript website http://mc. manuscriptcentral.com/ijnm, with a statement that they are intended for this Special Issue.

Vertical GaN-based trench metal oxide semiconductor field-effect transistors on a free-standing GaN substrate with blocking voltage of 1.6 kV

This paper reports the characteristics of vertical GaN-based trench metal–oxide–semiconductor field-effect transistors on a free-standing GaN substrate with a blocking voltage of 1.6 kV. The high blocking voltage was obtained by using field plate edge termination around the isolation mesa of the transistor. To our knowledge, the blocking voltage is the highest ever reported for vertical GaN-based transistors on free-standing GaN substrates. Normally off operation with a threshold voltage of 7 V is also demonstrated.

GaN Power Transistor Modeling for High-Speed Converter Circuit Design

A circuit simulator has been developed to design power losses of high-frequency power converters using GaN-based heterojunction field-effect transistors (GaN-HFETs). The simulator is based on a high-accuracy equivalent model of GaN-HFETs with peculiar device physics and high-speed loss calculation methods. The simulated power losses were consistent with measured results in dc-dc converters constructed by a GaN-HFET and a SiC Schottky diode with more than 93% accuracy. By utilizing the developed simulator, key requirements in heat-dissipation technologies, circuit parasitic inductances, and gate-drive technologies for next-generation converters are discussed.

Polarization-Engineered Ga-Face GaN-Based Heterostructures for Normally-Off Heterostructure Field-Effect Transistors

Polarization-engineered Ga-face GaN-based heterostructures with a GaN cap layer and an AlGaN/p-GaN back barrier have been designed for normally-off field-effect transistors (FETs). The simulation results show that an unintentionally doped GaN cap and p-GaN layer in the buffer primarily deplete electrons in the channel and the Al0.2Ga0.8N back barrier helps to pinch off the channel. Experimentally, we have demonstrated a normally-off GaN-based field-effect transistor on the designed GaN cap/Al0.3Ga0.7N/GaN channel/Al0.2Ga0.8N/p-GaN/GaN heterostructure. A positive threshold voltage of 0.2 V and maximum transconductance of 2.6 mS/mm were achieved for 80-μm-long gate devices. The device fabrication process does not require a dry etching process for gate recessing, while highly selective etching of the GaN cap against a very thin Al0.3GaN0.7N top barrier has to be performed to create a two-dimensional electron gas for both the ohmic and access regions. A self-aligned, selective etch of the GaN cap in the access region is introduced, using the gate metal as an etch mask. The absence of gate recess etching is promising for uniform and repeatable threshold voltage control in normally-off AlGaN/GaN heterostructure FETs for power switching applications.

Polarization-reduced quaternary InAlGaN/GaN HFET and MISHFET devices

The reduction of the polarization charge in a GaN-based single-heterostructure field-effect transistor (HFET) by polarization engineering is proposed as a method for achieving normally off operation. The concept minimizes the dependence of the threshold voltage on the barrier layer thickness. Therefore, thicker gate dielectrics for suppression of gate leakage currents can be applied without a shift in threshold voltage. A polarization-reduced enhancement-mode (E-mode) InAlGaN/GaN HFET is presented and demonstrates the basic working principle. Also an insulated-gate device with only minor shift in threshold voltage compared to the HFET validates the new concept and demonstrates the advantages compared to commonly applied concepts for E-mode operation.

High-responsivity, low-noise, room-temperature, self-mixing terahertz detector realized using floating antennas on a GaN-based field-effect transistor

Using only optical lithography, we have fabricated a GaN/AlGaN high-electron mobility transistor with distinctive source and drain antennas electrically isolated from the electron channel. Working at room temperature, it efficiently detects terahertz radiation via self-mixing, with a responsivity (3.6 kV/W) exceptionally high for a III-V device and with a noise (40pW/Hz) just above the thermal limit. Performance improves at 77 K. While the device itself is micrometer-sized, our modeling indicates the asymmetric antennas induce a rather localized (<200 nm) region of strong self-mixing. Thus, a nanometer-scale active region is achieved by design and without recourse to electron-beam lithography.

245-GHz InAlN/GaN HEMTs With Oxygen Plasma Treatment

We report lattice-matched In0.17Al0.83N/GaN high-electron mobility transistors on a SiC substrate with a record current gain cutoff frequency (fT). The key to this performance is the use of an oxygen plasma treatment to form a thin oxide layer on the InAlN barrier and to reduce the gate leakage current by more than two orders of magnitude. In addition, the RF transconductance (gm) collapse is reduced in the O2-treated devices, which results in a significant improvement in the fT . In a transistor with a gate length of 30 nm, an fT of 245 GHz is achieved, the highest value ever reported in GaN-based field-effect transistors.

Breakdown Voltage Enhancement of AlGaN/GaN High-Electron-Mobility Transistors via Selective-Area Growth for Ohmic Contacts over Ion Implantation

Selective-area growth (SAG) based on plasma-assisted molecular-beam epitaxy (PAMBE) was shown to facilitate improvement of Ohmic contacts and direct-current (DC) characteristics for GaN-based field-effect transistors (FETs) over the widely accepted ion-implantation technique. Twofold improvements in breakdown voltage were also demonstrated for samples grown on both sapphire and silicon substrates. An AlGaN/GaN high-electron-mobility transistor (HEMT) fabricated with PAMBE-SAG exhibited a low specific contact resistivity of 5.86 × 10−7 Ω cm2, peak drain current of 420 mA/mm, and high breakdown voltage of 77 V. These results demonstrate that PAMBE-SAG is suited to fabricating HEMTs for high-power applications.

Over 100A operation normally-off AlGaN/GaN hybrid MOS-HFET on Si substrate with high-breakdown voltage

Abstract The demonstration of a normally-off n-channel AlGaN/GaN hybrid metal–oxide–semiconductor heterojunction field-effect transistor (MOS-HFET) on Si substrate for large-current operation is reported. The AlGaN/GaN hybrid MOS-HFET has the merits of both a MOS channel and an AlGaN/GaN heterostructure with high mobility two dimensional electron gases (2DEG). The maximum drain current of over 100 A with 2 μm channel length and 340 mm channel width is performed. This is the best value for a normally-off GaN-based field-effect transistor. The specific on-state resistance is 9.3 mΩ cm 2 . The fabricated device also exhibits good normally-off operation with the threshold voltage of 2.7 V and the breakdown voltage of over 600 V.

Low Hysteresis Dispersion La2O3 AlGaN ∕ GaN MOS-HEMTs

metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) using electron-beam evaporated high-dielectric-constant (high-) lanthanum oxide layer as the gate insulator have been investigated and compared with the traditional GaN HEMTs. The dielectric constant of the insulator layer developed in this study was 13.1. In addition, a negligible hysteresis voltage shift in the capacitance–voltage curves can be obtained after high temperature annealing. The compositions and the crystalline structures of with different annealing temperatures were observed by X-ray photoelectron spectroscopy and X-ray diffraction, respectively. The thin film achieved a good thermal stability after 200, 400, and postdeposition annealing owing to its high binding energy characteristics. Moreover, the gate leakage current of a traditional metal gate GaN HEMT can be suppressed for 1 order of magnitude after inserting a insulator between Ni and AlGaN, resulting in a better pulsed-mode operation. The device linearity was also improved due to its flat and wide transconductance distribution, which was analyzed by a polynomial curve-fitting technique. Therefore, is a potential candidate high- material for the gate insulator to enhance the GaN-based field effect transistor performance while scaling down the device dimension and device reliability at high power operation.

Electron-polar optical phonon scattering suppression and mobility enhancement in wurtzite heterostructures

We have shown theoretically that the electron mobility in wurtzite AlN/GaN/AlN heterostructures can be enhanced by compensating the built-in electric field with the externally applied perpendicular electric field and by introducing a shallow InxGa1-xN channel in the center of GaN potential well. It was found that two- to fivefold increase of the room temperature electron mobility can be achieved. The tuning of the electron mobility with the external electric field or InxGa1-xN channel can be useful for the design of GaN-based field-effect transistors and optoelectronic devices.

HIGHER-ORDER PLASMON RESONANCES IN GAN-BASED FIELD-EFFECT TRANSISTOR ARRAYS

Terahertz (THz) response spectra of GaN-based field-effect transistor (FET) arrays are calculated in a self-consistent electromagmetic approach. Two types of FET arrays are considered: (i) FET array with a common channel and a large-area grating gate, and (ii) array of FET units with separate channels and combined intrinsic source and drain contacts. It is shown that the coupling between plasmons and THz radiation in the FET array can be strongly enhanced as compared to a single-unit FET. The computer simulations show that the higher-order plasmon modes can be excited much more effectively in the array of FET units with separate channels and combined source and drain contacts then in FET array with a common channel and a large-area grating gate.

Observation of cross-sectional electric field for GaN-based field effect transistor with field-modulating plate

Cross-sectional potential distribution of a GaN-based field effect transistor with a field-modulating plate has been measured by Kelvin prove force microscopy to investigate the effect of the field-modulating plate on an electric field under high-voltage biasing conditions. The observed potential distribution clearly revealed that the introduction of the field-modulating plate is effective in relaxing the peak electric field intensity at the drain side of the gate edge. Furthermore, the authors experimentally observed that the peak of electric field splits into two positions: drain-side edges of the gate and field-modulating plate electrodes.

C-Band GaN-Based Field-Effect-Transistor Power Amplifiers with 170-W Output Power

A C-band high-power amplifier is successfully developed with two-chip 24-mm-wide GaN-based field effect transistors (FET). At 5.0 GHz, the fabricated GaN-FET amplifier delivers a 171 W cw output power with 11 dB linear gain and 38% power-added efficiency with a drain voltage of 50 V. To the best of our knowledge, this is the highest cw output power achieved from a solid-state power amplifier at C-band.