Gallium Zinc Oxide Transistors Research Articles

IGZO TFT Backplane Integration for µLED Flat-Panel Display

The focus of this work is the process integration of Indium Gallium Zinc Oxide (IGZO) transistors as a µLED backplane for row/column addressing. A single pixel is composed of a µLED driven by an arrangement of two transistors and a storage capacitor. The pixels are then arrayed on a glass substrate to support active-matrix control of monochrome and full color (RGB) displays from 1x1cm (50 x 50 pixels) up to 7.6 x 7.6 cm (380 x 380 pixels). Optimization of circuit parameters considering size and scan frequency was modeled using existing TFT and µLED electrical device compact models. New process parameters and procedures were determined for the proper integration of µLEDs in an existing TFT fabrication process. Red, green, and blue µLED devices were fabricated at Tyndall National Institute on native substrates and were transferred to TFT pixels using an X-Display MTP-1003 micro-transfer printer. The performance of individual test cells was assessed using an Agilent B1500, revealing a voltage transfer characteristic indicating the ability to modulate and control µLED current.

Substrate temperature effects on PEALD HfAlO dielectric films for IGZO-TFT applications

Aluminum incorporated hafnium oxide (HfAlO) has garnered significant attention due to its high dielectric constant. The present study employs supercycle plasma-enhanced atomic layer deposition (PEALD) to prepare HfAlO films, switching between HfO2 and Al2O3 deposition. The effects of substate temperature on the HfAlO films are systematically investigated. The experimental results indicate that increased substrate temperatures favor Al2O3 growth on HfO2, but excessively high temperatures result in deviated PEALD growth and deteriorated film properties. The PEALD window can be reached at substrate temperatures of 300 to 350 °C. The Al content is substantially affected by the substrate temperature, despite a constant Al2O3 PEALD cycle ratio used. The film deposited at 350 °C exhibits the highest Al content, density, and (111) crystalline orientation ratio, leading to a high breakdown field of 6 MV/cm and a considerable dielectric constant of 27. The HfAlO films are applied to indium gallium zinc oxide transistor as the dielectric layer, and the 350 °C-deposited HfAlO leads to the best device performance with a remarkably high on/off current ratio of 3.5 × 109, low threshold voltage of −0.1 V, saturated mobility of 6.1 cm2 V−1 s−1, and a low subthreshold swing of 76 mV/dec.

Electrolyte-gated amorphous IGZO transistors with extended gates for prostate-specific antigen detection.

The prostate-specific antigen (PSA) test is considered an important way for preoperative diagnosis and accurate screening of prostate cancer. Current antigen detection methods, including radioimmunoassay, enzyme-linked immunosorbent assay and microfluidic electrochemical detection, feature expensive equipment, long testing time and poor stability. Here, we propose a portable biosensor composed of electrolyte-gated amorphous indium gallium zinc oxide (a-IGZO) transistors with an extended gate, which can achieve real-time, instant PSA detection at a low operating voltage (<2 V) owing to the liquid-free ionic conductive elastomer (ICE) serving as the gate dielectric. The electric double layer (EDL) capacitance in ICE enhances the accumulation of carriers in the IGZO channel, leading to strong gate modulation, which enables the IGZO transistor to have a small subthreshold swing (<0.5 V dec-1) and a high on-state current (∼4 × 10-4 A). The separate, biodegradable, and pluggable sensing pad, serving as an extended gate connected to the IGZO transistor, prevents contamination and depletion arising from direct contact with biomolecular buffers, enabling the IGZO transistor to maintain superior electronic performance for at least six months. The threshold voltage and channel current of the transistor exhibit excellent linear response to PSA molecule concentrations across five orders of magnitude ranging from 1 fg mL-1 to 10 pg mL-1, with a detection limit of 400 ag mL-1 and a detection time of ∼5.1 s. The fabricated biosensors offer a point-of-care system for antigen detection, attesting the feasibility of the electrolyte-gated transistors in clinical screening, healthcare diagnostics and biological management.

Nanowire-Enhanced Fully Transparent and Flexible Indium Gallium Zinc Oxide Transistors with Chitosan Hydrogel Gate Dielectric: A Pathway to Improved Synaptic Properties.

In this study, a transparent and flexible synaptic transistor was fabricated based on a random-network nanowire (NW) channel made of indium gallium zinc oxide. This device employs a biocompatible chitosan-based hydrogel as an electrolytic gate dielectric. The NW structure, with its high surface-to-volume ratio, facilitated a more effective modulation of the channel conductance induced by protonic-ion polarization. A comparative analysis of the synaptic properties of NW- and film-type devices revealed the distinctive features of the NW-type configuration. In particular, the NW-type synaptic transistors exhibited a significantly larger hysteresis window under identical gate-bias conditions. Notably, these transistors demonstrated enhanced paired-pulse facilitation properties, synaptic weight modulation, and transition from short- to long-term memory. The NW-type devices displayed gradual potentiation and depression of the channel conductance and thus achieved a broader dynamic range, improved linearity, and reduced power consumption compared with their film-type counterparts. Remarkably, the NW-type synaptic transistors exhibited impressive recognition accuracy outcomes in Modified National Institute of Standards and Technology pattern-recognition simulations. This characteristic enhances the efficiency of practical artificial intelligence (AI) processes. Consequently, the proposed NW-type synaptic transistor is expected to emerge as a superior candidate for use in high-efficiency artificial neural network systems, thus making it a promising technology for next-generation AI semiconductor applications.

Thermal shape morphing of membrane-type electronics based on plastic-elastomer frameworks for 3D electronics with various Gaussian curvatures

This study demonstrates a means of shape morphing planar membrane-type electronic devices into three-dimensional (3D) structures with various Gaussian curvatures using a plastic-elastomer supportive framework consisting of acrylonitrile–butadienestyrene (ABS) lines with tensile stress inside an Ecoflex film. The plastic part, created by extrusion shear printing (ESP), provides the driving force for shape morphing upon thermal annealing, whereas the elastomer part provides a base to mount membrane-type electronic devices and allows a comparably large degree of deformation. To ensure reliable interfacial adhesion in the plastic-elastomer framework, the ABS lines are treated with an allyl-terminated self-assembled monolayer (SAM) for chemical bonding to the Ecoflex layer. To determine control parameters for reliable shape morphing, the annealing conditions (e.g., temperature and time), the printing conditions (e.g., shear rate and pitch), and relative thicknesses of the ABS/Ecoflex are examined. Based on these findings, various 3D structures, including bent, cone, saddle, and dome shapes, can be generated from planar forms using ABS-Ecoflex frameworks, which are also predicted by a mechanical finite element method (FEM) simulation. Furthermore, a metal electrode and a membrane-type indium gallium zinc oxide (IGZO) transistor array are successfully mounted on ABS-Ecoflex frameworks and transformed into curvilinear structures without electrical failure.

Hysteresis and turn-on voltage tailoring of indium gallium zinc oxide transistors by employing a sandwiched structure with indium oxide

• Transistor with ternary oxide semiconductor shows large hysteresis at low voltage. • Hysteresis can be addressed by improving semiconductor-dielectric interface. • Forming a sandwich structure with In 2 O 3 reduces hysteresis. • Turn-on voltage of transistors is controlled via the In 2 O 3 film thickness. Transparent electronics with low power consumption is an important area of research for the display industry. Operating voltages of transistors can be successfully reduced by employing gate dielectrics with high dielectric constants. However, interfacial trap sites between dielectric and semiconductor layers might cause hysteresis. Here, transistors were fabricated using amorphous indium gallium zinc oxide (a-IGZO, molar ratio of In:Ga:Zn 1:1:1), a transparent semiconductor with high electron mobility. When prepared on top of Al 2 O 3 gate dielectric, drain current was found to depend on the direction of the gate sweep. A stacked active layer was prepared with the a-IGZO being sandwiched between In 2 O 3 thin films to mitigate the hysteresis of the device. Moreover, it was found that by varying the In 2 O 3 layer thickness, the device fabrication can be optimized to improve the device-to-device reproducibility of the charge carrier mobility. Additionally, the turn-on voltage, a crucial parameter of transistors in binary logic circuits, improved significantly when using the optimized layer structure.

High-performance inorganic metal halide perovskite transistors

The p-type characteristic of solution-processed metal halide perovskite transistors means that they could be used in combination with their n-type counterparts, such as indium–gallium–zinc-oxide transistors, to create complementary metal–oxide–semiconductor-like circuits. However, the performance and stability of perovskite-based transistors do not yet match their n-type counterparts, which limit their broader application. Here we report high-performance p-channel perovskite thin-film transistors based on inorganic caesium tin triiodide semiconducting layers that have moderate hole concentrations and high Hall mobilities. The perovskite channels are formed by engineering the film composition and crystallization process using a tin-fluoride-modified caesium-iodide-rich precursor with lead substitution. The optimized transistors exhibit field-effect hole mobilities of over 50 cm2 V−1 s−1 and on/off current ratios exceeding 108, as well as high operational stability and reproducibility.

A thin and flexible scanner for fingerprints and documents based on metal halide perovskites

Solution-processed photodetectors could be of use in large-area light-sensing applications because they can be fabricated at low cost on plastic substrates and their absorption spectra can be tuned by chemical design. However, fabricating photodetectors with low dark currents and integrating them into high-resolution backplanes remains challenging. Here we show that solution-processed metal halide perovskite photodiodes on top of an amorphous indium gallium zinc oxide transistor backplane can be used to create a flexible image sensor that is ~100 μm thick and has a resolution of 508 pixels per inch. We have developed a pixel edge cover layer for the system that reduces electrode current leakage and thus dark current density. The low noise current in combination with high external quantum efficiency results in high photodetectivity at wavelengths from 550 nm to 770 nm. We show that our imager can be used for document scanning and biometric fingerprinting and that it can be wrapped around objects with radii as small as 0.6 cm. Low-dark-current perovskite photodetectors can be integrated with an oxide transistor backplane to create a high-resolution optical scanning array capable of imaging flat and curved surfaces.

Construction of high stability indium gallium zinc oxide transistor biosensors for reliable detection of bladder cancer-associated microRNA

Bladder cancer is the most common malignant tumours with high morbidity, mortality and recurrence. However, currently developed detection methods for bladder cancer-associated urine biomarkers are hindered by their extremely low abundance. Hence, the exploration of a highly sensitive and selective approach for the detection of trace bladder cancer-associated biomarkers in human urine is of vital importance for the diagnosis of bladder cancer. Herein, we developed a highly reliable indium gallium zinc oxide field effect transistor (IGZO FET) biosensor for the detection of bladder cancer-related biomarker microRNA. The single-stranded DNA-functionalized IGZO FET biosensors exhibit high sensing reproducibility and stability with an ultralow detection limit of 19.8 amol/L. The device could also be used for quantitative detection of trace microRNA in human urine samples and can effectively distinguish bladder cancer patients from healthy donors. The development of high performance IGZO FET biosensors presents new opportunities for the achievement of early-stage diagnosis of bladder cancer.

Healable Cellulose Iontronic Hydrogel Stickers for Sustainable Electronics on Paper

AbstractNovel nature‐based engineered functional materials combined with sustainable and economically efficient processes are among the great challenges for the future of mankind. In this context, this work presents a new generation of versatile flexible and highly conformable regenerated cellulose hydrogel electrolytes with high ionic conductivity and self‐healing ability, capable of being (re)used in electrical and electrochemical devices. They can be provided in the form of stickers and easily applied as gate dielectric onto flexible indium–gallium–zinc oxide transistors, decreasing the manufacturing complexity. Flexible and low‐voltage (&lt;2.5 V) circuits can be handwritten on‐demand on paper transistors for patterning of conductive/resistive lines. This user‐friendly and simplified manufacturing approach holds potential for fast production of low‐cost, portable, disposable/recyclable, and low‐power ion‐controlled electronics on paper, making it attractive for application in sensors and concepts such as the “Internet‐on‐Things.”

Residual Image Suppression Through Annealing Process of Amorphous Indium Gallium Zinc Oxide Thin Film Transistor for Plastic Organic Light-Emitting Diode Display.

For the evaluation of the residual image suppression, the amorphous indium-gallium-zinc-oxide thin film transistor was manufactured with electric field shield metal on silicon oxide multi-buffer layer, without the need for a silicon crystallization process through the excimer laser process, and is advantageous for the manufacture of large-scale plastic organic light-emitting display. We conducted a study on the propensity to suppress a residual image according to the temperature of the annealing process in amorphous indium gallium zinc oxide. The evaluation divided by the ambient process temperature conditions to measure the change and restoration tendency of the gray current by the black/white current of thin film transistors, and for precise measurement of the current change intervals, the current was analyzed in 0.004 seconds per point. Through the study, residual image of amorphous Indium Gallium Zinc Oxide transistor was found to be suppressed as the temperature of the annealing crystallization increased from 250°C to 325°C, and there was no improvement effect on the 325°C or higher. The trend of threshold voltage shift of thin film transistors according to the two process temperature conditions, 250°C and 325°C, was analyzed by Two sample T analysis method, and the analysis confirmed that the trend of current deterioration is different through p-value 0.007.

Origin of High Current and Illumination Stress Instability in Self-Aligned a-InGaZnO Thin Film Transistors With Al2O3 as High-κ Gate Dielectric

This paper analyzes the effect of high current under illumination stress (HCIS) in self-aligned amorphous indium gallium zinc oxide transistors with Al2O3 as high- $\kappa $ gate dielectric. A negative parallel threshold voltage $({V}_{T}$ ) shift with the appearance of hysteresis $(\Delta {V}_{{hys}})$ is observed after HCIS. In contrast to the double ionized oxygen vacancy ( $\text{V}_{\text O}^{\text 2+}$ ) theory, a peroxide donor theory based on ${ab~ initio}$ calculations is proposed to explain the degradation. Several methods are carried out to support the mechanism, including $\Delta {V}_{{hys}}$ generation, stress recovery behavior and capacitance-voltage ${(C-V)}$ measurements. A linear dependence between initial ${V}_{T}$ and negative ${V}_{T}$ shift is observed that further supports the peroxide theory. This work highlights the importance of evaluating the HCIS for oxide base semiconductor devices.

Automatic Transformation of Membrane‐Type Electronic Devices into Complex 3D Structures via Extrusion Shear Printing and Thermal Relaxation of Acrylonitrile–Butadiene–Styrene Frameworks

AbstractThis work demonstrates a means of automatic transformation from planar electronic devices to desirable 3D forms. The method uses a spatially designed thermoplastic framework created via extrusion shear printing of acrylonitrile–butadiene–styrene (ABS) on a stress‐free ABS film, which can be laminated to a membrane‐type electronic device layer. Thermal annealing above the glass transition temperature allows stress relaxation in the printed polymer chains, resulting in an overall shape transformation of the framework. In addition, the significant reduction in the Young's modulus and the ability of the polymer chains to reflow in the rubbery state release the stress concentration in the electronic device layer, which can be positioned outside the neutral mechanical plane. Electrical analyses and mechanical simulations of a membrane‐type Au electrode and indium gallium zinc oxide transistor arrays before and after transformation confirm the versatility of this method for developing 3D electronic devices based on planar forms.

Improved electrical performance of a sol\u2013gel IGZO transistor with high-k Al2O3 gate dielectric achieved by post annealing

We have explored the effect of post-annealing on the electrical properties of an indium gallium zinc oxide (IGZO) transistor with an Al2O3 bottom gate dielectric, formed by a sol–gel process. The post-annealed IGZO device demonstrated improved electrical performance in terms of threshold variation, on/off ratio, subthreshold swing, and mobility compared to the non-annealed reference device. Capacitance–voltage measurement confirmed that annealing can lead to enhanced capacitance properties due to reduced charge trapping. Depth profile analysis using X-ray photoelectron spectroscopy proved that percentage of both the oxygen vacancy (VO) and the hydroxyl groups (M–OH) within the IGZO/Al2O3 layers, which serve as a charge trapping source, can be substantially reduced by annealing the fabricated transistor device. Furthermore, the undesired degradation of the contact interface between source/drain electrode and the channel, which mainly concerns VO, can be largely prevented by post-annealing. Thus, the facile annealing process also improves the electrical bias stress stability. This simple post annealing approach provides a strategy for realising better performance and reliability of the solid sol–gel oxide transistor.

Novel Tunnel-Contact-Controlled IGZO Thin-Film Transistors with High Tolerance to Geometrical Variability.

Thin insulating layers are used to modulate a depletion region at the source of a thin-film transistor. Bottom contact, staggered-electrode indium gallium zinc oxide transistors with a 3 nm Al2 O3 layer between the semiconductor and Ni source/drain contacts, show behaviors typical of source-gated transistors (SGTs): low saturation voltage (VD_SAT ≈ 3 V), change in VD_SAT with a gate voltage of only 0.12 V V-1 , and flat saturated output characteristics (small dependence of drain current on drain voltage). The transistors show high tolerance to geometry: the saturated current changes only 0.15× for 2-50 µm channels and 2× for 9-45 µm source-gate overlaps. A higher than expected (5×) increase in drain current for a 30 K change in temperature, similar to Schottky-contact SGTs, underlines a more complex device operation than previously theorized. Optimization for increasing intrinsic gain and reducing temperature effects is discussed. These devices complete the portfolio of contact-controlled transistors, comprising devices with Schottky contacts, bulk barrier, or heterojunctions, and now, tunneling insulating layers. The findings should also apply to nanowire transistors, leading to new low-power, robust design approaches as large-scale fabrication techniques with sub-nanometer control mature.

Understanding Electric Double-Layer Gating Based on Ionic Liquids: from Nanoscale to Macroscale.

In electric double-layer transistors (EDLTs), it is well known that the EDL formed by ionic liquids (ILs) can induce an ultrahigh carrier density at the semiconductor surface, compared to solid dielectric. However, the mechanism of device performance is still not fully understood, especially at a molecular level. Here, we evaluate the gating performance of amorphous indium gallium zinc oxide (a-IGZO) transistor coupled with a series of imidazolium-based ILs, using an approach combining of molecular dynamics simulation and finite element modeling. Results reveal that the EDL with different ion structures could produce inhomogeneous electric fields at the solid-electrolyte interface, and the heterogeneity of electric field-induced charge distributions at semiconductor surface could reduce the electrical conductance of a-IGZO during gating process. Meanwhile, a resistance network analysis was adopted to bridge the nanoscopic data with the macroscopic transfer characteristics of IL-gated transistor, and showed that our theoretical results could well estimate the gating performance of practical devices. Thereby, our findings could provide both new concepts and modeling techniques for IL-gated transistors.

A Bottom-Gate Metal–Oxide Thin-Film Transistor With Self-Aligned Source/Drain Regions

Proper driving of a large-area, high-resolution, and high-frame-rate active-matrix display can be hindered by excessive delay along a signal path, such as a scan line. Depending on the transistor architecture, such delay could be dominated by the parasitic overlap capacitance between the gate electrodes and the source/drain (S/D) regions of the address-transistors attached to a scan line. While the capacitance can be minimized by employing a transistor with the edges of the regions self-aligned (SA) to those of the electrode, actual implementation is easier with a top-gate rather than the more commonly deployed bottom-gate architecture. Presently reported is the realization and characterization of a bottom-gate, SA indium–gallium–zinc oxide transistor. The extent of the overlap between the S/D and the gate is determined by a thermal “activation” process, similar to how it is controlled in a conventional top-gate, SA transistor.

Nitroacetylacetone as a Cofuel for the Combustion Synthesis of High-Performance Indium–Gallium–Zinc Oxide Transistors

Thin-film combustion synthesis has been utilized for the fabrication of solution processed high-performance metal-oxide thin-film transistors (MOTFTs) at lower temperatures than conventional sol–gel processes. The fuel-oxidizer ensemble in the MO precursor solution/film plays an important role in achieving high-efficiency and low-residual combustion byproducts. However, unlike conventional bulk combustion, only a very limited number of thin-film fuels have been investigated. Here we report the use of an efficient new cofuel, 3-nitroacetylacetone (NAcAcH), incorporating a −NO2 group, for the combustion synthesis of display-relevant indium–gallium–zinc-oxide (IGZO) thin films. Compared to the traditional acetylacetone (AcAcH) fuel, a higher enthalpy of combustion (988.6 vs 784.4 J/g) and a lower ignition temperature (107.8 vs 166.5 °C) are achieved for NAcAcH-based formulations. The resulting NAcAcH-derived IGZO TFTs exhibit far higher average electron mobilities (5.7 cm2 V–1 s–1) than AcAcH-derived TFTs (2...

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices.

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal-insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment and theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.

High Mobility Flexible Amorphous IGZO Thin-Film Transistors with a Low Thermal Budget Ultra-Violet Pulsed Light Process.

Amorphous, sol-gel processed, indium gallium zinc oxide (IGZO) transistors on plastic substrate with a printable gate dielectric and an electron mobility of 4.5 cm2/(V s), as well as a mobility of 7 cm2/(V s) on solid substrate (Si/SiO2) are reported. These performances are obtained using a low temperature pulsed light annealing technique. Ultraviolet (UV) pulsed light system is an innovative technique compared to conventional (furnace or hot-plate) annealing process that we successfully implemented on sol-gel IGZO thin film transistors (TFTs) made on plastic substrate. The photonic annealing treatment has been optimized to obtain IGZO TFTs with significant electrical properties. Organic gate dielectric layers deposited on this pulsed UV light annealed films have also been optimized. This technique is very promising for the development of amorphous IGZO TFTs on plastic substrates.